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c59e1b4d | 1 | /* |
3d7506fa | 2 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
c59e1b4d TT |
3 | * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
4 | * Timur Tabi <timur@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
c59e1b4d TT |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include "../board/freescale/common/ics307_clk.h" | |
13 | ||
840a5182 TY |
14 | #define CONFIG_DISPLAY_BOARDINFO |
15 | ||
9899ac19 JY |
16 | #ifdef CONFIG_36BIT |
17 | #define CONFIG_PHYS_64BIT | |
18 | #endif | |
19 | ||
af253608 | 20 | #ifdef CONFIG_SDCARD |
7c8eea59 YZ |
21 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
22 | #define CONFIG_SPL_ENV_SUPPORT | |
23 | #define CONFIG_SPL_SERIAL_SUPPORT | |
24 | #define CONFIG_SPL_MMC_SUPPORT | |
25 | #define CONFIG_SPL_MMC_MINIMAL | |
26 | #define CONFIG_SPL_FLUSH_IMAGE | |
27 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
28 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
29 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
30 | #define CONFIG_SPL_I2C_SUPPORT | |
31 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
32 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
33 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
ee4d6511 YZ |
34 | #define CONFIG_SPL_PAD_TO 0x20000 |
35 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
e222b1f3 | 36 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
7c8eea59 YZ |
37 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
38 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
ee4d6511 | 39 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) |
7c8eea59 YZ |
40 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
41 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
42 | #define CONFIG_SPL_MMC_BOOT | |
43 | #ifdef CONFIG_SPL_BUILD | |
44 | #define CONFIG_SPL_COMMON_INIT_DDR | |
45 | #endif | |
af253608 MM |
46 | #endif |
47 | ||
48 | #ifdef CONFIG_SPIFLASH | |
382ce7e9 YZ |
49 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
50 | #define CONFIG_SPL_ENV_SUPPORT | |
51 | #define CONFIG_SPL_SERIAL_SUPPORT | |
52 | #define CONFIG_SPL_SPI_SUPPORT | |
53 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
54 | #define CONFIG_SPL_SPI_FLASH_MINIMAL | |
55 | #define CONFIG_SPL_FLUSH_IMAGE | |
56 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
57 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
58 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
59 | #define CONFIG_SPL_I2C_SUPPORT | |
60 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
61 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
62 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
ee4d6511 YZ |
63 | #define CONFIG_SPL_PAD_TO 0x20000 |
64 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
e222b1f3 | 65 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
382ce7e9 YZ |
66 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
67 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
ee4d6511 | 68 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
382ce7e9 YZ |
69 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
70 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
71 | #define CONFIG_SPL_SPI_BOOT | |
72 | #ifdef CONFIG_SPL_BUILD | |
73 | #define CONFIG_SPL_COMMON_INIT_DDR | |
74 | #endif | |
af253608 MM |
75 | #endif |
76 | ||
f45210d6 | 77 | #define CONFIG_NAND_FSL_ELBC |
9407c3fc YS |
78 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
79 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 | |
f45210d6 MM |
80 | |
81 | #ifdef CONFIG_NAND | |
5d97fe2a YZ |
82 | #ifdef CONFIG_TPL_BUILD |
83 | #define CONFIG_SPL_NAND_BOOT | |
84 | #define CONFIG_SPL_FLUSH_IMAGE | |
85 | #define CONFIG_SPL_ENV_SUPPORT | |
86 | #define CONFIG_SPL_NAND_INIT | |
87 | #define CONFIG_SPL_SERIAL_SUPPORT | |
88 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
89 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
90 | #define CONFIG_SPL_I2C_SUPPORT | |
91 | #define CONFIG_SPL_NAND_SUPPORT | |
92 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
93 | #define CONFIG_SPL_COMMON_INIT_DDR | |
94 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
95 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
96 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
e222b1f3 | 97 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
5d97fe2a YZ |
98 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
99 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
100 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
101 | #elif defined(CONFIG_SPL_BUILD) | |
f45210d6 MM |
102 | #define CONFIG_SPL_INIT_MINIMAL |
103 | #define CONFIG_SPL_SERIAL_SUPPORT | |
104 | #define CONFIG_SPL_NAND_SUPPORT | |
f45210d6 | 105 | #define CONFIG_SPL_FLUSH_IMAGE |
5d97fe2a YZ |
106 | #define CONFIG_SPL_TEXT_BASE 0xff800000 |
107 | #define CONFIG_SPL_MAX_SIZE 4096 | |
108 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
109 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
110 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
111 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
112 | #endif | |
113 | #define CONFIG_SPL_PAD_TO 0x20000 | |
114 | #define CONFIG_TPL_PAD_TO 0x20000 | |
115 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
116 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
117 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
f45210d6 MM |
118 | #endif |
119 | ||
c59e1b4d TT |
120 | /* High Level Configuration Options */ |
121 | #define CONFIG_BOOKE /* BOOKE */ | |
122 | #define CONFIG_E500 /* BOOKE e500 family */ | |
c59e1b4d TT |
123 | #define CONFIG_P1022 |
124 | #define CONFIG_P1022DS | |
125 | #define CONFIG_MP /* support multiple processors */ | |
126 | ||
2ae18241 | 127 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 128 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
2ae18241 WD |
129 | #endif |
130 | ||
7a577fda KG |
131 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
132 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
133 | #endif | |
134 | ||
c59e1b4d TT |
135 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ |
136 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
137 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
138 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
139 | #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ | |
140 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
141 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
142 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
143 | ||
c59e1b4d | 144 | #define CONFIG_ENABLE_36BIT_PHYS |
babb348c TT |
145 | |
146 | #ifdef CONFIG_PHYS_64BIT | |
c59e1b4d TT |
147 | #define CONFIG_ADDR_MAP |
148 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
9899ac19 | 149 | #endif |
c59e1b4d TT |
150 | |
151 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
152 | ||
153 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
154 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
155 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ | |
156 | ||
157 | /* | |
158 | * These can be toggled for performance analysis, otherwise use default. | |
159 | */ | |
160 | #define CONFIG_L2_CACHE | |
161 | #define CONFIG_BTB | |
162 | ||
163 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | |
164 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
165 | ||
e46fedfe TT |
166 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
167 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
c59e1b4d | 168 | |
f45210d6 MM |
169 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k |
170 | SPL code*/ | |
171 | #ifdef CONFIG_SPL_BUILD | |
172 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
173 | #endif | |
174 | ||
175 | ||
c59e1b4d TT |
176 | /* DDR Setup */ |
177 | #define CONFIG_DDR_SPD | |
178 | #define CONFIG_VERY_BIG_RAM | |
5614e71b | 179 | #define CONFIG_SYS_FSL_DDR3 |
c59e1b4d TT |
180 | |
181 | #ifdef CONFIG_DDR_ECC | |
182 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
183 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
184 | #endif | |
185 | ||
186 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
187 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
188 | ||
189 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
190 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
191 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
192 | ||
193 | /* I2C addresses of SPD EEPROMs */ | |
194 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
c39f44dc | 195 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
c59e1b4d | 196 | |
f45210d6 MM |
197 | /* These are used when DDR doesn't use SPD. */ |
198 | #define CONFIG_SYS_SDRAM_SIZE 2048 | |
199 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G | |
200 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
201 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
202 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F | |
203 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 | |
204 | #define CONFIG_SYS_DDR_TIMING_3 0x00010000 | |
205 | #define CONFIG_SYS_DDR_TIMING_0 0x40110104 | |
206 | #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 | |
207 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca | |
208 | #define CONFIG_SYS_DDR_MODE_1 0x00441221 | |
209 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
210 | #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 | |
211 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
212 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 | |
213 | #define CONFIG_SYS_DDR_CONTROL 0xc7000008 | |
214 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 | |
215 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
216 | #define CONFIG_SYS_DDR_TIMING_5 0x02401400 | |
217 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
218 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 | |
219 | ||
220 | ||
c59e1b4d TT |
221 | /* |
222 | * Memory map | |
223 | * | |
224 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
225 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable | |
226 | * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable | |
227 | * | |
228 | * Localbus cacheable (TBD) | |
229 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
230 | * | |
231 | * Localbus non-cacheable | |
232 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
233 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
f45210d6 | 234 | * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable |
c59e1b4d TT |
235 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
236 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
237 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
238 | */ | |
239 | ||
240 | /* | |
241 | * Local Bus Definitions | |
242 | */ | |
f45210d6 | 243 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ |
9899ac19 | 244 | #ifdef CONFIG_PHYS_64BIT |
f45210d6 | 245 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull |
9899ac19 JY |
246 | #else |
247 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
248 | #endif | |
c59e1b4d TT |
249 | |
250 | #define CONFIG_FLASH_BR_PRELIM \ | |
f45210d6 | 251 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
c59e1b4d TT |
252 | #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) |
253 | ||
f45210d6 MM |
254 | #ifdef CONFIG_NAND |
255 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
256 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
257 | #else | |
c59e1b4d TT |
258 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
259 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
f45210d6 | 260 | #endif |
c59e1b4d | 261 | |
f45210d6 | 262 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
c59e1b4d TT |
263 | #define CONFIG_SYS_FLASH_QUIET_TEST |
264 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
265 | ||
f45210d6 | 266 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
c59e1b4d TT |
267 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
268 | ||
f45210d6 MM |
269 | #ifndef CONFIG_SYS_MONITOR_BASE |
270 | #ifdef CONFIG_SPL_BUILD | |
271 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
272 | #else | |
14d0a02a | 273 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
f45210d6 MM |
274 | #endif |
275 | #endif | |
c59e1b4d TT |
276 | |
277 | #define CONFIG_FLASH_CFI_DRIVER | |
278 | #define CONFIG_SYS_FLASH_CFI | |
279 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
280 | ||
f45210d6 MM |
281 | /* Nand Flash */ |
282 | #if defined(CONFIG_NAND_FSL_ELBC) | |
283 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
284 | #ifdef CONFIG_PHYS_64BIT | |
285 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
286 | #else | |
287 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
288 | #endif | |
289 | ||
5d97fe2a | 290 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
f45210d6 | 291 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
f45210d6 | 292 | #define CONFIG_CMD_NAND 1 |
5d97fe2a | 293 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) |
f45210d6 MM |
294 | #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE |
295 | ||
296 | /* NAND flash config */ | |
297 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
298 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
299 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
300 | | BR_MS_FCM /* MSEL = FCM */ \ | |
301 | | BR_V) /* valid */ | |
302 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ | |
303 | | OR_FCM_PGS /* Large Page*/ \ | |
304 | | OR_FCM_CSCT \ | |
305 | | OR_FCM_CST \ | |
306 | | OR_FCM_CHT \ | |
307 | | OR_FCM_SCY_1 \ | |
308 | | OR_FCM_TRLX \ | |
309 | | OR_FCM_EHTR) | |
310 | #ifdef CONFIG_NAND | |
311 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
312 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
313 | #else | |
314 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
315 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
316 | #endif | |
317 | ||
318 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
319 | ||
c59e1b4d TT |
320 | #define CONFIG_BOARD_EARLY_INIT_F |
321 | #define CONFIG_BOARD_EARLY_INIT_R | |
322 | #define CONFIG_MISC_INIT_R | |
a2d12f88 | 323 | #define CONFIG_HWCONFIG |
c59e1b4d TT |
324 | |
325 | #define CONFIG_FSL_NGPIXIS | |
326 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
9899ac19 | 327 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 328 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
9899ac19 JY |
329 | #else |
330 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
331 | #endif | |
c59e1b4d TT |
332 | |
333 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
334 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) | |
335 | ||
336 | #define PIXIS_LBMAP_SWITCH 7 | |
2906845a | 337 | #define PIXIS_LBMAP_MASK 0xF0 |
c59e1b4d | 338 | #define PIXIS_LBMAP_ALTBANK 0x20 |
f45210d6 MM |
339 | #define PIXIS_SPD 0x07 |
340 | #define PIXIS_SPD_SYSCLK_MASK 0x07 | |
9b6e9d1c JY |
341 | #define PIXIS_ELBC_SPI_MASK 0xc0 |
342 | #define PIXIS_SPI 0x80 | |
c59e1b4d TT |
343 | |
344 | #define CONFIG_SYS_INIT_RAM_LOCK | |
345 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 346 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
c59e1b4d | 347 | |
c59e1b4d | 348 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 349 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
c59e1b4d TT |
350 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
351 | ||
9307cbab | 352 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
07b5edc2 | 353 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
c59e1b4d | 354 | |
7c8eea59 YZ |
355 | /* |
356 | * Config the L2 Cache as L2 SRAM | |
357 | */ | |
358 | #if defined(CONFIG_SPL_BUILD) | |
382ce7e9 | 359 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
7c8eea59 YZ |
360 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
361 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
362 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
363 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
364 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
27585bd3 | 365 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
7c8eea59 | 366 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) |
27585bd3 YZ |
367 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) |
368 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) | |
7c8eea59 | 369 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
5d97fe2a YZ |
370 | #elif defined(CONFIG_NAND) |
371 | #ifdef CONFIG_TPL_BUILD | |
372 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
373 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
374 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
375 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
376 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
377 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
378 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
379 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
380 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
381 | #else | |
382 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
383 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
384 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
385 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
386 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) | |
387 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
388 | #endif | |
7c8eea59 YZ |
389 | #endif |
390 | #endif | |
391 | ||
c59e1b4d TT |
392 | /* |
393 | * Serial Port | |
394 | */ | |
395 | #define CONFIG_CONS_INDEX 1 | |
c59e1b4d TT |
396 | #define CONFIG_SYS_NS16550_SERIAL |
397 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
398 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
7c8eea59 | 399 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
f45210d6 MM |
400 | #define CONFIG_NS16550_MIN_FUNCTIONS |
401 | #endif | |
c59e1b4d TT |
402 | |
403 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
404 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
405 | ||
406 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
407 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
408 | ||
409 | /* Use the HUSH parser */ | |
410 | #define CONFIG_SYS_HUSH_PARSER | |
c59e1b4d | 411 | |
c59e1b4d | 412 | /* Video */ |
ba8e76bd | 413 | |
d5e01e49 TT |
414 | #ifdef CONFIG_FSL_DIU_FB |
415 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) | |
416 | #define CONFIG_VIDEO | |
417 | #define CONFIG_CMD_BMP | |
c59e1b4d | 418 | #define CONFIG_CFB_CONSOLE |
7d3053fb | 419 | #define CONFIG_VIDEO_SW_CURSOR |
c59e1b4d | 420 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
d5e01e49 TT |
421 | #define CONFIG_VIDEO_LOGO |
422 | #define CONFIG_VIDEO_BMP_LOGO | |
55b05237 TT |
423 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
424 | /* | |
425 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
426 | * disable empty flash sector detection, which is I/O-intensive. | |
427 | */ | |
428 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
c59e1b4d TT |
429 | #endif |
430 | ||
ba8e76bd | 431 | #ifndef CONFIG_FSL_DIU_FB |
218a758f JY |
432 | #endif |
433 | ||
434 | #ifdef CONFIG_ATI | |
435 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
436 | #define CONFIG_VIDEO | |
437 | #define CONFIG_BIOSEMU | |
438 | #define CONFIG_VIDEO_SW_CURSOR | |
439 | #define CONFIG_ATI_RADEON_FB | |
440 | #define CONFIG_VIDEO_LOGO | |
441 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
442 | #define CONFIG_CFB_CONSOLE | |
443 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
444 | #endif | |
445 | ||
c59e1b4d TT |
446 | /* |
447 | * Pass open firmware flat tree | |
448 | */ | |
c59e1b4d TT |
449 | #define CONFIG_OF_BOARD_SETUP |
450 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
451 | ||
452 | /* new uImage format support */ | |
453 | #define CONFIG_FIT | |
454 | #define CONFIG_FIT_VERBOSE | |
455 | ||
456 | /* I2C */ | |
00f792e0 HS |
457 | #define CONFIG_SYS_I2C |
458 | #define CONFIG_SYS_I2C_FSL | |
459 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
460 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
461 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
462 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
463 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
464 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
c59e1b4d | 465 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} |
c59e1b4d TT |
466 | |
467 | /* | |
468 | * I2C2 EEPROM | |
469 | */ | |
470 | #define CONFIG_ID_EEPROM | |
471 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
472 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
473 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
474 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
475 | ||
9b6e9d1c JY |
476 | /* |
477 | * eSPI - Enhanced SPI | |
478 | */ | |
9b6e9d1c JY |
479 | |
480 | #define CONFIG_HARD_SPI | |
9b6e9d1c JY |
481 | |
482 | #define CONFIG_CMD_SF | |
483 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
484 | #define CONFIG_SF_DEFAULT_MODE 0 | |
485 | ||
c59e1b4d TT |
486 | /* |
487 | * General PCI | |
488 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
489 | */ | |
490 | ||
491 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
492 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
9899ac19 | 493 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
494 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
495 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull | |
9899ac19 JY |
496 | #else |
497 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
498 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
499 | #endif | |
c59e1b4d TT |
500 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
501 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
502 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
9899ac19 | 503 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 504 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
9899ac19 JY |
505 | #else |
506 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
507 | #endif | |
c59e1b4d TT |
508 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
509 | ||
510 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
511 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
9899ac19 | 512 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
513 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
514 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
9899ac19 JY |
515 | #else |
516 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
517 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
518 | #endif | |
c59e1b4d TT |
519 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
520 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
521 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
9899ac19 | 522 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 523 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
9899ac19 JY |
524 | #else |
525 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
526 | #endif | |
c59e1b4d TT |
527 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
528 | ||
529 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
530 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
9899ac19 | 531 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d TT |
532 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
533 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull | |
9899ac19 JY |
534 | #else |
535 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
536 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
537 | #endif | |
c59e1b4d TT |
538 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
539 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
540 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
9899ac19 | 541 | #ifdef CONFIG_PHYS_64BIT |
c59e1b4d | 542 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
9899ac19 JY |
543 | #else |
544 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
545 | #endif | |
c59e1b4d TT |
546 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
547 | ||
548 | #ifdef CONFIG_PCI | |
842033e6 | 549 | #define CONFIG_PCI_INDIRECT_BRIDGE |
c59e1b4d TT |
550 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
551 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
552 | #endif | |
553 | ||
554 | /* SATA */ | |
555 | #define CONFIG_LIBATA | |
556 | #define CONFIG_FSL_SATA | |
9760b274 | 557 | #define CONFIG_FSL_SATA_V2 |
c59e1b4d TT |
558 | |
559 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
560 | #define CONFIG_SATA1 | |
561 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
562 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
563 | #define CONFIG_SATA2 | |
564 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
565 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
566 | ||
567 | #ifdef CONFIG_FSL_SATA | |
568 | #define CONFIG_LBA48 | |
569 | #define CONFIG_CMD_SATA | |
570 | #define CONFIG_DOS_PARTITION | |
571 | #define CONFIG_CMD_EXT2 | |
572 | #endif | |
573 | ||
574 | #define CONFIG_MMC | |
575 | #ifdef CONFIG_MMC | |
576 | #define CONFIG_CMD_MMC | |
577 | #define CONFIG_FSL_ESDHC | |
578 | #define CONFIG_GENERIC_MMC | |
579 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
580 | #endif | |
581 | ||
582 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
583 | #define CONFIG_CMD_EXT2 | |
584 | #define CONFIG_CMD_FAT | |
585 | #define CONFIG_DOS_PARTITION | |
586 | #endif | |
587 | ||
588 | #define CONFIG_TSEC_ENET | |
589 | #ifdef CONFIG_TSEC_ENET | |
590 | ||
591 | #define CONFIG_TSECV2 | |
c59e1b4d TT |
592 | |
593 | #define CONFIG_MII /* MII PHY management */ | |
594 | #define CONFIG_TSEC1 1 | |
595 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
596 | #define CONFIG_TSEC2 1 | |
597 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
598 | ||
599 | #define TSEC1_PHY_ADDR 1 | |
600 | #define TSEC2_PHY_ADDR 2 | |
601 | ||
602 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
603 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
604 | ||
605 | #define TSEC1_PHYIDX 0 | |
606 | #define TSEC2_PHYIDX 0 | |
607 | ||
608 | #define CONFIG_ETHPRIME "eTSEC1" | |
609 | ||
610 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
611 | #endif | |
612 | ||
94b383e7 YL |
613 | /* |
614 | * Dynamic MTD Partition support with mtdparts | |
615 | */ | |
616 | #define CONFIG_MTD_DEVICE | |
617 | #define CONFIG_MTD_PARTITIONS | |
618 | #define CONFIG_CMD_MTDPARTS | |
619 | #define CONFIG_FLASH_CFI_MTD | |
620 | #ifdef CONFIG_PHYS_64BIT | |
621 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor" | |
622 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ | |
623 | "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ | |
624 | "512k(dtb),768k(u-boot)" | |
625 | #else | |
626 | #define MTDIDS_DEFAULT "nor0=e8000000.nor" | |
627 | #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ | |
628 | "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ | |
629 | "512k(dtb),768k(u-boot)" | |
630 | #endif | |
631 | ||
c59e1b4d TT |
632 | /* |
633 | * Environment | |
634 | */ | |
382ce7e9 | 635 | #ifdef CONFIG_SPIFLASH |
af253608 MM |
636 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
637 | #define CONFIG_ENV_SPI_BUS 0 | |
638 | #define CONFIG_ENV_SPI_CS 0 | |
639 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
640 | #define CONFIG_ENV_SPI_MODE 0 | |
641 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
642 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
643 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
7c8eea59 | 644 | #elif defined(CONFIG_SDCARD) |
af253608 | 645 | #define CONFIG_ENV_IS_IN_MMC |
7c8eea59 | 646 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
af253608 MM |
647 | #define CONFIG_ENV_SIZE 0x2000 |
648 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
f45210d6 | 649 | #elif defined(CONFIG_NAND) |
5d97fe2a YZ |
650 | #ifdef CONFIG_TPL_BUILD |
651 | #define CONFIG_ENV_SIZE 0x2000 | |
652 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
653 | #else | |
af253608 | 654 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
5d97fe2a YZ |
655 | #endif |
656 | #define CONFIG_ENV_IS_IN_NAND | |
657 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
af253608 | 658 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
f45210d6 | 659 | #elif defined(CONFIG_SYS_RAMBOOT) |
af253608 MM |
660 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
661 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
662 | #define CONFIG_ENV_SIZE 0x2000 | |
af253608 | 663 | #else |
c59e1b4d | 664 | #define CONFIG_ENV_IS_IN_FLASH |
af253608 | 665 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
c59e1b4d | 666 | #define CONFIG_ENV_SIZE 0x2000 |
af253608 MM |
667 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
668 | #endif | |
c59e1b4d TT |
669 | |
670 | #define CONFIG_LOADS_ECHO | |
671 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
672 | ||
673 | /* | |
674 | * Command line configuration. | |
675 | */ | |
79ee3448 | 676 | #define CONFIG_CMD_ERRATA |
c59e1b4d | 677 | #define CONFIG_CMD_IRQ |
c59e1b4d TT |
678 | #define CONFIG_CMD_I2C |
679 | #define CONFIG_CMD_MII | |
79ee3448 | 680 | #define CONFIG_CMD_PING |
b8339e2b | 681 | #define CONFIG_CMD_REGINFO |
c59e1b4d TT |
682 | |
683 | #ifdef CONFIG_PCI | |
684 | #define CONFIG_CMD_PCI | |
c59e1b4d TT |
685 | #endif |
686 | ||
687 | /* | |
688 | * USB | |
689 | */ | |
3d7506fa | 690 | #define CONFIG_HAS_FSL_DR_USB |
691 | #ifdef CONFIG_HAS_FSL_DR_USB | |
c59e1b4d TT |
692 | #define CONFIG_USB_EHCI |
693 | ||
694 | #ifdef CONFIG_USB_EHCI | |
695 | #define CONFIG_CMD_USB | |
696 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
697 | #define CONFIG_USB_EHCI_FSL | |
698 | #define CONFIG_USB_STORAGE | |
699 | #define CONFIG_CMD_FAT | |
700 | #endif | |
3d7506fa | 701 | #endif |
c59e1b4d TT |
702 | |
703 | /* | |
704 | * Miscellaneous configurable options | |
705 | */ | |
706 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
707 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
5be58f5f | 708 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
c59e1b4d | 709 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
c59e1b4d TT |
710 | #ifdef CONFIG_CMD_KGDB |
711 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
712 | #else | |
713 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
714 | #endif | |
715 | /* Print Buffer Size */ | |
716 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
717 | #define CONFIG_SYS_MAXARGS 16 | |
718 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
c59e1b4d TT |
719 | |
720 | /* | |
721 | * For booting Linux, the board info and command line data | |
a832ac41 | 722 | * have to be in the first 64 MB of memory, since this is |
c59e1b4d TT |
723 | * the maximum mapped by the Linux kernel during initialization. |
724 | */ | |
a832ac41 KG |
725 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
726 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
c59e1b4d | 727 | |
c59e1b4d TT |
728 | #ifdef CONFIG_CMD_KGDB |
729 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
c59e1b4d TT |
730 | #endif |
731 | ||
732 | /* | |
733 | * Environment Configuration | |
734 | */ | |
735 | ||
736 | #define CONFIG_HOSTNAME p1022ds | |
8b3637c6 | 737 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 738 | #define CONFIG_BOOTFILE "uImage" |
c59e1b4d TT |
739 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
740 | ||
741 | #define CONFIG_LOADADDR 1000000 | |
742 | ||
743 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
c59e1b4d TT |
744 | |
745 | #define CONFIG_BAUDRATE 115200 | |
746 | ||
84e34b65 TT |
747 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
748 | "netdev=eth0\0" \ | |
5368c55d MV |
749 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
750 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
84e34b65 TT |
751 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
752 | "protect off $ubootaddr +$filesize && " \ | |
753 | "erase $ubootaddr +$filesize && " \ | |
754 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
755 | "protect on $ubootaddr +$filesize && " \ | |
756 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
757 | "consoledev=ttyS0\0" \ | |
758 | "ramdiskaddr=2000000\0" \ | |
759 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
760 | "fdtaddr=c00000\0" \ | |
761 | "fdtfile=p1022ds.dtb\0" \ | |
762 | "bdev=sda3\0" \ | |
ba8e76bd | 763 | "hwconfig=esdhc;audclk:12\0" |
c59e1b4d TT |
764 | |
765 | #define CONFIG_HDBOOT \ | |
766 | "setenv bootargs root=/dev/$bdev rw " \ | |
84e34b65 | 767 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
768 | "tftp $loadaddr $bootfile;" \ |
769 | "tftp $fdtaddr $fdtfile;" \ | |
770 | "bootm $loadaddr - $fdtaddr" | |
771 | ||
772 | #define CONFIG_NFSBOOTCOMMAND \ | |
773 | "setenv bootargs root=/dev/nfs rw " \ | |
774 | "nfsroot=$serverip:$rootpath " \ | |
775 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
84e34b65 | 776 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
777 | "tftp $loadaddr $bootfile;" \ |
778 | "tftp $fdtaddr $fdtfile;" \ | |
779 | "bootm $loadaddr - $fdtaddr" | |
780 | ||
781 | #define CONFIG_RAMBOOTCOMMAND \ | |
782 | "setenv bootargs root=/dev/ram rw " \ | |
84e34b65 | 783 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
c59e1b4d TT |
784 | "tftp $ramdiskaddr $ramdiskfile;" \ |
785 | "tftp $loadaddr $bootfile;" \ | |
786 | "tftp $fdtaddr $fdtfile;" \ | |
787 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
788 | ||
789 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
790 | ||
791 | #endif |