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feb7838f | 1 | /* |
3d7506fa | 2 | * Copyright 2007-2012 Freescale Semiconductor, Inc. |
feb7838f SS |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * p2020ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
ebf9d526 KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_36BIT |
a0f9e0e0 KG |
33 | #define CONFIG_PHYS_64BIT |
34 | #endif | |
35 | ||
1ac63e40 JH |
36 | #ifdef CONFIG_SDCARD |
37 | #define CONFIG_SYS_RAMBOOT | |
38 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
39 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 | |
40 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
41 | #endif | |
42 | ||
21dd9af3 JH |
43 | #ifdef CONFIG_SPIFLASH |
44 | #define CONFIG_SYS_RAMBOOT | |
45 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
46 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 | |
47 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
48 | #endif | |
49 | ||
feb7838f SS |
50 | /* High Level Configuration Options */ |
51 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
52 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
53 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
54 | #define CONFIG_P2020 1 | |
55 | #define CONFIG_P2020DS 1 | |
56 | #define CONFIG_MP 1 /* support multiple processors */ | |
feb7838f | 57 | |
2ae18241 WD |
58 | #ifndef CONFIG_SYS_TEXT_BASE |
59 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
60 | #endif | |
61 | ||
7a577fda KG |
62 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
63 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
64 | #endif | |
65 | ||
28a096e7 LY |
66 | #define CONFIG_SYS_SRIO |
67 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
68 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
69 | ||
feb7838f SS |
70 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
71 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
72 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
73 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
74 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
75 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 76 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
feb7838f SS |
77 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
78 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
79 | ||
80 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
29c35182 | 81 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
feb7838f SS |
82 | |
83 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
84 | #define CONFIG_ENV_OVERWRITE | |
85 | ||
ebf9d526 KG |
86 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
87 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
feb7838f | 88 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
feb7838f SS |
89 | |
90 | /* | |
91 | * These can be toggled for performance analysis, otherwise use default. | |
92 | */ | |
93 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
94 | #define CONFIG_BTB /* toggle branch predition */ | |
95 | ||
9c4d8767 JH |
96 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
97 | ||
feb7838f SS |
98 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
99 | ||
100 | #ifdef CONFIG_PHYS_64BIT | |
101 | #define CONFIG_ADDR_MAP 1 | |
102 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
103 | #endif | |
104 | ||
84bc0030 YS |
105 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
106 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
107 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
feb7838f SS |
108 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
109 | ||
1ac63e40 JH |
110 | /* |
111 | * Config the L2 Cache | |
112 | */ | |
113 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
114 | #ifdef CONFIG_PHYS_64BIT | |
115 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
116 | #else | |
117 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
118 | #endif | |
119 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
120 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
121 | ||
e46fedfe TT |
122 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
123 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
feb7838f | 124 | |
feb7838f | 125 | /* DDR Setup */ |
feb7838f | 126 | #define CONFIG_VERY_BIG_RAM |
d24f2d32 | 127 | #ifdef CONFIG_DDR2 |
394c46ca YS |
128 | #define CONFIG_FSL_DDR2 |
129 | #else | |
feb7838f | 130 | #define CONFIG_FSL_DDR3 1 |
394c46ca | 131 | #endif |
feb7838f | 132 | |
8e5e9b94 WD |
133 | /* ECC will be enabled based on perf_mode environment variable */ |
134 | /* #define CONFIG_DDR_ECC */ | |
135 | ||
feb7838f SS |
136 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
137 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
138 | ||
139 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
140 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
141 | ||
142 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
143 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
144 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
145 | ||
146 | /* I2C addresses of SPD EEPROMs */ | |
394c46ca | 147 | #define CONFIG_DDR_SPD |
feb7838f | 148 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
c39f44dc | 149 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
feb7838f SS |
150 | |
151 | /* These are used when DDR doesn't use SPD. */ | |
feb7838f SS |
152 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
153 | ||
154 | /* Default settings for "stable" mode */ | |
155 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
156 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
157 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
158 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
159 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
160 | #define CONFIG_SYS_DDR_TIMING_0 0x00330804 | |
161 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 | |
162 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 | |
163 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 | |
164 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
165 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 | |
166 | #define CONFIG_SYS_DDR_INTERVAL 0x61800100 | |
167 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
168 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 | |
169 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
170 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
171 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
172 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 | |
173 | #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ | |
174 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 | |
175 | #define CONFIG_SYS_DDR_CDR1 0x00040000 | |
176 | #define CONFIG_SYS_DDR_CDR2 0x00000000 | |
177 | ||
178 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
179 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
180 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
181 | ||
182 | /* Settings that differ for "performance" mode */ | |
183 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ | |
184 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ | |
185 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 | |
186 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 | |
187 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce | |
188 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ | |
189 | ||
190 | /* | |
191 | * The following set of values were tested for DDR2 | |
192 | * with a DDR3 to DDR2 interposer | |
193 | * | |
194 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
195 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
196 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
197 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
198 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
199 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
200 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
201 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
202 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
203 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
204 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
205 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 | |
206 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
207 | * | |
208 | */ | |
209 | ||
feb7838f SS |
210 | /* |
211 | * Memory map | |
212 | * | |
213 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
214 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
215 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
216 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
217 | * | |
218 | * Localbus cacheable (TBD) | |
219 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
220 | * | |
221 | * Localbus non-cacheable | |
222 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
223 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
224 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
225 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 | |
226 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
227 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
228 | */ | |
229 | ||
230 | /* | |
231 | * Local Bus Definitions | |
232 | */ | |
233 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ | |
234 | #ifdef CONFIG_PHYS_64BIT | |
235 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
236 | #else | |
237 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
238 | #endif | |
239 | ||
7ee41107 TT |
240 | #define CONFIG_FLASH_BR_PRELIM \ |
241 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) | |
feb7838f SS |
242 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
243 | ||
244 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
245 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
246 | ||
247 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
248 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
249 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
250 | ||
251 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
252 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
feb7838f SS |
253 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
254 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
255 | ||
14d0a02a | 256 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
feb7838f SS |
257 | |
258 | #define CONFIG_FLASH_CFI_DRIVER | |
259 | #define CONFIG_SYS_FLASH_CFI | |
260 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
261 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
262 | ||
263 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
264 | ||
394c46ca | 265 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
5a469608 TT |
266 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
267 | ||
268 | #ifdef CONFIG_FSL_NGPIXIS | |
feb7838f SS |
269 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
270 | #ifdef CONFIG_PHYS_64BIT | |
271 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
272 | #else | |
273 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
274 | #endif | |
275 | ||
276 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
277 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
278 | ||
5a469608 TT |
279 | #define PIXIS_LBMAP_SWITCH 7 |
280 | #define PIXIS_LBMAP_MASK 0xf0 | |
281 | #define PIXIS_LBMAP_SHIFT 4 | |
282 | #define PIXIS_LBMAP_ALTBANK 0x20 | |
283 | #endif | |
feb7838f SS |
284 | |
285 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
286 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
d51cc7a0 YS |
287 | #ifdef CONFIG_PHYS_64BIT |
288 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
289 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
290 | /* The assembler doesn't like typecast */ | |
291 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
292 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
293 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
294 | #else | |
295 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
296 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
297 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
298 | #endif | |
553f0982 | 299 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
feb7838f | 300 | |
25ddd1fb | 301 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
feb7838f SS |
302 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
303 | ||
304 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
305 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
306 | ||
307 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
308 | #ifdef CONFIG_PHYS_64BIT | |
309 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
310 | #else | |
311 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
312 | #endif | |
313 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ | |
314 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
315 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
316 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
317 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
318 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
319 | #define CONFIG_CMD_NAND 1 | |
320 | #define CONFIG_NAND_FSL_ELBC 1 | |
321 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
322 | ||
323 | /* NAND flash config */ | |
a3055c58 | 324 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
feb7838f SS |
325 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
326 | | BR_PS_8 /* Port Size = 8bit */ \ | |
327 | | BR_MS_FCM /* MSEL = FCM */ \ | |
328 | | BR_V) /* valid */ | |
a3055c58 | 329 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
feb7838f SS |
330 | | OR_FCM_PGS /* Large Page*/ \ |
331 | | OR_FCM_CSCT \ | |
332 | | OR_FCM_CST \ | |
333 | | OR_FCM_CHT \ | |
334 | | OR_FCM_SCY_1 \ | |
335 | | OR_FCM_TRLX \ | |
336 | | OR_FCM_EHTR) | |
337 | ||
338 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
339 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
340 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
341 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
feb7838f | 342 | |
7ee41107 | 343 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
feb7838f SS |
344 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
345 | | BR_PS_8 /* Port Size = 8bit */ \ | |
346 | | BR_MS_FCM /* MSEL = FCM */ \ | |
347 | | BR_V) /* valid */ | |
a3055c58 | 348 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
7ee41107 | 349 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
feb7838f SS |
350 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
351 | | BR_PS_8 /* Port Size = 8bit */ \ | |
352 | | BR_MS_FCM /* MSEL = FCM */ \ | |
353 | | BR_V) /* valid */ | |
a3055c58 | 354 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
feb7838f | 355 | |
7ee41107 | 356 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
feb7838f SS |
357 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
358 | | BR_PS_8 /* Port Size = 8bit */ \ | |
359 | | BR_MS_FCM /* MSEL = FCM */ \ | |
360 | | BR_V) /* valid */ | |
a3055c58 | 361 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
feb7838f SS |
362 | |
363 | /* Serial Port - controlled on board with jumper J8 | |
364 | * open - index 2 | |
365 | * shorted - index 1 | |
366 | */ | |
367 | #define CONFIG_CONS_INDEX 1 | |
feb7838f SS |
368 | #define CONFIG_SYS_NS16550 |
369 | #define CONFIG_SYS_NS16550_SERIAL | |
370 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
371 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
372 | ||
373 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
fb365a8a | 374 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
feb7838f SS |
375 | |
376 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
377 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
378 | ||
379 | /* Use the HUSH parser */ | |
380 | #define CONFIG_SYS_HUSH_PARSER | |
feb7838f SS |
381 | |
382 | /* | |
383 | * Pass open firmware flat tree | |
384 | */ | |
385 | #define CONFIG_OF_LIBFDT 1 | |
386 | #define CONFIG_OF_BOARD_SETUP 1 | |
387 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
388 | ||
feb7838f | 389 | /* I2C */ |
00f792e0 HS |
390 | #define CONFIG_SYS_I2C |
391 | #define CONFIG_SYS_I2C_FSL | |
392 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
393 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
394 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
395 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
396 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
397 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
feb7838f | 398 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
00f792e0 | 399 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
feb7838f SS |
400 | |
401 | /* | |
402 | * I2C2 EEPROM | |
403 | */ | |
404 | #define CONFIG_ID_EEPROM | |
405 | #ifdef CONFIG_ID_EEPROM | |
406 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
407 | #endif | |
408 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
409 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
410 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
411 | ||
21dd9af3 JH |
412 | /* |
413 | * eSPI - Enhanced SPI | |
414 | */ | |
415 | #define CONFIG_FSL_ESPI | |
416 | ||
417 | #define CONFIG_SPI_FLASH | |
418 | #define CONFIG_SPI_FLASH_SPANSION | |
419 | ||
420 | #define CONFIG_CMD_SF | |
421 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
422 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
423 | ||
feb7838f SS |
424 | /* |
425 | * General PCI | |
426 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
427 | */ | |
428 | ||
429 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
4d5723da | 430 | #define CONFIG_SYS_PCIE3_NAME "Slot 1" |
feb7838f SS |
431 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
432 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 433 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
feb7838f SS |
434 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
435 | #else | |
436 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
437 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
438 | #endif | |
439 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
440 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
441 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
442 | #ifdef CONFIG_PHYS_64BIT | |
443 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
444 | #else | |
445 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
446 | #endif | |
447 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
448 | ||
449 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
4d5723da | 450 | #define CONFIG_SYS_PCIE2_NAME "ULI" |
feb7838f SS |
451 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
452 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 453 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
feb7838f SS |
454 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
455 | #else | |
456 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
457 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
458 | #endif | |
459 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
460 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
461 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
462 | #ifdef CONFIG_PHYS_64BIT | |
463 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
464 | #else | |
465 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
466 | #endif | |
467 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
468 | ||
469 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
4d5723da | 470 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
feb7838f SS |
471 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
472 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 473 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
feb7838f SS |
474 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
475 | #else | |
476 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
477 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
478 | #endif | |
479 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
480 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
481 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
482 | #ifdef CONFIG_PHYS_64BIT | |
483 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
484 | #else | |
485 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
486 | #endif | |
487 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
488 | ||
489 | #if defined(CONFIG_PCI) | |
490 | ||
491 | /*PCIE video card used*/ | |
492 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
493 | ||
494 | /* video */ | |
d4ed6542 | 495 | #undef CONFIG_VIDEO |
feb7838f SS |
496 | |
497 | #if defined(CONFIG_VIDEO) | |
498 | #define CONFIG_BIOSEMU | |
499 | #define CONFIG_CFB_CONSOLE | |
500 | #define CONFIG_VIDEO_SW_CURSOR | |
501 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
502 | #define CONFIG_ATI_RADEON_FB | |
503 | #define CONFIG_VIDEO_LOGO | |
504 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
505 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
506 | #endif | |
507 | ||
28a096e7 LY |
508 | /* SRIO1 uses the same window as PCIE2 mem window */ |
509 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
510 | #ifdef CONFIG_PHYS_64BIT | |
511 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
512 | #else | |
513 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 | |
514 | #endif | |
515 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
516 | ||
517 | /* SRIO2 uses the same window as PCIE1 mem window */ | |
518 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 | |
519 | #ifdef CONFIG_PHYS_64BIT | |
520 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull | |
521 | #else | |
522 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 | |
523 | #endif | |
524 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ | |
525 | ||
feb7838f | 526 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
feb7838f SS |
527 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
528 | #define CONFIG_DOS_PARTITION | |
529 | #define CONFIG_SCSI_AHCI | |
530 | ||
531 | #ifdef CONFIG_SCSI_AHCI | |
532 | #define CONFIG_SATA_ULI5288 | |
533 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 | |
534 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
535 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
536 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
537 | #endif /* SCSI */ | |
538 | ||
539 | #endif /* CONFIG_PCI */ | |
540 | ||
541 | ||
542 | #if defined(CONFIG_TSEC_ENET) | |
543 | ||
feb7838f SS |
544 | #define CONFIG_MII 1 /* MII PHY management */ |
545 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
546 | #define CONFIG_TSEC1 1 | |
547 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
548 | #define CONFIG_TSEC2 1 | |
549 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
550 | #define CONFIG_TSEC3 1 | |
551 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
552 | ||
feb7838f SS |
553 | #define CONFIG_FSL_SGMII_RISER 1 |
554 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
555 | ||
556 | #ifdef CONFIG_FSL_SGMII_RISER | |
557 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
558 | #endif | |
559 | ||
560 | #define TSEC1_PHY_ADDR 0 | |
561 | #define TSEC2_PHY_ADDR 1 | |
562 | #define TSEC3_PHY_ADDR 2 | |
563 | ||
564 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
565 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
566 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
567 | ||
568 | #define TSEC1_PHYIDX 0 | |
569 | #define TSEC2_PHYIDX 0 | |
570 | #define TSEC3_PHYIDX 0 | |
571 | ||
572 | #define CONFIG_ETHPRIME "eTSEC1" | |
573 | ||
574 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
575 | #endif /* CONFIG_TSEC_ENET */ | |
576 | ||
577 | /* | |
578 | * Environment | |
579 | */ | |
1ac63e40 JH |
580 | #if defined(CONFIG_SDCARD) |
581 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 582 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
1ac63e40 JH |
583 | #define CONFIG_ENV_SIZE 0x2000 |
584 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
21dd9af3 JH |
585 | #elif defined(CONFIG_SPIFLASH) |
586 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
587 | #define CONFIG_ENV_SPI_BUS 0 | |
588 | #define CONFIG_ENV_SPI_CS 0 | |
589 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
590 | #define CONFIG_ENV_SPI_MODE 0 | |
591 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
592 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
593 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
1ac63e40 | 594 | #else |
feb7838f SS |
595 | #define CONFIG_ENV_IS_IN_FLASH 1 |
596 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
597 | #define CONFIG_ENV_ADDR 0xfff80000 | |
598 | #else | |
599 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
600 | #endif | |
601 | #define CONFIG_ENV_SIZE 0x2000 | |
602 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
1ac63e40 | 603 | #endif |
feb7838f SS |
604 | |
605 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
606 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
607 | ||
608 | /* | |
609 | * Command line configuration. | |
610 | */ | |
611 | #include <config_cmd_default.h> | |
612 | ||
613 | #define CONFIG_CMD_IRQ | |
614 | #define CONFIG_CMD_PING | |
615 | #define CONFIG_CMD_I2C | |
616 | #define CONFIG_CMD_MII | |
617 | #define CONFIG_CMD_ELF | |
618 | #define CONFIG_CMD_IRQ | |
619 | #define CONFIG_CMD_SETEXPR | |
199e262e | 620 | #define CONFIG_CMD_REGINFO |
feb7838f SS |
621 | |
622 | #if defined(CONFIG_PCI) | |
623 | #define CONFIG_CMD_PCI | |
feb7838f SS |
624 | #define CONFIG_CMD_NET |
625 | #define CONFIG_CMD_SCSI | |
626 | #define CONFIG_CMD_EXT2 | |
627 | #endif | |
628 | ||
0ead6f2e RZ |
629 | /* |
630 | * USB | |
631 | */ | |
3d7506fa | 632 | #define CONFIG_HAS_FSL_DR_USB |
633 | #ifdef CONFIG_HAS_FSL_DR_USB | |
9c4d8767 JH |
634 | #define CONFIG_USB_EHCI |
635 | ||
636 | #ifdef CONFIG_USB_EHCI | |
0ead6f2e RZ |
637 | #define CONFIG_CMD_USB |
638 | #define CONFIG_USB_STORAGE | |
0ead6f2e RZ |
639 | #define CONFIG_USB_EHCI_FSL |
640 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
9c4d8767 | 641 | #endif |
3d7506fa | 642 | #endif |
0ead6f2e | 643 | |
9c4d8767 JH |
644 | /* |
645 | * SDHC/MMC | |
646 | */ | |
647 | #define CONFIG_MMC | |
648 | ||
649 | #ifdef CONFIG_MMC | |
650 | #define CONFIG_FSL_ESDHC | |
651 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
652 | #define CONFIG_CMD_MMC | |
653 | #define CONFIG_GENERIC_MMC | |
654 | #endif | |
655 | ||
656 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
657 | #define CONFIG_CMD_EXT2 | |
658 | #define CONFIG_CMD_FAT | |
659 | #define CONFIG_DOS_PARTITION | |
660 | #endif | |
661 | ||
feb7838f SS |
662 | /* |
663 | * Miscellaneous configurable options | |
664 | */ | |
665 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
5be58f5f KP |
666 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
667 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
feb7838f SS |
668 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
669 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
670 | #if defined(CONFIG_CMD_KGDB) | |
671 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
672 | #else | |
673 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
674 | #endif | |
675 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
676 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
677 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
678 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
679 | ||
680 | /* | |
681 | * For booting Linux, the board info and command line data | |
a832ac41 | 682 | * have to be in the first 64 MB of memory, since this is |
feb7838f SS |
683 | * the maximum mapped by the Linux kernel during initialization. |
684 | */ | |
a832ac41 KG |
685 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
686 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
feb7838f | 687 | |
feb7838f SS |
688 | #if defined(CONFIG_CMD_KGDB) |
689 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
690 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
691 | #endif | |
692 | ||
693 | /* | |
694 | * Environment Configuration | |
695 | */ | |
696 | ||
697 | /* The mac addresses for all ethernet interface */ | |
698 | #if defined(CONFIG_TSEC_ENET) | |
699 | #define CONFIG_HAS_ETH0 | |
feb7838f | 700 | #define CONFIG_HAS_ETH1 |
feb7838f | 701 | #define CONFIG_HAS_ETH2 |
feb7838f SS |
702 | #endif |
703 | ||
704 | #define CONFIG_IPADDR 192.168.1.254 | |
705 | ||
706 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 707 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 708 | #define CONFIG_BOOTFILE "uImage" |
feb7838f SS |
709 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
710 | ||
711 | #define CONFIG_SERVERIP 192.168.1.1 | |
712 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
713 | #define CONFIG_NETMASK 255.255.255.0 | |
714 | ||
715 | /* default location for tftp and bootm */ | |
716 | #define CONFIG_LOADADDR 1000000 | |
717 | ||
718 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
feb7838f SS |
719 | |
720 | #define CONFIG_BAUDRATE 115200 | |
721 | ||
722 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 723 | "perf_mode=performance\0" \ |
68d4230c RM |
724 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ |
725 | "usb1:dr_mode=host,phy_type=ulpi\0" \ | |
5368c55d MV |
726 | "netdev=eth0\0" \ |
727 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
728 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
729 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
730 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
731 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
732 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
733 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
734 | "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ | |
ccc4a8d8 LY |
735 | "console=$consoledev,$baudrate $othbootargs;" \ |
736 | "tftp $loadaddr $bootfile;" \ | |
737 | "tftp $fdtaddr $fdtfile;" \ | |
738 | "bootm $loadaddr - $fdtaddr" \ | |
5368c55d MV |
739 | "consoledev=ttyS0\0" \ |
740 | "ramdiskaddr=2000000\0" \ | |
741 | "ramdiskfile=p2020ds/ramdisk.uboot\0" \ | |
742 | "fdtaddr=c00000\0" \ | |
743 | "othbootargs=cache-sram-size=0x10000\0" \ | |
744 | "fdtfile=p2020ds/p2020ds.dtb\0" \ | |
745 | "bdev=sda3\0" \ | |
746 | "partition=scsi 0:0\0" | |
feb7838f SS |
747 | |
748 | #define CONFIG_HDBOOT \ | |
749 | "setenv bootargs root=/dev/$bdev rw " \ | |
750 | "console=$consoledev,$baudrate $othbootargs;" \ | |
ccc4a8d8 LY |
751 | "ext2load $partition $loadaddr $bootfile;" \ |
752 | "ext2load $partition $fdtaddr $fdtfile;" \ | |
feb7838f SS |
753 | "bootm $loadaddr - $fdtaddr" |
754 | ||
755 | #define CONFIG_NFSBOOTCOMMAND \ | |
756 | "setenv bootargs root=/dev/nfs rw " \ | |
757 | "nfsroot=$serverip:$rootpath " \ | |
758 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
759 | "console=$consoledev,$baudrate $othbootargs;" \ | |
760 | "tftp $loadaddr $bootfile;" \ | |
761 | "tftp $fdtaddr $fdtfile;" \ | |
762 | "bootm $loadaddr - $fdtaddr" | |
763 | ||
764 | #define CONFIG_RAMBOOTCOMMAND \ | |
765 | "setenv bootargs root=/dev/ram rw " \ | |
766 | "console=$consoledev,$baudrate $othbootargs;" \ | |
767 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
768 | "tftp $loadaddr $bootfile;" \ | |
769 | "tftp $fdtaddr $fdtfile;" \ | |
770 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
771 | ||
772 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
773 | ||
774 | #endif /* __CONFIG_H */ |