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4f1d1b7d MH |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * P2041 RDB board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | #define CONFIG_P2041RDB | |
31 | #define CONFIG_PHYS_64BIT | |
32 | #define CONFIG_PPC_P2041 | |
33 | ||
34 | #ifdef CONFIG_RAMBOOT_PBL | |
35 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
36 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
37 | #endif | |
38 | ||
39 | /* High Level Configuration Options */ | |
40 | #define CONFIG_BOOKE | |
41 | #define CONFIG_E500 /* BOOKE e500 family */ | |
42 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
43 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
44 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
45 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
46 | #define CONFIG_MP /* support multiple processors */ | |
47 | ||
48 | #ifndef CONFIG_SYS_TEXT_BASE | |
49 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
50 | #endif | |
51 | ||
52 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
53 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
54 | #endif | |
55 | ||
56 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
57 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
58 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
59 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
60 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
61 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
62 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
63 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
64 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
65 | ||
66 | #define CONFIG_SYS_SRIO | |
67 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
68 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
4d28db8a | 69 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ |
4f1d1b7d MH |
70 | |
71 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
72 | ||
73 | #define CONFIG_ENV_OVERWRITE | |
74 | ||
75 | #ifdef CONFIG_SYS_NO_FLASH | |
76 | #define CONFIG_ENV_IS_NOWHERE | |
77 | #else | |
78 | #define CONFIG_FLASH_CFI_DRIVER | |
79 | #define CONFIG_SYS_FLASH_CFI | |
80 | #endif | |
81 | ||
82 | #if defined(CONFIG_SPIFLASH) | |
83 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
84 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
85 | #define CONFIG_ENV_SPI_BUS 0 | |
86 | #define CONFIG_ENV_SPI_CS 0 | |
87 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
88 | #define CONFIG_ENV_SPI_MODE 0 | |
89 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
90 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
91 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
92 | #elif defined(CONFIG_SDCARD) | |
93 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
94 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 95 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
4f1d1b7d MH |
96 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
97 | #define CONFIG_ENV_SIZE 0x2000 | |
98 | #define CONFIG_ENV_OFFSET (512 * 1097) | |
15c8c6c2 SX |
99 | #elif defined(CONFIG_NAND) |
100 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
101 | #define CONFIG_ENV_IS_IN_NAND | |
102 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
103 | #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
4f1d1b7d MH |
104 | #else |
105 | #define CONFIG_ENV_IS_IN_FLASH | |
106 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ | |
107 | - CONFIG_ENV_SECT_SIZE) | |
108 | #define CONFIG_ENV_SIZE 0x2000 | |
109 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
110 | #endif | |
111 | ||
44d50f0b SX |
112 | #ifndef __ASSEMBLY__ |
113 | unsigned long get_board_sys_clk(unsigned long dummy); | |
114 | #endif | |
115 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
4f1d1b7d MH |
116 | |
117 | /* | |
118 | * These can be toggled for performance analysis, otherwise use default. | |
119 | */ | |
120 | #define CONFIG_SYS_CACHE_STASHING | |
cd420e0b MH |
121 | #define CONFIG_BACKSIDE_L2_CACHE |
122 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
4f1d1b7d MH |
123 | #define CONFIG_BTB /* toggle branch predition */ |
124 | ||
125 | #define CONFIG_ENABLE_36BIT_PHYS | |
126 | ||
127 | #ifdef CONFIG_PHYS_64BIT | |
128 | #define CONFIG_ADDR_MAP | |
129 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
130 | #endif | |
131 | ||
132 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ | |
133 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
134 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
135 | #define CONFIG_SYS_ALT_MEMTEST | |
136 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
137 | ||
138 | /* | |
139 | * Config the L3 Cache as L3 SRAM | |
140 | */ | |
141 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
142 | #ifdef CONFIG_PHYS_64BIT | |
143 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ | |
144 | CONFIG_RAMBOOT_TEXT_BASE) | |
145 | #else | |
146 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
147 | #endif | |
148 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
149 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
150 | ||
4f1d1b7d MH |
151 | #ifdef CONFIG_PHYS_64BIT |
152 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
153 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
154 | #endif | |
155 | ||
156 | /* EEPROM */ | |
157 | #define CONFIG_ID_EEPROM | |
158 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
159 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
160 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
161 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
162 | ||
163 | /* | |
164 | * DDR Setup | |
165 | */ | |
166 | #define CONFIG_VERY_BIG_RAM | |
167 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
168 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
169 | ||
170 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
171 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
172 | ||
173 | #define CONFIG_DDR_SPD | |
174 | #define CONFIG_FSL_DDR3 | |
175 | ||
176 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
177 | #define SPD_EEPROM_ADDRESS 0x52 | |
178 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
179 | ||
180 | /* | |
181 | * Local Bus Definitions | |
182 | */ | |
183 | ||
184 | /* Set the local bus clock 1/8 of platform clock */ | |
185 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
186 | ||
187 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ | |
188 | #ifdef CONFIG_PHYS_64BIT | |
189 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull | |
190 | #else | |
191 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
192 | #endif | |
193 | ||
c9b2feaf | 194 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
4f1d1b7d | 195 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
c9b2feaf SX |
196 | #define CONFIG_SYS_FLASH_OR_PRELIM \ |
197 | ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
198 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
4f1d1b7d MH |
199 | |
200 | #define CONFIG_FSL_CPLD | |
201 | #define CPLD_BASE 0xffdf0000 /* CPLD registers */ | |
202 | #ifdef CONFIG_PHYS_64BIT | |
203 | #define CPLD_BASE_PHYS 0xfffdf0000ull | |
204 | #else | |
205 | #define CPLD_BASE_PHYS CPLD_BASE | |
206 | #endif | |
207 | ||
208 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) | |
209 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
210 | ||
211 | #define PIXIS_LBMAP_SWITCH 7 | |
212 | #define PIXIS_LBMAP_MASK 0xf0 | |
213 | #define PIXIS_LBMAP_SHIFT 4 | |
214 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
215 | ||
216 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
217 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
218 | ||
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
220 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ | |
222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ | |
223 | ||
224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
225 | ||
226 | #if defined(CONFIG_RAMBOOT_PBL) | |
227 | #define CONFIG_SYS_RAMBOOT | |
228 | #endif | |
229 | ||
c9b2feaf SX |
230 | #define CONFIG_NAND_FSL_ELBC |
231 | /* Nand Flash */ | |
232 | #ifdef CONFIG_NAND_FSL_ELBC | |
233 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
234 | #ifdef CONFIG_PHYS_64BIT | |
235 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
236 | #else | |
237 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
238 | #endif | |
239 | ||
240 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
241 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
242 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
243 | #define CONFIG_CMD_NAND | |
244 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
245 | ||
246 | /* NAND flash config */ | |
247 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
248 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
249 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
250 | | BR_MS_FCM /* MSEL = FCM */ \ | |
251 | | BR_V) /* valid */ | |
252 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
253 | | OR_FCM_PGS /* Large Page*/ \ | |
254 | | OR_FCM_CSCT \ | |
255 | | OR_FCM_CST \ | |
256 | | OR_FCM_CHT \ | |
257 | | OR_FCM_SCY_1 \ | |
258 | | OR_FCM_TRLX \ | |
259 | | OR_FCM_EHTR) | |
260 | ||
261 | #ifdef CONFIG_NAND | |
262 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
263 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
264 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
265 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
266 | #else | |
267 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
268 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
269 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
270 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
271 | #endif | |
272 | #else | |
273 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
274 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
275 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
276 | ||
4f1d1b7d MH |
277 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
278 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
279 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
280 | ||
281 | #define CONFIG_BOARD_EARLY_INIT_F | |
282 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
283 | #define CONFIG_MISC_INIT_R | |
284 | ||
285 | #define CONFIG_HWCONFIG | |
286 | ||
287 | /* define to use L1 as initial stack */ | |
288 | #define CONFIG_L1_INIT_RAM | |
289 | #define CONFIG_SYS_INIT_RAM_LOCK | |
290 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
291 | #ifdef CONFIG_PHYS_64BIT | |
292 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
293 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
294 | /* The assembler doesn't like typecast */ | |
295 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
296 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
297 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
298 | #else | |
299 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
300 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
301 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
302 | #endif | |
303 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
304 | ||
305 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
306 | GENERATED_GBL_DATA_SIZE) | |
307 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
308 | ||
309 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
310 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) | |
311 | ||
312 | /* Serial Port - controlled on board with jumper J8 | |
313 | * open - index 2 | |
314 | * shorted - index 1 | |
315 | */ | |
316 | #define CONFIG_CONS_INDEX 1 | |
317 | #define CONFIG_SYS_NS16550 | |
318 | #define CONFIG_SYS_NS16550_SERIAL | |
319 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
320 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
321 | ||
322 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
323 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
324 | ||
325 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
326 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
327 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
328 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
329 | ||
330 | /* Use the HUSH parser */ | |
331 | #define CONFIG_SYS_HUSH_PARSER | |
4f1d1b7d MH |
332 | |
333 | /* pass open firmware flat tree */ | |
334 | #define CONFIG_OF_LIBFDT | |
335 | #define CONFIG_OF_BOARD_SETUP | |
336 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
337 | ||
338 | /* new uImage format support */ | |
339 | #define CONFIG_FIT | |
340 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
341 | ||
342 | /* I2C */ | |
343 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
344 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
345 | #define CONFIG_I2C_MULTI_BUS | |
346 | #define CONFIG_I2C_CMD_TREE | |
347 | #define CONFIG_SYS_I2C_SPEED 400000 | |
348 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
349 | #define CONFIG_SYS_I2C_OFFSET 0x118000 | |
350 | #define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
351 | ||
352 | /* | |
353 | * RapidIO | |
354 | */ | |
355 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
356 | #ifdef CONFIG_PHYS_64BIT | |
357 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
358 | #else | |
359 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 | |
360 | #endif | |
361 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
362 | ||
363 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
364 | #ifdef CONFIG_PHYS_64BIT | |
365 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
366 | #else | |
367 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 | |
368 | #endif | |
369 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
370 | ||
371 | /* | |
372 | * eSPI - Enhanced SPI | |
373 | */ | |
374 | #define CONFIG_FSL_ESPI | |
375 | #define CONFIG_SPI_FLASH | |
376 | #define CONFIG_SPI_FLASH_SPANSION | |
377 | #define CONFIG_CMD_SF | |
378 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
379 | #define CONFIG_SF_DEFAULT_MODE 0 | |
380 | ||
381 | /* | |
382 | * General PCI | |
383 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
384 | */ | |
385 | ||
386 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
387 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
388 | #ifdef CONFIG_PHYS_64BIT | |
389 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
390 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
391 | #else | |
392 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
393 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
394 | #endif | |
395 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
396 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
397 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
398 | #ifdef CONFIG_PHYS_64BIT | |
399 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
400 | #else | |
401 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
402 | #endif | |
403 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
404 | ||
405 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
406 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
407 | #ifdef CONFIG_PHYS_64BIT | |
408 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
409 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
410 | #else | |
411 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
412 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
413 | #endif | |
414 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
415 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
416 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
417 | #ifdef CONFIG_PHYS_64BIT | |
418 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
419 | #else | |
420 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
421 | #endif | |
422 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
423 | ||
424 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
425 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
426 | #ifdef CONFIG_PHYS_64BIT | |
427 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
428 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
429 | #else | |
430 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
431 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
432 | #endif | |
433 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
434 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
435 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
436 | #ifdef CONFIG_PHYS_64BIT | |
437 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
438 | #else | |
439 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
440 | #endif | |
441 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
442 | ||
443 | /* Qman/Bman */ | |
444 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
445 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
446 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
447 | #ifdef CONFIG_PHYS_64BIT | |
448 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
449 | #else | |
450 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
451 | #endif | |
452 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
453 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
454 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
455 | #ifdef CONFIG_PHYS_64BIT | |
456 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
457 | #else | |
458 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
459 | #endif | |
460 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
461 | ||
462 | #define CONFIG_SYS_DPAA_FMAN | |
463 | #define CONFIG_SYS_DPAA_PME | |
464 | /* Default address of microcode for the Linux Fman driver */ | |
4f1d1b7d MH |
465 | #if defined(CONFIG_SPIFLASH) |
466 | /* | |
467 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
468 | * env, so we got 0x110000. | |
469 | */ | |
f2717b47 TT |
470 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
471 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 | |
4f1d1b7d MH |
472 | #elif defined(CONFIG_SDCARD) |
473 | /* | |
474 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
475 | * about 545KB (1089 blocks), Env is stored after the image, and the env size is | |
476 | * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. | |
477 | */ | |
f2717b47 TT |
478 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
479 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) | |
4f1d1b7d | 480 | #elif defined(CONFIG_NAND) |
f2717b47 TT |
481 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
482 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
4f1d1b7d | 483 | #else |
f2717b47 TT |
484 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
485 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 | |
4f1d1b7d | 486 | #endif |
f2717b47 TT |
487 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
488 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
4f1d1b7d MH |
489 | |
490 | #ifdef CONFIG_SYS_DPAA_FMAN | |
491 | #define CONFIG_FMAN_ENET | |
0787ecc0 MH |
492 | #define CONFIG_PHYLIB_10G |
493 | #define CONFIG_PHY_VITESSE | |
494 | #define CONFIG_PHY_TERANETICS | |
4f1d1b7d MH |
495 | #endif |
496 | ||
497 | #ifdef CONFIG_PCI | |
4f1d1b7d MH |
498 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
499 | #define CONFIG_E1000 | |
500 | ||
501 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
502 | #define CONFIG_DOS_PARTITION | |
503 | #endif /* CONFIG_PCI */ | |
504 | ||
aa7f281c | 505 | /* SATA */ |
aa7f281c | 506 | #define CONFIG_FSL_SATA |
3e0529f7 TT |
507 | #ifdef CONFIG_FSL_SATA |
508 | #define CONFIG_LIBATA | |
aa7f281c MH |
509 | |
510 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
511 | #define CONFIG_SATA1 | |
512 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
513 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
514 | #define CONFIG_SATA2 | |
515 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
516 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
517 | ||
518 | #define CONFIG_LBA48 | |
519 | #define CONFIG_CMD_SATA | |
520 | #define CONFIG_DOS_PARTITION | |
521 | #define CONFIG_CMD_EXT2 | |
522 | #endif | |
523 | ||
4f1d1b7d MH |
524 | #ifdef CONFIG_FMAN_ENET |
525 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 | |
526 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 | |
527 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 | |
528 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 | |
529 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 | |
530 | ||
531 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
532 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
533 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
534 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
535 | ||
0787ecc0 MH |
536 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 |
537 | ||
4f1d1b7d MH |
538 | #define CONFIG_SYS_TBIPA_VALUE 8 |
539 | #define CONFIG_MII /* MII PHY management */ | |
540 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
541 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
542 | #endif | |
543 | ||
544 | /* | |
545 | * Environment | |
546 | */ | |
547 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
548 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
549 | ||
550 | /* | |
551 | * Command line configuration. | |
552 | */ | |
553 | #include <config_cmd_default.h> | |
554 | ||
555 | #define CONFIG_CMD_DHCP | |
556 | #define CONFIG_CMD_ELF | |
557 | #define CONFIG_CMD_ERRATA | |
558 | #define CONFIG_CMD_GREPENV | |
559 | #define CONFIG_CMD_IRQ | |
560 | #define CONFIG_CMD_I2C | |
561 | #define CONFIG_CMD_MII | |
562 | #define CONFIG_CMD_PING | |
563 | #define CONFIG_CMD_SETEXPR | |
564 | ||
565 | #ifdef CONFIG_PCI | |
566 | #define CONFIG_CMD_PCI | |
567 | #define CONFIG_CMD_NET | |
568 | #endif | |
569 | ||
570 | /* | |
571 | * USB | |
572 | */ | |
573 | #define CONFIG_CMD_USB | |
574 | #define CONFIG_USB_STORAGE | |
575 | #define CONFIG_USB_EHCI | |
576 | #define CONFIG_USB_EHCI_FSL | |
577 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
578 | #define CONFIG_CMD_EXT2 | |
579 | ||
580 | #define CONFIG_MMC | |
581 | ||
582 | #ifdef CONFIG_MMC | |
583 | #define CONFIG_FSL_ESDHC | |
584 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
585 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
586 | #define CONFIG_CMD_MMC | |
587 | #define CONFIG_GENERIC_MMC | |
588 | #define CONFIG_CMD_EXT2 | |
589 | #define CONFIG_CMD_FAT | |
590 | #define CONFIG_DOS_PARTITION | |
591 | #endif | |
592 | ||
593 | /* | |
594 | * Miscellaneous configurable options | |
595 | */ | |
596 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
597 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
598 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
599 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
600 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
601 | #ifdef CONFIG_CMD_KGDB | |
602 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
603 | #else | |
604 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
605 | #endif | |
606 | /* Print Buffer Size */ | |
607 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
608 | sizeof(CONFIG_SYS_PROMPT)+16) | |
609 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
610 | /* Boot Argument Buffer Size */ | |
611 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
612 | #define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */ | |
613 | ||
614 | /* | |
615 | * For booting Linux, the board info and command line data | |
616 | * have to be in the first 64 MB of memory, since this is | |
617 | * the maximum mapped by the Linux kernel during initialization. | |
618 | */ | |
619 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ | |
620 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
621 | ||
622 | #ifdef CONFIG_CMD_KGDB | |
623 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
624 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
625 | #endif | |
626 | ||
627 | /* | |
628 | * Environment Configuration | |
629 | */ | |
8b3637c6 | 630 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 631 | #define CONFIG_BOOTFILE "uImage" |
4f1d1b7d MH |
632 | #define CONFIG_UBOOTPATH u-boot.bin |
633 | ||
634 | /* default location for tftp and bootm */ | |
635 | #define CONFIG_LOADADDR 1000000 | |
636 | ||
637 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
638 | ||
639 | #define CONFIG_BAUDRATE 115200 | |
640 | ||
641 | #define __USB_PHY_TYPE utmi | |
642 | ||
643 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
644 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
645 | "bank_intlv=cs0_cs1\0" \ | |
646 | "netdev=eth0\0" \ | |
647 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
648 | "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ | |
649 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
650 | "protect off $ubootaddr +$filesize && " \ | |
651 | "erase $ubootaddr +$filesize && " \ | |
652 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
653 | "protect on $ubootaddr +$filesize && " \ | |
654 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
655 | "consoledev=ttyS0\0" \ | |
656 | "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ | |
657 | "usb_dr_mode=host\0" \ | |
658 | "ramdiskaddr=2000000\0" \ | |
659 | "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ | |
660 | "fdtaddr=c00000\0" \ | |
661 | "fdtfile=p2041rdb/p2041rdb.dtb\0" \ | |
662 | "bdev=sda3\0" \ | |
663 | "c=ffe\0" | |
664 | ||
665 | #define CONFIG_HDBOOT \ | |
666 | "setenv bootargs root=/dev/$bdev rw " \ | |
667 | "console=$consoledev,$baudrate $othbootargs;" \ | |
668 | "tftp $loadaddr $bootfile;" \ | |
669 | "tftp $fdtaddr $fdtfile;" \ | |
670 | "bootm $loadaddr - $fdtaddr" | |
671 | ||
672 | #define CONFIG_NFSBOOTCOMMAND \ | |
673 | "setenv bootargs root=/dev/nfs rw " \ | |
674 | "nfsroot=$serverip:$rootpath " \ | |
675 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
676 | "console=$consoledev,$baudrate $othbootargs;" \ | |
677 | "tftp $loadaddr $bootfile;" \ | |
678 | "tftp $fdtaddr $fdtfile;" \ | |
679 | "bootm $loadaddr - $fdtaddr" | |
680 | ||
681 | #define CONFIG_RAMBOOTCOMMAND \ | |
682 | "setenv bootargs root=/dev/ram rw " \ | |
683 | "console=$consoledev,$baudrate $othbootargs;" \ | |
684 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
685 | "tftp $loadaddr $bootfile;" \ | |
686 | "tftp $fdtaddr $fdtfile;" \ | |
687 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
688 | ||
689 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
690 | ||
691 | #ifdef CONFIG_SECURE_BOOT | |
692 | #include <asm/fsl_secure_boot.h> | |
693 | #endif | |
694 | ||
695 | #endif /* __CONFIG_H */ |