[people/ms/u-boot.git] / include / configs / P4080DS.h

/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * P4080 DS board configuration file
 * Also supports P4040 DS
 */
#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */

#define CONFIG_PCIE3

#define CONFIG_SYS_SATA_MAX_DEVICE  2
#define CONFIG_LBA48

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */
#define CONFIG_SRIO2			/* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */

#include "corenet_ds.h"
Commit	Line	Data
d1712369	1	/*
d621da00	2	* Copyright 2009-2011 Freescale Semiconductor, Inc.
d1712369	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
d1712369 KG	5	*/
	6
	7	/*
	8	* P4080 DS board configuration file
3e978f5d	9	* Also supports P4040 DS
d1712369	10	*/
c6d33901 KG	11	#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
c6d33901 KG	12
c6d33901 KG	13	#define CONFIG_PCIE3
c6d33901 KG	14
70672a29	15	#define CONFIG_SYS_SATA_MAX_DEVICE 2
70672a29 SX	16	#define CONFIG_LBA48
70672a29 SX	17
11860d88 TT	18	#define CONFIG_SYS_SRIO
	19	#define CONFIG_SRIO1 /* SRIO port 1 */
	20	#define CONFIG_SRIO2 /* SRIO port 2 */
c8b28152	21	#define CONFIG_SRIO_PCIE_BOOT_MASTER
0ce8437f KG	22	#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
0ce8437f KG	23
d1712369	24	#include "corenet_ds.h"