[people/ms/u-boot.git] / include / configs / PATI.h

/*
 * (C) Copyright 2003
 * Denis Peter d.peter@mpl.ch
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation,
 */

/*
 * File:		PATI.h
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
#define CONFIG_PATI		1		/* ...On a PATI board	*/
/* Serial Console Configuration */
#define	CONFIG_5xx_CONS_SCI1
#undef	CONFIG_5xx_CONS_SCI2

#define CONFIG_BAUDRATE		9600


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_ENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BSP
#define CONFIG_CMD_IMI
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MISC


#if 0
#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
#else
#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
#endif
#define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/

#define CONFIG_BOOTARGS		""		/* */

#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/

/*#define CONFIG_STATUS_LED	1		*/ /* Enable status led */

#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */

/*
 * Miscellaneous configurable options
 */
#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
#define CONFIG_PREBOOT

#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16	       /* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00010000	/* memtest works on		*/
#define CFG_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/

#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }


/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT

/*
 * Low Level Configuration Settings
 */

/*
 * Internal Memory Mapped (This is not the IMMR content)
 */
#define CFG_IMMR		0x01C00000		/* Physical start adress of internal memory map */

/*
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
#define	CFG_GBL_DATA_SIZE	128			/* Size in bytes reserved for initial global data */
#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
#define	CFG_INIT_SP_ADDR	(CFG_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
/*
 * Start addresses for the final memory configuration
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
#define CFG_FLASH_BASE		0xffC00000	/* External flash */
#define PCI_BASE		0x03000000	/* PCI Base (CS2) */
#define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
#define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */

#define	CFG_MONITOR_BASE	0xFFF00000
/* CFG_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file.	*/
						/* This adress is given to the linker with -Ttext to	*/
						/* locate the text section at this adress.		*/
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/

#define CFG_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/


/*-----------------------------------------------------------------------
 * FLASH organization
 *-----------------------------------------------------------------------
 *
 */

#define CFG_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
#define CFG_MAX_FLASH_SECT		128		/* Max number of sectors on one chip	*/
#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/


#define	CONFIG_ENV_IS_IN_EEPROM
#ifdef	CONFIG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET		0
#define CFG_ENV_SIZE		2048
#endif

#undef  CONFIG_ENV_IS_IN_FLASH
#ifdef	CONFIG_ENV_IS_IN_FLASH
#define	CFG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
#define CFG_ENV_OFFSET		((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE)		/* Environment starts at this adress	*/
#endif


#define CONFIG_SPI		1
#define CFG_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
#define CFG_SPI_CS_BASE	0x08 /* CS3 is active low */
#define CFG_SPI_CS_ACT	0x00 /* CS3 is active low */
/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * SW Watchdog freeze
 */
#undef CONFIG_WATCHDOG
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWP)
#endif	/* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration
 *-----------------------------------------------------------------------
 * Data show cycle
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register
 *-----------------------------------------------------------------------
 * Set all bits to 40 Mhz
 *
 */
#define CFG_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/


#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)

/*-----------------------------------------------------------------------
 * UMCR - UIMB Module Configuration Register
 *-----------------------------------------------------------------------
 *
 */
#define CFG_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/

/*-----------------------------------------------------------------------
 * ICTRL - I-Bus Support Control Register
 */
#define CFG_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/

/*-----------------------------------------------------------------------
 * USIU - Memory Controller Register
 *-----------------------------------------------------------------------
 */
#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
#define CFG_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
/* SDRAM */
#define CFG_BR1_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
#define CFG_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
/* PCI */
#define CFG_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
/* config registers: */
#define CFG_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
#define CFG_OR3_PRELIM		(0xffff0000)

#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/

/*-----------------------------------------------------------------------
 * DER - Timer Decrementer
 *-----------------------------------------------------------------------
 * Initialise to zero
 */
#define CFG_DER			0x00000000


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01			/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02			/* Software reboot			*/


#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10084-001"

#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG

#endif	/* __CONFIG_H */
Commit	Line	Data
b6e4c403 WD	1	/*
	2	* (C) Copyright 2003
	3	* Denis Peter d.peter@mpl.ch
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation,
	21	*/
	22
	23	/*
	24	* File: PATI.h
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	*/
	33
	34	#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
53677ef1	35	#define CONFIG_PATI 1 /* ...On a PATI board */
b6e4c403 WD	36	/* Serial Console Configuration */
	37	#define CONFIG_5xx_CONS_SCI1
	38	#undef CONFIG_5xx_CONS_SCI2
	39
	40	#define CONFIG_BAUDRATE 9600
	41
b6e4c403	42
a1aa0bb5 JL	43	/*
	44	* BOOTP options
	45	*/
	46	#define CONFIG_BOOTP_BOOTFILESIZE
	47	#define CONFIG_BOOTP_BOOTPATH
	48	#define CONFIG_BOOTP_GATEWAY
	49	#define CONFIG_BOOTP_HOSTNAME
	50
	51
acf02697 JL	52	/*
	53	* Command line configuration.
	54	*/
	55	#define CONFIG_CMD_MEMORY
	56	#define CONFIG_CMD_LOADB
	57	#define CONFIG_CMD_REGINFO
	58	#define CONFIG_CMD_FLASH
	59	#define CONFIG_CMD_LOADS
	60	#define CONFIG_CMD_ENV
	61	#define CONFIG_CMD_REGINFO
	62	#define CONFIG_CMD_BDI
	63	#define CONFIG_CMD_CONSOLE
	64	#define CONFIG_CMD_RUN
	65	#define CONFIG_CMD_BSP
	66	#define CONFIG_CMD_IMI
	67	#define CONFIG_CMD_EEPROM
	68	#define CONFIG_CMD_IRQ
	69	#define CONFIG_CMD_MISC
	70
b6e4c403 WD	71
	72	#if 0
	73	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	74	#else
	75	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	76	#endif
53677ef1	77	#define CONFIG_BOOTCOMMAND "" /* autoboot command */
b6e4c403 WD	78
	79	#define CONFIG_BOOTARGS "" /* */
	80
53677ef1	81	#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
b6e4c403	82
3a473b2a	83	/#define CONFIG_STATUS_LED 1 / /* Enable status led */
b6e4c403 WD	84
	85	#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
	86
	87	/*
	88	* Miscellaneous configurable options
	89	*/
	90	#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
	91	#define CONFIG_PREBOOT
	92
	93	#define CFG_LONGHELP /* undef to save memory */
	94	#define CFG_PROMPT "pati=> " /* Monitor Command Prompt */
acf02697	95	#if defined(CONFIG_CMD_KGDB)
b6e4c403 WD	96	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	97	#else
	98	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	99	#endif
	100	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	101	#define CFG_MAXARGS 16 /* max number of command args */
	102	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	103
	104	#define CFG_MEMTEST_START 0x00010000 /* memtest works on */
	105	#define CFG_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
	106
	107	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	108
	109	#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
	110
	111	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
	112
	113
	114	/***********************************************************************
	115	* Last Stage Init
	116	***********************************************************************/
	117	#define CONFIG_LAST_STAGE_INIT
	118
	119	/*
	120	* Low Level Configuration Settings
	121	*/
	122
	123	/*
	124	* Internal Memory Mapped (This is not the IMMR content)
	125	*/
53677ef1	126	#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */
b6e4c403 WD	127
	128	/*
	129	* Definitions for initial stack pointer and data area
	130	*/
53677ef1 WD	131	#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
	132	#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
	133	#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */
b6e4c403	134	#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
53677ef1	135	#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */
b6e4c403 WD	136	/*
	137	* Start addresses for the final memory configuration
	138	* Please note that CFG_SDRAM_BASE _must_ start at 0
	139	*/
53677ef1	140	#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
b6e4c403 WD	141	#define CFG_FLASH_BASE 0xffC00000 /* External flash */
	142	#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
	143	#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
	144	#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
	145
	146	#define CFG_MONITOR_BASE 0xFFF00000
53677ef1 WD	147	/* CFG_FLASH_BASE / / TEXT_BASE is defined in the board config.mk file. */
	148	/* This adress is given to the linker with -Ttext to */
	149	/* locate the text section at this adress. */
b6e4c403 WD	150	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
	151	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	152
b6e4c403 WD	153	#define CFG_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
	154
	155	/*
	156	* For booting Linux, the board info and command line data
	157	* have to be in the first 8 MB of memory, since this is
	158	* the maximum mapped by the Linux kernel during initialization.
	159	*/
	160	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	161
	162
	163	/*-----------------------------------------------------------------------
	164	* FLASH organization
	165	*-----------------------------------------------------------------------
	166	*
	167	*/
	168
	169	#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
53677ef1 WD	170	#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */
	171	#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
	172	#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
b6e4c403 WD	173
b6e4c403 WD	174
bb1f8b4f JCPV	175	#define CONFIG_ENV_IS_IN_EEPROM
bb1f8b4f JCPV	176	#ifdef CONFIG_ENV_IS_IN_EEPROM
b6e4c403 WD	177	#define CFG_ENV_OFFSET 0
	178	#define CFG_ENV_SIZE 2048
	179	#endif
	180
5a1aceb0 JCPV	181	#undef CONFIG_ENV_IS_IN_FLASH
5a1aceb0 JCPV	182	#ifdef CONFIG_ENV_IS_IN_FLASH
53677ef1 WD	183	#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */
53677ef1 WD	184	#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */
b6e4c403 WD	185	#endif
	186
	187
	188	#define CONFIG_SPI 1
	189	#define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
	190	#define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */
	191	#define CFG_SPI_CS_ACT 0x00 /* CS3 is active low */
	192	/*-----------------------------------------------------------------------
	193	* SYPCR - System Protection Control
	194	* SYPCR can only be written once after reset!
	195	*-----------------------------------------------------------------------
	196	* SW Watchdog freeze
	197	*/
	198	#undef CONFIG_WATCHDOG
	199	#if defined(CONFIG_WATCHDOG)
	200	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	201	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	202	#else
	203	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	204	SYPCR_SWP)
	205	#endif /* CONFIG_WATCHDOG */
	206
b6e4c403 WD	207	/*-----------------------------------------------------------------------
	208	* TBSCR - Time Base Status and Control
	209	*-----------------------------------------------------------------------
	210	* Clear Reference Interrupt Status, Timebase freezing enabled
	211	*/
	212	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	213
	214	/*-----------------------------------------------------------------------
	215	* PISCR - Periodic Interrupt Status and Control
	216	*-----------------------------------------------------------------------
	217	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	218	*/
	219	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	220
	221	/*-----------------------------------------------------------------------
	222	* SCCR - System Clock and reset Control Register
	223	*-----------------------------------------------------------------------
	224	* Set clock output, timebase and RTC source and divider,
	225	* power management and some other internal clocks
	226	*/
	227	#define SCCR_MASK SCCR_EBDF00
	228	#define CFG_SCCR (SCCR_TBS \| SCCR_RTDIV \| SCCR_RTSEL \| \
	229	SCCR_COM01 \| SCCR_DFNL000 \| SCCR_DFNH000)
	230
	231	/*-----------------------------------------------------------------------
	232	* SIUMCR - SIU Module Configuration
	233	*-----------------------------------------------------------------------
	234	* Data show cycle
	235	*/
53677ef1	236	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_EARB \| SIUMCR_GPC01 \| SIUMCR_MLRC11) /* Disable data show cycle */
b6e4c403 WD	237
	238	/*-----------------------------------------------------------------------
	239	* PLPRCR - PLL, Low-Power, and Reset Control Register
	240	*-----------------------------------------------------------------------
	241	* Set all bits to 40 Mhz
	242	*
	243	*/
53677ef1	244	#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
b6e4c403 WD	245
	246
	247	#define CFG_PLPRCR (PLPRCR_MF_9 \| PLPRCR_DIVF_0)
	248
	249	/*-----------------------------------------------------------------------
	250	* UMCR - UIMB Module Configuration Register
	251	*-----------------------------------------------------------------------
	252	*
	253	*/
53677ef1	254	#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
b6e4c403 WD	255
	256	/*-----------------------------------------------------------------------
	257	* ICTRL - I-Bus Support Control Register
	258	*/
53677ef1	259	#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
b6e4c403 WD	260
	261	/*-----------------------------------------------------------------------
	262	* USIU - Memory Controller Register
	263	*-----------------------------------------------------------------------
	264	*/
	265	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| BR_V \| BR_BI \| BR_PS_16 \| BR_SETA)
	266	#define CFG_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
	267	/* SDRAM */
	268	#define CFG_BR1_PRELIM (CFG_SDRAM_BASE \| BR_V \| BR_BI \| BR_PS_32 \| BR_SETA)
	269	#define CFG_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
	270	/* PCI */
	271	#define CFG_BR2_PRELIM (PCI_BASE \| BR_V \| BR_PS_32 \| BR_SETA)
	272	#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
	273	/* config registers: */
	274	#define CFG_BR3_PRELIM (PCI_CONFIG_BASE \| BR_V \| BR_BI \| BR_PS_32 \| BR_SETA)
	275	#define CFG_OR3_PRELIM (0xffff0000)
	276
	277	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
	278
	279	/*-----------------------------------------------------------------------
	280	* DER - Timer Decrementer
	281	*-----------------------------------------------------------------------
	282	* Initialise to zero
	283	*/
	284	#define CFG_DER 0x00000000
	285
	286
	287	/*
	288	* Internal Definitions
	289	*
	290	* Boot Flags
	291	*/
	292	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	293	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	294
	295
	296	#define VERSION_TAG "released"
	297	#define CONFIG_ISO_STRING "MEV-10084-001"
	298
	299	#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
	300
	301	#endif /* __CONFIG_H */