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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /*********************************************************** | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | ***********************************************************/ | |
19 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c609719b | 20 | #define CONFIG_PIP405 1 /* ...on a PIP405 board */ |
2ae18241 WD |
21 | |
22 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
23 | ||
c609719b WD |
24 | /*********************************************************** |
25 | * Clock | |
26 | ***********************************************************/ | |
27 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
28 | ||
a1aa0bb5 JL |
29 | /* |
30 | * BOOTP options | |
31 | */ | |
32 | #define CONFIG_BOOTP_BOOTFILESIZE | |
33 | #define CONFIG_BOOTP_BOOTPATH | |
34 | #define CONFIG_BOOTP_GATEWAY | |
35 | #define CONFIG_BOOTP_HOSTNAME | |
36 | ||
acf02697 JL |
37 | /* |
38 | * Command line configuration. | |
39 | */ | |
acf02697 | 40 | #define CONFIG_CMD_IDE |
acf02697 | 41 | #define CONFIG_CMD_PCI |
acf02697 JL |
42 | #define CONFIG_CMD_IRQ |
43 | #define CONFIG_CMD_EEPROM | |
acf02697 JL |
44 | #define CONFIG_CMD_REGINFO |
45 | #define CONFIG_CMD_FDC | |
c649e3c9 | 46 | #define CONFIG_SCSI |
acf02697 | 47 | #define CONFIG_CMD_DATE |
acf02697 | 48 | #define CONFIG_CMD_SDRAM |
acf02697 JL |
49 | #define CONFIG_CMD_SAVES |
50 | #define CONFIG_CMD_BSP | |
51 | ||
c609719b WD |
52 | /************************************************************** |
53 | * I2C Stuff: | |
54 | * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address | |
55 | * 0x53. | |
56 | * Caution: on the same bus is the SPD (Serial Presens Detect | |
57 | * EEPROM of the SDRAM | |
58 | * The Atmel EEPROM uses 16Bit addressing. | |
59 | ***************************************************************/ | |
880540de DE |
60 | #define CONFIG_SYS_I2C |
61 | #define CONFIG_SYS_I2C_PPC4XX | |
62 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
63 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000 | |
64 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 65 | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 |
67 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
bb1f8b4f | 68 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
69 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
70 | #define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */ | |
c609719b | 71 | |
6d0f6bcf JCPV |
72 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
73 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ | |
c609719b WD |
74 | /* 64 byte page write mode using*/ |
75 | /* last 6 bits of the address */ | |
6d0f6bcf | 76 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 77 | |
c609719b WD |
78 | /*************************************************************** |
79 | * Definitions for Serial Presence Detect EEPROM address | |
80 | * (to get SDRAM settings) | |
81 | ***************************************************************/ | |
82 | #define SPD_EEPROM_ADDRESS 0x50 | |
83 | ||
c837dcb1 | 84 | #define CONFIG_BOARD_EARLY_INIT_F |
21be309b DM |
85 | #define CONFIG_BOARD_EARLY_INIT_R |
86 | ||
c609719b WD |
87 | /************************************************************** |
88 | * Environment definitions | |
89 | **************************************************************/ | |
90 | #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ | |
91 | ||
c609719b | 92 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ |
2afbe4ed | 93 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
c609719b | 94 | |
3e38691e | 95 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
c609719b WD |
96 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
97 | ||
98 | #define CONFIG_IPADDR 10.0.0.100 | |
99 | #define CONFIG_SERVERIP 10.0.0.1 | |
100 | #define CONFIG_PREBOOT | |
101 | /*************************************************************** | |
102 | * defines if the console is stored in the environment | |
103 | ***************************************************************/ | |
6d0f6bcf | 104 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ |
c609719b WD |
105 | /*************************************************************** |
106 | * defines if an overwrite_console function exists | |
107 | *************************************************************/ | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
109 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
c609719b WD |
110 | /*************************************************************** |
111 | * defines if the overwrite_console should be stored in the | |
112 | * environment | |
113 | **************************************************************/ | |
6d0f6bcf | 114 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
c609719b WD |
115 | |
116 | /************************************************************** | |
117 | * loads config | |
118 | *************************************************************/ | |
119 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 120 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 121 | |
7205e407 | 122 | #define CONFIG_MISC_INIT_R |
c609719b WD |
123 | /*********************************************************** |
124 | * Miscellaneous configurable options | |
125 | **********************************************************/ | |
6d0f6bcf | 126 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
acf02697 | 127 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 128 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 129 | #else |
6d0f6bcf | 130 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 131 | #endif |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
133 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
134 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
137 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ | |
c609719b | 138 | |
550650dd | 139 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
140 | #define CONFIG_SYS_NS16550_SERIAL |
141 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
142 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
143 | ||
6d0f6bcf JCPV |
144 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
145 | #define CONFIG_SYS_BASE_BAUD 691200 | |
c609719b WD |
146 | |
147 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 148 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
c609719b WD |
149 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
150 | 57600, 115200, 230400, 460800, 921600 } | |
151 | ||
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
153 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 154 | |
c609719b WD |
155 | /*----------------------------------------------------------------------- |
156 | * PCI stuff | |
157 | *----------------------------------------------------------------------- | |
158 | */ | |
159 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
160 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
161 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
162 | ||
163 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 164 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c609719b WD |
165 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ |
166 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
167 | /* resource configuration */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
169 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
170 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
171 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
172 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
173 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
174 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
175 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
c609719b WD |
176 | |
177 | /*----------------------------------------------------------------------- | |
178 | * Start addresses for the final memory configuration | |
179 | * (Set up by the startup code) | |
6d0f6bcf | 180 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 181 | */ |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
183 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
184 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
185 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
186 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
c609719b WD |
187 | |
188 | /* | |
189 | * For booting Linux, the board info and command line data | |
190 | * have to be in the first 8 MB of memory, since this is | |
191 | * the maximum mapped by the Linux kernel during initialization. | |
192 | */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
194 | /*----------------------------------------------------------------------- |
195 | * FLASH organization | |
196 | */ | |
21be309b DM |
197 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
198 | #define CONFIG_SYS_FLASH_PROTECTION | |
199 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
200 | ||
201 | #define CONFIG_SYS_FLASH_CFI | |
202 | #define CONFIG_FLASH_CFI_DRIVER | |
203 | ||
204 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
c609719b | 205 | |
21be309b DM |
206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
207 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
c609719b | 208 | |
c609719b WD |
209 | /* |
210 | * Init Memory Controller: | |
211 | */ | |
7205e407 WD |
212 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
213 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ | |
214 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ | |
215 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ | |
c609719b | 216 | |
c837dcb1 | 217 | #define CONFIG_BOARD_EARLY_INIT_F |
c609719b WD |
218 | |
219 | /* Configuration Port location */ | |
220 | #define CONFIG_PORT_ADDR 0xF4000000 | |
221 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 | |
222 | ||
c609719b WD |
223 | /*----------------------------------------------------------------------- |
224 | * Definitions for initial stack pointer and data area (in On Chip SRAM) | |
225 | */ | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
227 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
228 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
229 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 230 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 231 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 232 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 233 | |
c609719b WD |
234 | /*********************************************************************** |
235 | * External peripheral base address | |
236 | ***********************************************************************/ | |
6d0f6bcf | 237 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
c609719b WD |
238 | |
239 | /*********************************************************************** | |
240 | * Last Stage Init | |
241 | ***********************************************************************/ | |
242 | #define CONFIG_LAST_STAGE_INIT | |
243 | /************************************************************ | |
244 | * Ethernet Stuff | |
245 | ***********************************************************/ | |
96e21f86 | 246 | #define CONFIG_PPC4xx_EMAC |
c609719b WD |
247 | #define CONFIG_MII 1 /* MII PHY management */ |
248 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
c609719b WD |
249 | /************************************************************ |
250 | * RTC | |
251 | ***********************************************************/ | |
252 | #define CONFIG_RTC_MC146818 | |
253 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
254 | ||
255 | /************************************************************ | |
256 | * IDE/ATA stuff | |
257 | ************************************************************/ | |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
259 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
c609719b | 260 | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
262 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
263 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
264 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
265 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
266 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
c609719b WD |
267 | |
268 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
269 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
270 | #define CONFIG_IDE_RESET /* reset for ide supported... */ | |
271 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
7205e407 | 272 | #define CONFIG_SUPPORT_VFAT |
c609719b WD |
273 | |
274 | /************************************************************ | |
275 | * ATAPI support (experimental) | |
276 | ************************************************************/ | |
277 | #define CONFIG_ATAPI /* enable ATAPI Support */ | |
278 | ||
279 | /************************************************************ | |
280 | * SCSI support (experimental) only SYM53C8xx supported | |
281 | ************************************************************/ | |
282 | #define CONFIG_SCSI_SYM53C8XX | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */ |
284 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ | |
285 | #define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */ | |
286 | #define CONFIG_SYS_SCSI_SPIN_UP_TIME 2 | |
c609719b WD |
287 | |
288 | /************************************************************ | |
289 | * Disk-On-Chip configuration | |
290 | ************************************************************/ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
292 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT | |
293 | #define CONFIG_SYS_DOC_SUPPORT_2000 | |
294 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
c609719b WD |
295 | |
296 | /************************************************************ | |
297 | * DISK Partition support | |
298 | ************************************************************/ | |
299 | #define CONFIG_DOS_PARTITION | |
300 | #define CONFIG_MAC_PARTITION | |
301 | #define CONFIG_ISO_PARTITION /* Experimental */ | |
302 | ||
c609719b WD |
303 | /************************************************************ |
304 | * Video support | |
305 | ************************************************************/ | |
306 | #define CONFIG_VIDEO /*To enable video controller support */ | |
307 | #define CONFIG_VIDEO_CT69000 | |
308 | #define CONFIG_CFB_CONSOLE | |
309 | #define CONFIG_VIDEO_LOGO | |
310 | #define CONFIG_CONSOLE_EXTRA_INFO | |
311 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
312 | #define CONFIG_VIDEO_SW_CURSOR | |
313 | #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ | |
314 | ||
315 | /************************************************************ | |
316 | * USB support | |
317 | ************************************************************/ | |
318 | #define CONFIG_USB_UHCI | |
319 | #define CONFIG_USB_KEYBOARD | |
c609719b WD |
320 | |
321 | /* Enable needed helper functions */ | |
52cb4d4f | 322 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
c609719b WD |
323 | |
324 | /************************************************************ | |
325 | * Debug support | |
326 | ************************************************************/ | |
acf02697 | 327 | #if defined(CONFIG_CMD_KGDB) |
c609719b | 328 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
c609719b WD |
329 | #endif |
330 | ||
a2663ea4 WD |
331 | /************************************************************ |
332 | * support BZIP2 compression | |
333 | ************************************************************/ | |
334 | #define CONFIG_BZIP2 1 | |
335 | ||
c609719b WD |
336 | /************************************************************ |
337 | * Ident | |
338 | ************************************************************/ | |
339 | #define VERSION_TAG "released" | |
f3e0de60 | 340 | #define CONFIG_ISO_STRING "MEV-10066-001" |
c609719b | 341 | |
c609719b | 342 | #endif /* __CONFIG_H */ |