[people/ms/u-boot.git] / include / configs / PIP405.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#define CONFIG_SYS_GENERIC_BOARD

/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FDC
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP

#define	 CONFIG_SYS_HUSH_PARSER
/**************************************************************
 * I2C Stuff:
 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * Caution: on the same bus is the SPD (Serial Presens Detect
 * EEPROM of the SDRAM
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */

#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */


/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
#define SPD_EEPROM_ADDRESS      0x50

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R

/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */


#define CONFIG_BOOTDELAY	5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */


#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if the console is stored in the environment
 ***************************************************************/
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFF80000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_UPDATE_FLASH_SIZE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

/*
 * Init Memory Controller:
 */
#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/

#define CONFIG_BOARD_EARLY_INIT_F

/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF4000000
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
#define CONFIG_SUPPORT_VFAT

/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * SCSI support (experimental) only SYM53C8xx supported
 ************************************************************/
#define CONFIG_SCSI_SYM53C8XX
#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2

/************************************************************
 * Disk-On-Chip configuration
 ************************************************************/
#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM

/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Keyboard support
 ************************************************************/
#define CONFIG_ISA_KEYBOARD

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO			/*To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */

/************************************************************
 * USB support
 ************************************************************/
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE

/* Enable needed helper functions */
#define CONFIG_SYS_STDIO_DEREGISTER		/* needs stdio_deregister */

/************************************************************
 * Debug support
 ************************************************************/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/************************************************************
 * support BZIP2 compression
 ************************************************************/
#define CONFIG_BZIP2		1

/************************************************************
 * Ident
 ************************************************************/
#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10066-001"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/***********************************************************
	16	* High Level Configuration Options
	17	* (easy to change)
	18	***********************************************************/
	19	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c609719b	20	#define CONFIG_PIP405 1 /* ...on a PIP405 board */
2ae18241 WD	21
	22	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
	23
3f2b5bb6 DMEA	24	#define CONFIG_SYS_GENERIC_BOARD
3f2b5bb6 DMEA	25
c609719b WD	26	/***********************************************************
	27	* Clock
	28	***********************************************************/
	29	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	30
acf02697	31
a1aa0bb5 JL	32	/*
	33	* BOOTP options
	34	*/
	35	#define CONFIG_BOOTP_BOOTFILESIZE
	36	#define CONFIG_BOOTP_BOOTPATH
	37	#define CONFIG_BOOTP_GATEWAY
	38	#define CONFIG_BOOTP_HOSTNAME
	39
	40
acf02697 JL	41	/*
	42	* Command line configuration.
	43	*/
acf02697 JL	44	#define CONFIG_CMD_IDE
	45	#define CONFIG_CMD_DHCP
	46	#define CONFIG_CMD_PCI
	47	#define CONFIG_CMD_CACHE
	48	#define CONFIG_CMD_IRQ
	49	#define CONFIG_CMD_EEPROM
	50	#define CONFIG_CMD_I2C
	51	#define CONFIG_CMD_REGINFO
	52	#define CONFIG_CMD_FDC
	53	#define CONFIG_CMD_SCSI
	54	#define CONFIG_CMD_FAT
	55	#define CONFIG_CMD_DATE
	56	#define CONFIG_CMD_ELF
	57	#define CONFIG_CMD_USB
	58	#define CONFIG_CMD_MII
	59	#define CONFIG_CMD_SDRAM
acf02697 JL	60	#define CONFIG_CMD_PING
	61	#define CONFIG_CMD_SAVES
	62	#define CONFIG_CMD_BSP
	63
6d0f6bcf	64	#define CONFIG_SYS_HUSH_PARSER
c609719b WD	65	/**************************************************************
	66	* I2C Stuff:
	67	* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	68	* 0x53.
	69	* Caution: on the same bus is the SPD (Serial Presens Detect
	70	* EEPROM of the SDRAM
	71	* The Atmel EEPROM uses 16Bit addressing.
	72	***************************************************************/
880540de DE	73	#define CONFIG_SYS_I2C
	74	#define CONFIG_SYS_I2C_PPC4XX
	75	#define CONFIG_SYS_I2C_PPC4XX_CH0
	76	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
	77	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	78
6d0f6bcf JCPV	79	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
6d0f6bcf JCPV	80	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
bb1f8b4f	81	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	82	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	83	#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
c609719b	84
6d0f6bcf JCPV	85	#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
6d0f6bcf JCPV	86	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
c609719b WD	87	/* 64 byte page write mode using*/
c609719b WD	88	/* last 6 bits of the address */
6d0f6bcf	89	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b WD	90
	91
	92	/***************************************************************
	93	* Definitions for Serial Presence Detect EEPROM address
	94	* (to get SDRAM settings)
	95	***************************************************************/
	96	#define SPD_EEPROM_ADDRESS 0x50
	97
c837dcb1	98	#define CONFIG_BOARD_EARLY_INIT_F
21be309b DM	99	#define CONFIG_BOARD_EARLY_INIT_R
21be309b DM	100
c609719b WD	101	/**************************************************************
	102	* Environment definitions
	103	**************************************************************/
	104	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
	105
	106
	107	#define CONFIG_BOOTDELAY 5
	108	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed	109	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
53677ef1	110	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
c609719b WD	111
c609719b WD	112
3e38691e	113	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
c609719b WD	114	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	115
	116	#define CONFIG_IPADDR 10.0.0.100
	117	#define CONFIG_SERVERIP 10.0.0.1
	118	#define CONFIG_PREBOOT
	119	/***************************************************************
	120	* defines if the console is stored in the environment
	121	***************************************************************/
6d0f6bcf	122	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
c609719b WD	123	/***************************************************************
	124	* defines if an overwrite_console function exists
	125	*************************************************************/
6d0f6bcf JCPV	126	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
6d0f6bcf JCPV	127	#define CONFIG_SYS_CONSOLE_INFO_QUIET
c609719b WD	128	/***************************************************************
	129	* defines if the overwrite_console should be stored in the
	130	* environment
	131	**************************************************************/
6d0f6bcf	132	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
c609719b WD	133
	134	/**************************************************************
	135	* loads config
	136	*************************************************************/
	137	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	138	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	139
7205e407	140	#define CONFIG_MISC_INIT_R
c609719b WD	141	/***********************************************************
	142	* Miscellaneous configurable options
	143	**********************************************************/
6d0f6bcf	144	#define CONFIG_SYS_LONGHELP /* undef to save memory */
acf02697	145	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	146	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	147	#else
6d0f6bcf	148	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	149	#endif
6d0f6bcf JCPV	150	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	151	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	152	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	153
6d0f6bcf JCPV	154	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
6d0f6bcf JCPV	155	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
c609719b	156
550650dd SR	157	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	158	#define CONFIG_SYS_NS16550
	159	#define CONFIG_SYS_NS16550_SERIAL
	160	#define CONFIG_SYS_NS16550_REG_SIZE 1
	161	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	162
6d0f6bcf JCPV	163	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf JCPV	164	#define CONFIG_SYS_BASE_BAUD 691200
c609719b WD	165
c609719b WD	166	/* The following table includes the supported baudrates */
6d0f6bcf	167	#define CONFIG_SYS_BAUDRATE_TABLE \
c609719b WD	168	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	169	57600, 115200, 230400, 460800, 921600 }
	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
6d0f6bcf JCPV	172	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	173
c609719b WD	174	/*-----------------------------------------------------------------------
	175	* PCI stuff
	176	*-----------------------------------------------------------------------
	177	*/
	178	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	179	#define PCI_HOST_FORCE 1 /* configure as pci host */
	180	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	181
	182	#define CONFIG_PCI /* include pci support */
842033e6	183	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c609719b WD	184	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	185	#define CONFIG_PCI_PNP /* pci plug-and-play */
	186	/* resource configuration */
6d0f6bcf JCPV	187	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	188	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	189	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	190	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	191	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	192	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	193	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	194	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
c609719b WD	195
	196	/*-----------------------------------------------------------------------
	197	* Start addresses for the final memory configuration
	198	* (Set up by the startup code)
6d0f6bcf	199	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	200	*/
6d0f6bcf JCPV	201	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	202	#define CONFIG_SYS_FLASH_BASE 0xFFF80000
	203	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	204	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	205	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
c609719b WD	206
	207	/*
	208	* For booting Linux, the board info and command line data
	209	* have to be in the first 8 MB of memory, since this is
	210	* the maximum mapped by the Linux kernel during initialization.
	211	*/
6d0f6bcf	212	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	213	/*-----------------------------------------------------------------------
	214	* FLASH organization
	215	*/
21be309b DM	216	#define CONFIG_SYS_UPDATE_FLASH_SIZE
	217	#define CONFIG_SYS_FLASH_PROTECTION
	218	#define CONFIG_SYS_FLASH_EMPTY_INFO
	219
	220	#define CONFIG_SYS_FLASH_CFI
	221	#define CONFIG_FLASH_CFI_DRIVER
	222
	223	#define CONFIG_FLASH_SHOW_PROGRESS 45
c609719b	224
21be309b DM	225	#define CONFIG_SYS_MAX_FLASH_BANKS 1
21be309b DM	226	#define CONFIG_SYS_MAX_FLASH_SECT 256
c609719b	227
c609719b WD	228	/*
	229	* Init Memory Controller:
	230	*/
7205e407 WD	231	#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
	232	#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
	233	/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
	234	#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
c609719b	235
c837dcb1	236	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	237
	238	/* Configuration Port location */
	239	#define CONFIG_PORT_ADDR 0xF4000000
	240	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
	241
	242
c609719b WD	243	/*-----------------------------------------------------------------------
	244	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	245	*/
6d0f6bcf JCPV	246	#define CONFIG_SYS_TEMP_STACK_OCM 1
	247	#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
	248	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	249	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
553f0982	250	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
25ddd1fb	251	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	252	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	253
c609719b WD	254	/***********************************************************************
	255	* External peripheral base address
	256	***********************************************************************/
6d0f6bcf	257	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
c609719b WD	258
	259	/***********************************************************************
	260	* Last Stage Init
	261	***********************************************************************/
	262	#define CONFIG_LAST_STAGE_INIT
	263	/************************************************************
	264	* Ethernet Stuff
	265	***********************************************************/
96e21f86	266	#define CONFIG_PPC4xx_EMAC
c609719b WD	267	#define CONFIG_MII 1 /* MII PHY management */
c609719b WD	268	#define CONFIG_PHY_ADDR 1 /* PHY address */
c609719b WD	269	/************************************************************
	270	* RTC
	271	***********************************************************/
	272	#define CONFIG_RTC_MC146818
	273	#undef CONFIG_WATCHDOG /* watchdog disabled */
	274
	275	/************************************************************
	276	* IDE/ATA stuff
	277	************************************************************/
6d0f6bcf JCPV	278	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	279	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
c609719b	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
	282	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	283	#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	284	#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
	285	#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
	286	#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
c609719b WD	287
	288	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	289	#undef CONFIG_IDE_LED /* no led for ide supported */
	290	#define CONFIG_IDE_RESET /* reset for ide supported... */
	291	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407	292	#define CONFIG_SUPPORT_VFAT
c609719b WD	293
	294	/************************************************************
	295	* ATAPI support (experimental)
	296	************************************************************/
	297	#define CONFIG_ATAPI /* enable ATAPI Support */
	298
	299	/************************************************************
	300	* SCSI support (experimental) only SYM53C8xx supported
	301	************************************************************/
	302	#define CONFIG_SCSI_SYM53C8XX
6d0f6bcf JCPV	303	#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
	304	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
	305	#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
	306	#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
c609719b WD	307
	308	/************************************************************
	309	* Disk-On-Chip configuration
	310	************************************************************/
6d0f6bcf JCPV	311	#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	312	#define CONFIG_SYS_DOC_SHORT_TIMEOUT
	313	#define CONFIG_SYS_DOC_SUPPORT_2000
	314	#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
c609719b WD	315
	316	/************************************************************
	317	* DISK Partition support
	318	************************************************************/
	319	#define CONFIG_DOS_PARTITION
	320	#define CONFIG_MAC_PARTITION
	321	#define CONFIG_ISO_PARTITION /* Experimental */
	322
	323	/************************************************************
	324	* Keyboard support
	325	************************************************************/
	326	#define CONFIG_ISA_KEYBOARD
	327
	328	/************************************************************
	329	* Video support
	330	************************************************************/
	331	#define CONFIG_VIDEO /To enable video controller support /
	332	#define CONFIG_VIDEO_CT69000
	333	#define CONFIG_CFB_CONSOLE
	334	#define CONFIG_VIDEO_LOGO
	335	#define CONFIG_CONSOLE_EXTRA_INFO
	336	#define CONFIG_VGA_AS_SINGLE_DEVICE
	337	#define CONFIG_VIDEO_SW_CURSOR
	338	#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
	339
	340	/************************************************************
	341	* USB support
	342	************************************************************/
	343	#define CONFIG_USB_UHCI
	344	#define CONFIG_USB_KEYBOARD
	345	#define CONFIG_USB_STORAGE
	346
	347	/* Enable needed helper functions */
52cb4d4f	348	#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
c609719b WD	349
	350	/************************************************************
	351	* Debug support
	352	************************************************************/
acf02697	353	#if defined(CONFIG_CMD_KGDB)
c609719b	354	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
c609719b WD	355	#endif
c609719b WD	356
a2663ea4 WD	357	/************************************************************
	358	* support BZIP2 compression
	359	************************************************************/
	360	#define CONFIG_BZIP2 1
	361
c609719b WD	362	/************************************************************
	363	* Ident
	364	************************************************************/
	365	#define VERSION_TAG "released"
f3e0de60 WD	366	#define CONFIG_ISO_STRING "MEV-10066-001"
f3e0de60 WD	367	#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
c609719b WD	368
	369
	370	#endif /* __CONFIG_H */