[people/ms/u-boot.git] / include / configs / PM826.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef CFG_RAMBOOT

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
#define CONFIG_PM826		1	/* ...on a PM8260 module	*/

#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; " 								\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
	"bootm"

/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
# define CFG_I2C_SPEED		50000
# define CFG_I2C_SLAVE		0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR	0x51

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if CONFIG_ETHER_ON_SCC is selected, then
 *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
 *   - CONFIG_NET_MULTI must not be defined
 *
 * if CONFIG_ETHER_ON_FCC is selected, then
 *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
 *   - CONFIG_NET_MULTI must be defined
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#define	CONFIG_NET_MULTI
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */

#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK10
 */
#define	CONFIG_ETHER_ON_FCC1
# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
#ifndef CONFIG_DB_CR826_J30x_ON
# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
#else
# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
#endif
/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK14
 */
#define	CONFIG_ETHER_ON_FCC2
# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
/*
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)

#ifdef CONFIG_PCI
#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
				 CFG_CMD_BEDBUG	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_I2C	| \
				 CFG_CMD_PCI)
#else	/* ! PCI */
#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
				 CFG_CMD_BEDBUG	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_I2C	)
#endif	/* CONFIG_PCI */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Disk-On-Chip configuration
 */

#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/

#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash and Boot ROM mapping
 */

#define	CFG_BOOTROM_BASE	0xFF800000
#define	CFG_BOOTROM_SIZE	0x00080000
#define	CFG_FLASH0_BASE		0xFF000000
#define	CFG_FLASH0_SIZE		0x02000000
#define CFG_DOC_BASE		0xFF800000
#define CFG_DOC_SIZE		0x00100000


/* Flash bank size (for preliminary settings)
 */
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#if 0
/* Start port with environment in flash; switch to EEPROM later */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
#define CFG_ENV_SIZE		0x40000
#define CFG_ENV_SECT_SIZE	0x40000
#else
/* Final version: environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_I2C_EEPROM_ADDR	0x58
#define CFG_I2C_EEPROM_ADDR_LEN	1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CFG_ENV_OFFSET		512
#define CFG_ENV_SIZE		(2048 - 512)
#endif

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#if defined(CONFIG_BOOT_ROM)
#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#else
#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#endif

/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1		0
#define CFG_HRCW_SLAVE2		0
#define CFG_HRCW_SLAVE3		0
#define CFG_HRCW_SLAVE4		0
#define CFG_HRCW_SLAVE5		0
#define CFG_HRCW_SLAVE6		0
#define CFG_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 * is mapped at SDRAM_BASE2_PRELIM.
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		CFG_FLASH0_BASE
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif

#ifdef	CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM		0x02	/* Software reboot                 */


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */

#define BCR_APD01       0x10000000
#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#if 0
#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
#else
#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 */
#define CFG_SCCR        (SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    64 bit  FLASH
 *  1   60x     SDRAM   64 bit  SDRAM
 *  2   Local   SDRAM   32 bit  SDRAM
 *
 */

	/* Initialize SDRAM on local bus
	 */
#define CFG_INIT_LOCAL_SDRAM


/* Minimum mask to separate preliminary
 * address ranges for CS[0:2]
 */
#define CFG_MIN_AM_MASK	0xC0000000

#define CFG_MPTPR       0x1F00

#define CFG_MRS_OFFS	0x00000000


#if defined(CONFIG_BOOT_ROM)
/*
 * Bank 0 - Boot ROM (8 bit wide)
 */
#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

/*
 * Bank 1 - Flash (64 bit wide)
 */
#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#else	/* ! CONFIG_BOOT_ROM */

/*
 * Bank 0 - Flash (64 bit wide)
 */
#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxG_EHTR                      |\
			 ORxG_TRLX)

/*
 * Bank 1 - Disk-On-Chip
 */
#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#endif /* CONFIG_BOOT_ROM */

/* Bank 2 - SDRAM
 */
#define CFG_PSRT        0x0F
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

	/* SDRAM initialization values for 8-column chips
	 */
#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A9             |\
			 ORxS_NUMR_12)

#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
			 PSDMR_BSMA_A14_A16             |\
			 PSDMR_SDA10_PBI0_A10           |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A7             |\
			 ORxS_NUMR_13)

#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
			 PSDMR_BSMA_A13_A15             |\
			 PSDMR_SDA10_PBI0_A9            |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

#define CFG_OR2_PRELIM   CFG_OR2_9COL
#define CFG_PSDMR        CFG_PSDMR_9COL

#endif /* CFG_RAMBOOT */

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#undef CFG_RAMBOOT
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
	39	#define CONFIG_PM826 1 /* ...on a PM8260 module */
	40
aacf9a49 WD	41	#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
aacf9a49 WD	42
0f8c9768 WD	43	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	44
	45	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	46
	47	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	48
	49	#undef CONFIG_BOOTARGS
	50	#define CONFIG_BOOTCOMMAND \
	51	"bootp; " \
	52	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	53	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	54	"bootm"
	55
	56	/* enable I2C and select the hardware/software driver */
	57	#undef CONFIG_HARD_I2C
	58	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	59	# define CFG_I2C_SPEED 50000
	60	# define CFG_I2C_SLAVE 0xFE
	61	/*
	62	* Software (bit-bang) I2C driver configuration
	63	*/
	64	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	65	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	66	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	67	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	68	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	69	else iop->pdat &= ~0x00010000
	70	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	71	else iop->pdat &= ~0x00020000
	72	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	73
	74
	75	#define CONFIG_RTC_PCF8563
	76	#define CFG_I2C_RTC_ADDR 0x51
	77
	78	/*
	79	* select serial console configuration
	80	*
	81	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	82	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	83	* for SCC).
	84	*
	85	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	86	* defined elsewhere (for example, on the cogent platform, there are serial
	87	* ports on the motherboard which are used for the serial console - see
	88	* cogent/cma101/serial.[ch]).
	89	*/
	90	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	91	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	92	#undef CONFIG_CONS_NONE /* define if console on something else*/
	93	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	94
	95	/*
	96	* select ethernet configuration
	97	*
aacf9a49 WD	98	* if CONFIG_ETHER_ON_SCC is selected, then
	99	* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
	100	* - CONFIG_NET_MULTI must not be defined
	101	*
	102	* if CONFIG_ETHER_ON_FCC is selected, then
	103	* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
	104	* - CONFIG_NET_MULTI must be defined
0f8c9768 WD	105	*
	106	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
	107	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
	108	* from CONFIG_COMMANDS to remove support for networking.
	109	*/
aacf9a49	110	#define CONFIG_NET_MULTI
0f8c9768	111	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0f8c9768	112
aacf9a49 WD	113	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	114	#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
	115
	116	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
0f8c9768 WD	117	/*
	118	* - Rx-CLK is CLK11
	119	* - Tx-CLK is CLK10
aacf9a49 WD	120	*/
	121	#define CONFIG_ETHER_ON_FCC1
	122	# define CFG_CMXFCR_MASK1 (CMXFCR_FC1\|CMXFCR_RF1CS_MSK\|CMXFCR_TF1CS_MSK)
	123	#ifndef CONFIG_DB_CR826_J30x_ON
	124	# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK10)
	125	#else
	126	# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK12)
	127	#endif
	128	/*
	129	* - Rx-CLK is CLK15
	130	* - Tx-CLK is CLK14
	131	*/
	132	#define CONFIG_ETHER_ON_FCC2
	133	# define CFG_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	134	# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	135	/*
0f8c9768 WD	136	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	137	* - Enable Full Duplex in FSMR
	138	*/
0f8c9768 WD	139	# define CFG_CPMFCR_RAMTYPE 0
	140	# define CFG_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
	141
0f8c9768 WD	142	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	143	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	144
	145	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
	146	#define CONFIG_BAUDRATE 230400
	147	#else
	148	#define CONFIG_BAUDRATE 9600
	149	#endif
	150
	151	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	152	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	153
	154	#undef CONFIG_WATCHDOG /* watchdog disabled */
	155
	156	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT\|CONFIG_BOOTP_BOOTFILESIZE)
	157
5d232d0e WD	158	#ifdef CONFIG_PCI
	159	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	160	CFG_CMD_BEDBUG \| \
	161	CFG_CMD_DATE \| \
	162	CFG_CMD_DOC \| \
	163	CFG_CMD_EEPROM \| \
	164	CFG_CMD_I2C \| \
	165	CFG_CMD_PCI)
	166	#else /* ! PCI */
0f8c9768 WD	167	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	168	CFG_CMD_BEDBUG \| \
	169	CFG_CMD_DATE \| \
3bac3513	170	CFG_CMD_DOC \| \
0f8c9768	171	CFG_CMD_EEPROM \| \
3bac3513	172	CFG_CMD_I2C )
5d232d0e	173	#endif /* CONFIG_PCI */
0f8c9768 WD	174
	175	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	176	#include <cmd_confdefs.h>
	177
	178	/*
	179	* Disk-On-Chip configuration
	180	*/
	181
	182	#define CFG_DOC_SHORT_TIMEOUT
	183	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	184
	185	#define CFG_DOC_SUPPORT_2000
	186	#define CFG_DOC_SUPPORT_MILLENNIUM
	187
	188	/*
	189	* Miscellaneous configurable options
	190	*/
	191	#define CFG_LONGHELP /* undef to save memory */
	192	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	193	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	194	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	195	#else
	196	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	197	#endif
	198	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	199	#define CFG_MAXARGS 16 /* max number of command args */
	200	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	201
	202	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	203	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	204
	205	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	206
	207	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	208
	209	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	210
ac6dbb85	211	#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
0f8c9768 WD	212
	213	/*
	214	* For booting Linux, the board info and command line data
	215	* have to be in the first 8 MB of memory, since this is
	216	* the maximum mapped by the Linux kernel during initialization.
	217	*/
	218	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	219
	220	/*-----------------------------------------------------------------------
	221	* Flash and Boot ROM mapping
	222	*/
	223
3bac3513	224	#define CFG_BOOTROM_BASE 0xFF800000
0f8c9768	225	#define CFG_BOOTROM_SIZE 0x00080000
3bac3513	226	#define CFG_FLASH0_BASE 0xFF000000
0f8c9768	227	#define CFG_FLASH0_SIZE 0x02000000
3bac3513	228	#define CFG_DOC_BASE 0xFF800000
0f8c9768 WD	229	#define CFG_DOC_SIZE 0x00100000
	230
	231
	232	/* Flash bank size (for preliminary settings)
	233	*/
	234	#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
	235
	236	/*-----------------------------------------------------------------------
	237	* FLASH organization
	238	*/
	239	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	240	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	241
	242	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	243	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	244
	245	#if 0
	246	/* Start port with environment in flash; switch to EEPROM later */
	247	#define CFG_ENV_IS_IN_FLASH 1
	248	#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
	249	#define CFG_ENV_SIZE 0x40000
	250	#define CFG_ENV_SECT_SIZE 0x40000
	251	#else
	252	/* Final version: environment in EEPROM */
	253	#define CFG_ENV_IS_IN_EEPROM 1
	254	#define CFG_I2C_EEPROM_ADDR 0x58
	255	#define CFG_I2C_EEPROM_ADDR_LEN 1
	256	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	257	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
3bac3513 WD	258	#define CFG_ENV_OFFSET 512
3bac3513 WD	259	#define CFG_ENV_SIZE (2048 - 512)
0f8c9768 WD	260	#endif
	261
	262	/*-----------------------------------------------------------------------
	263	* Hard Reset Configuration Words
	264	*
	265	* if you change bits in the HRCW, you must also change the CFG_*
	266	* defines for the various registers affected by the HRCW e.g. changing
	267	* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
	268	*/
	269	#if defined(CONFIG_BOOT_ROM)
	270	#define CFG_HRCW_MASTER (HRCW_BPS01 \| HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
	271	#else
	272	#define CFG_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
	273	#endif
	274
	275	/* no slaves so just fill with zeros */
	276	#define CFG_HRCW_SLAVE1 0
	277	#define CFG_HRCW_SLAVE2 0
	278	#define CFG_HRCW_SLAVE3 0
	279	#define CFG_HRCW_SLAVE4 0
	280	#define CFG_HRCW_SLAVE5 0
	281	#define CFG_HRCW_SLAVE6 0
	282	#define CFG_HRCW_SLAVE7 0
	283
	284	/*-----------------------------------------------------------------------
	285	* Internal Memory Mapped Register
	286	*/
	287	#define CFG_IMMR 0xF0000000
	288
	289	/*-----------------------------------------------------------------------
	290	* Definitions for initial stack pointer and data area (in DPRAM)
	291	*/
	292	#define CFG_INIT_RAM_ADDR CFG_IMMR
	293	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
	294	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
	295	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	296	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	297
	298	/*-----------------------------------------------------------------------
	299	* Start addresses for the final memory configuration
	300	* (Set up by the startup code)
	301	* Please note that CFG_SDRAM_BASE _must_ start at 0
	302	*
	303	* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
	304	* is mapped at SDRAM_BASE2_PRELIM.
	305	*/
	306	#define CFG_SDRAM_BASE 0x00000000
	307	#define CFG_FLASH_BASE CFG_FLASH0_BASE
	308	#define CFG_MONITOR_BASE TEXT_BASE
	309	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	310	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
	311
	312	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	313	# define CFG_RAMBOOT
	314	#endif
	315
10f67017	316	#ifdef CONFIG_PCI
4d75a504 WD	317	#define CONFIG_PCI_PNP
4d75a504 WD	318	#define CONFIG_EEPRO100
53cf9435	319	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
10f67017	320	#endif
4d75a504	321
0f8c9768 WD	322	/*
	323	* Internal Definitions
	324	*
	325	* Boot Flags
	326	*/
	327	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
	328	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	329
	330
	331	/*-----------------------------------------------------------------------
	332	* Cache Configuration
	333	*/
	334	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
	335	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	336	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	337	#endif
	338
	339	/*-----------------------------------------------------------------------
	340	* HIDx - Hardware Implementation-dependent Registers 2-11
	341	*-----------------------------------------------------------------------
	342	* HID0 also contains cache control - initially enable both caches and
	343	* invalidate contents, then the final state leaves only the instruction
	344	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	345	* but Soft reset does not.
	346	*
	347	* HID1 has only read-only information - nothing to set.
	348	*/
	349	#define CFG_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
8bde7f77	350	HID0_IFEM\|HID0_ABE)
0f8c9768 WD	351	#define CFG_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
	352	#define CFG_HID2 0
	353
	354	/*-----------------------------------------------------------------------
	355	* RMR - Reset Mode Register 5-5
	356	*-----------------------------------------------------------------------
	357	* turn on Checkstop Reset Enable
	358	*/
	359	#define CFG_RMR RMR_CSRE
	360
	361	/*-----------------------------------------------------------------------
	362	* BCR - Bus Configuration 4-25
	363	*-----------------------------------------------------------------------
	364	*/
	365
	366	#define BCR_APD01 0x10000000
	367	#define CFG_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
	368
	369	/*-----------------------------------------------------------------------
	370	* SIUMCR - SIU Module Configuration 4-31
	371	*-----------------------------------------------------------------------
	372	*/
	373	#if 0
	374	#define CFG_SIUMCR (SIUMCR_DPPC00\|SIUMCR_APPC10\|SIUMCR_CS10PC01)
	375	#else
	376	#define CFG_SIUMCR (SIUMCR_DPPC10\|SIUMCR_APPC10)
	377	#endif
	378
	379
	380	/*-----------------------------------------------------------------------
	381	* SYPCR - System Protection Control 4-35
	382	* SYPCR can only be written once after reset!
	383	*-----------------------------------------------------------------------
	384	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	385	*/
	386	#if defined(CONFIG_WATCHDOG)
	387	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	388	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
0f8c9768 WD	389	#else
0f8c9768 WD	390	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	391	SYPCR_SWRI\|SYPCR_SWP)
0f8c9768 WD	392	#endif /* CONFIG_WATCHDOG */
	393
	394	/*-----------------------------------------------------------------------
	395	* TMCNTSC - Time Counter Status and Control 4-40
	396	*-----------------------------------------------------------------------
	397	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	398	* and enable Time Counter
	399	*/
	400	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	401
	402	/*-----------------------------------------------------------------------
	403	* PISCR - Periodic Interrupt Status and Control 4-42
	404	*-----------------------------------------------------------------------
	405	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	406	* Periodic timer
	407	*/
	408	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	409
	410	/*-----------------------------------------------------------------------
	411	* SCCR - System Clock Control 9-8
	412	*-----------------------------------------------------------------------
	413	*/
	414	#define CFG_SCCR (SCCR_DFBRG01)
	415
	416	/*-----------------------------------------------------------------------
	417	* RCCR - RISC Controller Configuration 13-7
	418	*-----------------------------------------------------------------------
	419	*/
	420	#define CFG_RCCR 0
	421
	422	/*
	423	* Init Memory Controller:
	424	*
	425	* Bank Bus Machine PortSz Device
	426	* ---- --- ------- ------ ------
	427	* 0 60x GPCM 64 bit FLASH
	428	* 1 60x SDRAM 64 bit SDRAM
	429	* 2 Local SDRAM 32 bit SDRAM
	430	*
	431	*/
	432
	433	/* Initialize SDRAM on local bus
	434	*/
	435	#define CFG_INIT_LOCAL_SDRAM
	436
	437
	438	/* Minimum mask to separate preliminary
	439	* address ranges for CS[0:2]
	440	*/
	441	#define CFG_MIN_AM_MASK 0xC0000000
	442
	443	#define CFG_MPTPR 0x1F00
	444
	445	#define CFG_MRS_OFFS 0x00000000
	446
	447
	448	#if defined(CONFIG_BOOT_ROM)
	449	/*
	450	* Bank 0 - Boot ROM (8 bit wide)
	451	*/
	452	#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)\|\
	453	BRx_PS_8 \|\
	454	BRx_MS_GPCM_P \|\
	455	BRx_V)
456
457	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) \|\
458	ORxG_CSNT \|\
459	ORxG_ACS_DIV1 \|\
460	ORxG_SCY_3_CLK \|\
461	ORxG_EHTR \|\
462	ORxG_TRLX)
463
464	/*
465	* Bank 1 - Flash (64 bit wide)
466	*/
467	#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
468	BRx_PS_64 \|\
469	BRx_MS_GPCM_P \|\
470	BRx_V)
471
472	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
473	ORxG_CSNT \|\
474	ORxG_ACS_DIV1 \|\
475	ORxG_SCY_3_CLK \|\
476	ORxG_EHTR \|\
477	ORxG_TRLX)
478
479	#else /* ! CONFIG_BOOT_ROM */
480
481	/*
482	* Bank 0 - Flash (64 bit wide)
483	*/
484	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	485	BRx_PS_64 \|\
	486	BRx_MS_GPCM_P \|\
	487	BRx_V)
0f8c9768 WD	488
0f8c9768 WD	489	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
8bde7f77 WD	490	ORxG_CSNT \|\
	491	ORxG_ACS_DIV1 \|\
	492	ORxG_SCY_3_CLK \|\
	493	ORxG_EHTR \|\
	494	ORxG_TRLX)
0f8c9768 WD	495
	496	/*
	497	* Bank 1 - Disk-On-Chip
	498	*/
	499	#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) \|\
	500	BRx_PS_8 \|\
	501	BRx_MS_GPCM_P \|\
	502	BRx_V)
	503
	504	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) \|\
	505	ORxG_CSNT \|\
	506	ORxG_ACS_DIV1 \|\
	507	ORxG_SCY_3_CLK \|\
	508	ORxG_EHTR \|\
	509	ORxG_TRLX)
	510
	511	#endif /* CONFIG_BOOT_ROM */
	512
	513	/* Bank 2 - SDRAM
	514	*/
	515	#define CFG_PSRT 0x0F
	516	#ifndef CFG_RAMBOOT
	517	#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	518	BRx_PS_64 \|\
	519	BRx_MS_SDRAM_P \|\
	520	BRx_V)
0f8c9768 WD	521
	522	/* SDRAM initialization values for 8-column chips
	523	*/
	524	#define CFG_OR2_8COL (CFG_MIN_AM_MASK \|\
8bde7f77 WD	525	ORxS_BPD_4 \|\
	526	ORxS_ROWST_PBI0_A9 \|\
	527	ORxS_NUMR_12)
0f8c9768 WD	528
0f8c9768 WD	529	#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 \|\
8bde7f77 WD	530	PSDMR_BSMA_A14_A16 \|\
	531	PSDMR_SDA10_PBI0_A10 \|\
	532	PSDMR_RFRC_7_CLK \|\
	533	PSDMR_PRETOACT_2W \|\
	534	PSDMR_ACTTORW_1W \|\
	535	PSDMR_LDOTOPRE_1C \|\
	536	PSDMR_WRC_1C \|\
	537	PSDMR_CL_2)
0f8c9768 WD	538
	539	/* SDRAM initialization values for 9-column chips
	540	*/
	541	#define CFG_OR2_9COL (CFG_MIN_AM_MASK \|\
8bde7f77 WD	542	ORxS_BPD_4 \|\
	543	ORxS_ROWST_PBI0_A7 \|\
	544	ORxS_NUMR_13)
0f8c9768 WD	545
0f8c9768 WD	546	#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 \|\
8bde7f77 WD	547	PSDMR_BSMA_A13_A15 \|\
	548	PSDMR_SDA10_PBI0_A9 \|\
	549	PSDMR_RFRC_7_CLK \|\
	550	PSDMR_PRETOACT_2W \|\
	551	PSDMR_ACTTORW_1W \|\
	552	PSDMR_LDOTOPRE_1C \|\
	553	PSDMR_WRC_1C \|\
	554	PSDMR_CL_2)
0f8c9768 WD	555
	556	#define CFG_OR2_PRELIM CFG_OR2_9COL
	557	#define CFG_PSDMR CFG_PSDMR_9COL
	558
	559	#endif /* CFG_RAMBOOT */
	560
	561	#endif /* __CONFIG_H */