[people/ms/u-boot.git] / include / configs / PM856.h

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * MicroSys PM856 board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_MPC8560		1	/* MPC8560 specific */
#define CONFIG_CPM2		1	/* Has a CPM2 */
#define CONFIG_PM856		1	/* PM856 board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef  CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#if defined(CONFIG_SPD_EEPROM)
    /*
     * Determine DDR configuration from I2C interface.
     */
    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */

#else
    /*
     * Manually set up DDR parameters
     */
    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
    #define CFG_DDR_CS0_CONFIG	0x80000102
    #define CFG_DDR_TIMING_1	0x47444321
    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
#endif


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */

#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
#define CFG_BR0_PRELIM		0xfe001801	/* port size 32bit */

#define CFG_OR0_PRELIM		0xfe006f67	/* 32MB Flash */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/


#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */
#define CONFIG_CONS_INDEX       1  /* which serial channel for console */

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x58
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR		0x51

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

#endif  /* CONFIG_TSEC_ENET */

#define CONFIG_ETHPRIME		"TSEC0"

#define CONFIG_ETHER_ON_FCC	/* define if ether on FCC   */
#undef  CONFIG_ETHER_NONE	/* define if ether on something else */


/*
   * - Rx-CLK is CLK15
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
 */
#define CONFIG_ETHER_ON_FCC3
#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE	0
#define CFG_FCC_PSMR		(FCC_PSMR_FDE)

/*
 * Environment
 */
#ifndef CFG_RAMBOOT
  #define CFG_ENV_IS_IN_FLASH	1
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CFG_ENV_SIZE		0x2000
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now */
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CFG_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
#define CONFIG_LOOPW

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR   00:40:42:01:00:00
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:40:42:01:00:01
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:40:42:01:00:02
#endif


#define CONFIG_ROOTPATH		/opt/eldk/ppc_85xx
#define CONFIG_BOOTFILE		pm856/uImage

#define CONFIG_HOSTNAME		pm856
#define CONFIG_IPADDR    192.168.0.103
#define CONFIG_SERVERIP  192.168.0.64
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 5	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	9600

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=400000\0"						\
   "ramdiskfile=pm856/uRamdisk\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
b20d0032 WD	1	/*
	2	* Copyright 2004 Freescale Semiconductor.
	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* MicroSys PM856 board configuration file
	27	*
	28	* Please refer to doc/README.mpc85xx for more info.
	29	*
	30	* Make sure you change the MAC address and other network params first,
	31	* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* High Level Configuration Options */
	38	#define CONFIG_BOOKE 1 /* BOOKE */
	39	#define CONFIG_E500 1 /* BOOKE e500 family */
	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	41	#define CONFIG_MPC8560 1 /* MPC8560 specific */
452e8e72	42	#define CONFIG_CPM2 1 /* Has a CPM2 */
b20d0032 WD	43	#define CONFIG_PM856 1 /* PM856 board specific */
	44
	45	#define CONFIG_PCI
53677ef1	46	#define CONFIG_TSEC_ENET /* tsec ethernet support */
b20d0032 WD	47	#define CONFIG_ENV_OVERWRITE
	48	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
	49	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	50	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	51	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
452e8e72	52	#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
b20d0032	53
45f2166a	54	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
b20d0032 WD	55
	56	/*
	57	* sysclk for MPC85xx
	58	*
	59	* Two valid values are:
	60	* 33000000
	61	* 66000000
	62	*
	63	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
	64	* is likely the desired value here, so that is now the default.
	65	* The board, however, can run at 66MHz. In any event, this value
	66	* must match the settings of some switches. Details can be found
	67	* in the README.mpc85xxads.
	68	*/
	69
	70	#ifndef CONFIG_SYS_CLK_FREQ
	71	#define CONFIG_SYS_CLK_FREQ 66000000
	72	#endif
	73
	74
	75	/*
	76	* These can be toggled for performance analysis, otherwise use default.
	77	*/
	78	#define CONFIG_L2_CACHE /* toggle L2 cache */
	79	#define CONFIG_BTB /* toggle branch predition */
	80	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	81
	82	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	83
	84	#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
	85
	86	#undef CFG_DRAM_TEST /* memory test, takes time */
	87	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
	88	#define CFG_MEMTEST_END 0x00400000
	89
	90
	91	/*
	92	* Base addresses -- Note these are effective addresses where the
	93	* actual resources get mapped (not physical addresses)
	94	*/
53677ef1	95	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
b20d0032	96	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
f69766e4	97	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
b20d0032 WD	98	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	99
	100
	101	/*
	102	* DDR Setup
	103	*/
	104	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	105	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	106
	107	#if defined(CONFIG_SPD_EEPROM)
	108	/*
	109	* Determine DDR configuration from I2C interface.
	110	*/
	111	#define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
	112
	113	#else
	114	/*
	115	* Manually set up DDR parameters
	116	*/
	117	#define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
	118	#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
	119	#define CFG_DDR_CS0_CONFIG 0x80000102
	120	#define CFG_DDR_TIMING_1 0x47444321
	121	#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	122	#define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
	123	#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	124	#define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
	125	#endif
	126
	127
	128	/*
	129	* SDRAM on the Local Bus
	130	*/
	131	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
	132	#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
	133
	134	#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
	135	#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
	136
	137	#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */
	138	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	139	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
	140	#undef CFG_FLASH_CHECKSUM
	141	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	142	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	143
53677ef1	144	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
b20d0032 WD	145
	146	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	147	#define CFG_RAMBOOT
	148	#else
	149	#undef CFG_RAMBOOT
	150	#endif
	151
	152	#define CFG_FLASH_CFI_DRIVER
	153	#define CFG_FLASH_CFI
	154	#define CFG_FLASH_EMPTY_INFO
	155
	156	#undef CONFIG_CLOCKS_IN_MHZ
	157
	158
	159	/*
	160	* Local Bus Definitions
	161	*/
	162
	163	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	164	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	165	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	166	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
	167
	168
	169	#define CONFIG_L1_INIT_RAM
53677ef1	170	#define CFG_INIT_RAM_LOCK 1
b20d0032	171	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
53677ef1	172	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
b20d0032	173
53677ef1	174	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
b20d0032 WD	175	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	176	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	177
53677ef1 WD	178	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
53677ef1 WD	179	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
b20d0032 WD	180
	181	/* Serial Port */
	182	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	183	#undef CONFIG_CONS_NONE /* define if console on something else */
	184	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	185
	186	#define CFG_BAUDRATE_TABLE \
	187	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	188
	189	/* Use the HUSH parser */
	190	#define CFG_HUSH_PARSER
	191	#ifdef CFG_HUSH_PARSER
	192	#define CFG_PROMPT_HUSH_PS2 "> "
	193	#endif
	194
20476726 JL	195	/*
	196	* I2C
	197	*/
	198	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	199	#define CONFIG_HARD_I2C /* I2C with hardware support*/
b20d0032 WD	200	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	201	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	202	#define CFG_I2C_SLAVE 0x7F
	203	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	204	#define CFG_I2C_OFFSET 0x3000
b20d0032 WD	205
	206	/*
	207	* EEPROM configuration
	208	*/
	209	#define CFG_I2C_EEPROM_ADDR 0x58
	210	#define CFG_I2C_EEPROM_ADDR_LEN 1
	211	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	212	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	213
	214	/*
	215	* RTC configuration
	216	*/
	217	#define CONFIG_RTC_PCF8563
	218	#define CFG_I2C_RTC_ADDR 0x51
	219
	220	/* RapidIO MMU */
	221	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
	222	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
	223	#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
	224
	225	/*
	226	* General PCI
	227	* Addresses are mapped 1-1.
	228	*/
	229	#define CFG_PCI1_MEM_BASE 0x80000000
	230	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	231	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	232	#define CFG_PCI1_IO_BASE 0xe2000000
	233	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	234	#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
	235
	236	#if defined(CONFIG_PCI)
	237
	238	#define CONFIG_NET_MULTI
53677ef1	239	#define CONFIG_PCI_PNP /* do pci plug-and-play */
b20d0032 WD	240
	241	#undef CONFIG_EEPRO100
	242	#undef CONFIG_TULIP
	243
	244	#if !defined(CONFIG_PCI_PNP)
	245	#define PCI_ENET0_IOADDR 0xe0000000
	246	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	247	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
b20d0032 WD	248	#endif
	249
	250	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	251	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	252
	253	#endif /* CONFIG_PCI */
	254
	255
	256	#if defined(CONFIG_TSEC_ENET)
	257
	258	#ifndef CONFIG_NET_MULTI
53677ef1	259	#define CONFIG_NET_MULTI 1
b20d0032 WD	260	#endif
	261
	262	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	263	#define CONFIG_TSEC1 1
	264	#define CONFIG_TSEC1_NAME "TSEC0"
	265	#define CONFIG_TSEC2 1
	266	#define CONFIG_TSEC2_NAME "TSEC1"
b20d0032 WD	267	#define TSEC1_PHY_ADDR 0
	268	#define TSEC2_PHY_ADDR 1
	269	#define TSEC1_PHYIDX 0
	270	#define TSEC2_PHYIDX 0
3a79013e AF	271	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	272	#define TSEC2_FLAGS TSEC_GIGABIT
b20d0032 WD	273
	274	#endif /* CONFIG_TSEC_ENET */
	275
452e8e72	276	#define CONFIG_ETHPRIME "TSEC0"
b20d0032 WD	277
	278	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	279	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	280
	281
	282	/*
	283	* - Rx-CLK is CLK15
	284	* - Tx-CLK is CLK14
	285	* - Select bus for bd/buffers
	286	* - Full duplex
	287	*/
	288	#define CONFIG_ETHER_ON_FCC3
	289	#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 \| CMXFCR_RF3CS_MSK \| CMXFCR_TF3CS_MSK)
	290	#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 \| CMXFCR_TF3CS_CLK14)
	291	#define CFG_CPMFCR_RAMTYPE 0
	292	#define CFG_FCC_PSMR (FCC_PSMR_FDE)
	293
	294	/*
	295	* Environment
	296	*/
	297	#ifndef CFG_RAMBOOT
	298	#define CFG_ENV_IS_IN_FLASH 1
	299	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000)
	300	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
	301	#define CFG_ENV_SIZE 0x2000
	302	#else
	303	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	304	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	305	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	306	#define CFG_ENV_SIZE 0x2000
	307	#endif
	308
	309	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	310	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	311
2835e518	312
a1aa0bb5 JL	313	/*
	314	* BOOTP options
	315	*/
	316	#define CONFIG_BOOTP_BOOTFILESIZE
	317	#define CONFIG_BOOTP_BOOTPATH
	318	#define CONFIG_BOOTP_GATEWAY
	319	#define CONFIG_BOOTP_HOSTNAME
	320
	321
2835e518 JL	322	/*
	323	* Command line configuration.
	324	*/
	325	#include <config_cmd_default.h>
	326
	327	#define CONFIG_CMD_PING
	328	#define CONFIG_CMD_I2C
	329	#define CONFIG_CMD_DATE
	330	#define CONFIG_CMD_EEPROM
	331
	332	#if defined(CONFIG_PCI)
	333	#define CONFIG_CMD_PCI
	334	#endif
	335
b20d0032	336	#if defined(CFG_RAMBOOT)
2835e518 JL	337	#undef CONFIG_CMD_ENV
2835e518 JL	338	#undef CONFIG_CMD_LOADS
b20d0032 WD	339	#endif
b20d0032 WD	340
b20d0032 WD	341
	342	#undef CONFIG_WATCHDOG /* watchdog disabled */
	343
	344	/*
	345	* Miscellaneous configurable options
	346	*/
	347	#define CFG_LONGHELP /* undef to save memory */
	348	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	349	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	350
2835e518	351	#if defined(CONFIG_CMD_KGDB)
b20d0032 WD	352	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	353	#else
	354	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	355	#endif
	356
	357	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	358	#define CFG_MAXARGS 16 /* max number of command args */
	359	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	360	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	361	#define CONFIG_LOOPW
	362
	363	/*
	364	* For booting Linux, the board info and command line data
	365	* have to be in the first 8 MB of memory, since this is
	366	* the maximum mapped by the Linux kernel during initialization.
	367	*/
	368	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
	369
b20d0032 WD	370	/*
	371	* Internal Definitions
	372	*
	373	* Boot Flags
	374	*/
	375	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	376	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	377
2835e518	378	#if defined(CONFIG_CMD_KGDB)
b20d0032 WD	379	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	380	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	381	#endif
	382
	383
	384	/*
	385	* Environment Configuration
	386	*/
	387
	388	/* The mac addresses for all ethernet interface */
	389	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	390	#define CONFIG_HAS_ETH0
b20d0032 WD	391	#define CONFIG_ETHADDR 00:40:42:01:00:00
	392	#define CONFIG_HAS_ETH1
	393	#define CONFIG_ETH1ADDR 00:40:42:01:00:01
	394	#define CONFIG_HAS_ETH2
	395	#define CONFIG_ETH2ADDR 00:40:42:01:00:02
	396	#endif
	397
	398
	399	#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
	400	#define CONFIG_BOOTFILE pm856/uImage
	401
	402	#define CONFIG_HOSTNAME pm856
	403	#define CONFIG_IPADDR 192.168.0.103
	404	#define CONFIG_SERVERIP 192.168.0.64
	405	#define CONFIG_GATEWAYIP 192.168.0.1
	406	#define CONFIG_NETMASK 255.255.255.0
	407
	408	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	409
	410	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
	411	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	412
	413	#define CONFIG_BAUDRATE 9600
	414
	415	#define CONFIG_EXTRA_ENV_SETTINGS \
	416	"netdev=eth0\0" \
	417	"consoledev=ttyS0\0" \
	418	"ramdiskaddr=400000\0" \
	419	"ramdiskfile=pm856/uRamdisk\0"
	420
	421	#define CONFIG_NFSBOOTCOMMAND \
	422	"setenv bootargs root=/dev/nfs rw " \
	423	"nfsroot=$serverip:$rootpath " \
	424	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	425	"console=$consoledev,$baudrate $othbootargs;" \
	426	"tftp $loadaddr $bootfile;" \
	427	"bootm $loadaddr"
	428
	429	#define CONFIG_RAMBOOTCOMMAND \
	430	"setenv bootargs root=/dev/ram rw " \
	431	"console=$consoledev,$baudrate $othbootargs;" \
	432	"tftp $ramdiskaddr $ramdiskfile;" \
	433	"tftp $loadaddr $bootfile;" \
	434	"bootm $loadaddr $ramdiskaddr"
	435
	436	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	437
	438	#endif /* __CONFIG_H */