[people/ms/u-boot.git] / include / configs / PMC405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
#define CONFIG_PMC405		1	/* ...on a PMC405 board 	*/

#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */

#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_RAMBOOTCOMMAND							\
	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
	"bootm ffc00000 ffca0000"
#define CONFIG_NFSBOOTCOMMAND							\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
	"bootm ffc00000"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define	CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_PCI	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_ELF	| \
				CFG_CMD_DATE	| \
				CFG_CMD_JFFS2	| \
				CFG_CMD_MII	| \
				CFG_CMD_I2C	| \
				CFG_CMD_EEPROM  )

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000300 /* RTC Base Address         */

#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */

#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
#define CFG_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE      \
        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
         57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */

#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
                                        /* resource configuration       */

#undef CONFIG_PCI_SCAN_SHOW             /* print pci devices @ startup  */

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_MONITOR_BASE	0xFFFC0000
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_BASE		0xFE000000
#define CFG_FLASH_INCREMENT	0x01000000

#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */

#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
                                   /* total size of a CAT24WC16 is 2048 bytes */

#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last	4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384	/* For IBM 405 CPUs, older 405 ppc's    */
                                        /* have only 8kB, 16kB is save here     */
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */
#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
#define CAN_BA          0xF0000000          /* CAN Base Address                 */
#define RTC_BA          0xF0000500          /* RTC Base Address                 */
#define CF_BA           0xF0100000          /* CompactFlash Base Address        */

/* Memory Bank 0 (Flash Bank 0) initialization                                  */
#define CFG_EBC_PB0AP   0x92015480
#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/

/* Memory Bank 1 (Flash Bank 1) initialization                                  */
#define CFG_EBC_PB1AP   0x92015480
#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/

/* Memory Bank 2 (CAN0, 1, RTC) initialization                                  */
#define CFG_EBC_PB2AP   0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0      */
#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM      1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
071d897c SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	#define CONFIG_PMC405 1 /* ...on a PMC405 board */
	39
	40	#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	42
	43	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	44
	45	#define CONFIG_BAUDRATE 9600
	46	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47
	48	#undef CONFIG_BOOTARGS
	49	#define CONFIG_RAMBOOTCOMMAND \
	50	"setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
	51	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	52	"bootm ffc00000 ffca0000"
	53	#define CONFIG_NFSBOOTCOMMAND \
	54	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	55	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	56	"bootm ffc00000"
	57	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	58
	59	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	60	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	61
	62	#define CONFIG_MII 1 /* MII PHY management */
	63	#define CONFIG_PHY_ADDR 0 /* PHY address */
	64
65	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
66	CFG_CMD_PCI \| \
67	CFG_CMD_IRQ \| \
68	CFG_CMD_ELF \| \
69	CFG_CMD_DATE \| \
70	CFG_CMD_JFFS2 \| \
71	CFG_CMD_MII \| \
72	CFG_CMD_I2C \| \
73	CFG_CMD_EEPROM )
74
75	#define CONFIG_MAC_PARTITION
76	#define CONFIG_DOS_PARTITION
77
78	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
79	#include <cmd_confdefs.h>
80
81	#undef CONFIG_WATCHDOG /* watchdog disabled */
82
83	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
84	#define CFG_RTC_REG_BASE_ADDR 0xF0000300 /* RTC Base Address */
85
86	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
87
88	/*
89	* Miscellaneous configurable options
90	*/
91	#define CFG_LONGHELP /* undef to save memory */
92	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
93
94	#undef CFG_HUSH_PARSER /* use "hush" command parser */
95	#ifdef CFG_HUSH_PARSER
96	#define CFG_PROMPT_HUSH_PS2 "> "
97	#endif
98
99	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
100	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
101	#else
102	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
103	#endif
104	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105	#define CFG_MAXARGS 16 /* max number of command args */
106	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107
108	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
109
110	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
111
112	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
113	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
114
115	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
116	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
117	#define CFG_BASE_BAUD 691200
118
119	/* The following table includes the supported baudrates */
120	#define CFG_BAUDRATE_TABLE \
121	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
122	57600, 115200, 230400, 460800, 921600 }
123
124	#define CFG_LOAD_ADDR 0x100000 /* default load address */
125	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
126
127	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
128
129	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
130
53cf9435 SR	131	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	132
	133	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
	134
071d897c SR	135	/*-----------------------------------------------------------------------
	136	* PCI stuff
	137	*-----------------------------------------------------------------------
	138	*/
	139	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	140	#define PCI_HOST_FORCE 1 /* configure as pci host */
	141	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	142
	143	#define CONFIG_PCI /* include pci support */
	144	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	145	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	146	/* resource configuration */
	147
	148	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	149
	150	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	151	#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
	152	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	153	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	154	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	155	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	156	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	157	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	158	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	159
	160	/*-----------------------------------------------------------------------
	161	* Start addresses for the final memory configuration
	162	* (Set up by the startup code)
	163	* Please note that CFG_SDRAM_BASE _must_ start at 0
	164	*/
	165	#define CFG_SDRAM_BASE 0x00000000
	166	#define CFG_MONITOR_BASE 0xFFFC0000
	167	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	168	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	169
	170	/*
	171	* For booting Linux, the board info and command line data
	172	* have to be in the first 8 MB of memory, since this is
	173	* the maximum mapped by the Linux kernel during initialization.
	174	*/
	175	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	176
	177	/*-----------------------------------------------------------------------
	178	* FLASH organization
	179	*/
	180	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	181	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	182	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	183	#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
	184	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	185	#define CFG_FLASH_BASE 0xFE000000
	186	#define CFG_FLASH_INCREMENT 0x01000000
	187
	188	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	189
	190	#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
	191	#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
	192
	193	/*-----------------------------------------------------------------------
	194	* Environment Variable setup
	195	*/
	196	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	197	#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	198	#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
199	/* total size of a CAT24WC16 is 2048 bytes */
200
201	#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
202	#define CFG_NVRAM_SIZE 242 /* NVRAM size */
203
204	/*-----------------------------------------------------------------------
205	* I2C EEPROM (CAT24WC16) for environment
206	*/
207	#define CONFIG_HARD_I2C /* I2c with hardware support */
208	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
209	#define CFG_I2C_SLAVE 0x7F
210
211	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
212	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
213	/* mask of address bits that overflow into the "EEPROM chip address" */
214	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
215	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
216	/* 16 byte page write mode using*/
217	/* last 4 bits of the address */
218	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
219	#define CFG_EEPROM_PAGE_WRITE_ENABLE
220
221	/*-----------------------------------------------------------------------
222	* Cache Configuration
223	*/
224	#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
225	/* have only 8kB, 16kB is save here */
226	#define CFG_CACHELINE_SIZE 32 /* ... */
227	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
228	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
229	#endif
230
231	/*-----------------------------------------------------------------------
232	* External Bus Controller (EBC) Setup
233	*/
234	#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
235	#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
236	#define CAN_BA 0xF0000000 /* CAN Base Address */
237	#define RTC_BA 0xF0000500 /* RTC Base Address */
238	#define CF_BA 0xF0100000 /* CompactFlash Base Address */
239
240	/* Memory Bank 0 (Flash Bank 0) initialization */
241	#define CFG_EBC_PB0AP 0x92015480
242	#define CFG_EBC_PB0CR FLASH0_BA \| 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
243
244	/* Memory Bank 1 (Flash Bank 1) initialization */
245	#define CFG_EBC_PB1AP 0x92015480
246	#define CFG_EBC_PB1CR FLASH1_BA \| 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
247
248	/* Memory Bank 2 (CAN0, 1, RTC) initialization */
249	#define CFG_EBC_PB2AP 0x03000040 /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0 */
250	#define CFG_EBC_PB2CR CAN_BA \| 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
251
252	/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
253	#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
254	#define CFG_EBC_PB3CR CF_BA \| 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
255
256	/*-----------------------------------------------------------------------
257	* Definitions for initial stack pointer and data area (in data cache)
258	*/
259
260	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
261	#define CFG_TEMP_STACK_OCM 1
262
263	/* On Chip Memory location */
264	#define CFG_OCM_DATA_ADDR 0xF8000000
265	#define CFG_OCM_DATA_SIZE 0x1000
266
267	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
268	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
269	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
270	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
271	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
272
273	/*
274	* Internal Definitions
275	*
276	* Boot Flags
277	*/
278	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
279	#define BOOTFLAG_WARM 0x02 /* Software reboot */
280
281	#endif /* __CONFIG_H */