[people/ms/u-boot.git] / include / configs / PMC405.h

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PMC405		1	/* ...on a PMC405 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

/* Only interrupt boot if space is pressed. */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT	\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "

#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT			/* enable preboot variable	*/

#define CFG_BOOTM_LEN		0x1000000 /* support booting of huge images */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1	/* allow baudrate change	*/

#undef  CONFIG_HAS_ETH1

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP	1	/* disable sleep mode in LXT971	*/
#define CONFIG_RESET_PHY_R	1	/* use reset_phy()		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_UNIVERSE
#define CONFIG_CMD_EEPROM

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible */
#define CONFIG_SYS_RTC_REG_BASE_ADDR	0xF0000500 /* RTC Base Address */

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */

#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */

#define CONFIG_AUTO_COMPLETE		1       /* add autocompletion support */

#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock */
#define CONFIG_SYS_BASE_BAUD	806400

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_LOOPW		1	/* enable loopw command */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CONFIG_SYS_RX_ETH_BUFFER	16

/*
 * PCI stuff
 */
#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
#define PCI_HOST_FORCE		1	/* configure as pci host	*/
#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1	/* don't skip host bridge config */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()

#define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */

#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram	*/
#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA  0xef000000	/* point to internal regs */
#define CONFIG_SYS_PCI_PTM2MS  0xff000001	/* 16MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address */

#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* 128 kB for malloc() */

#define CONFIG_PRAM			0 /* use pram variable to overwrite */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_INCREMENT	0x01000000

#define CONFIG_SYS_FLASH_CFI		1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER		1 /* Use the common driver */
#define CONFIG_SYS_FLASH_PROTECTION	1 /* don't use hardware protection */
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
#define CONFIG_SYS_MAX_FLASH_BANKS	2 /* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
			CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
#define CONFIG_SYS_MAX_FLASH_SECT	128 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on fli */

/*
 * Environment Variable setup
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */

/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_OFFSET	0x000
#define CONFIG_ENV_SIZE		0x800 /* 2048 bytes may be used for env vars */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */

/*
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24W16 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24W16 has */
					/* 16 byte page write mode using*/
					/* last	4 bits of the address */

#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */

/*
 * External Bus Controller (EBC) Setup
 */
#define FLASH0_BA	0xFF000000	/* FLASH 0 Base Address	*/
#define FLASH1_BA	0xFE000000	/* FLASH 1 Base Address	*/
#define CAN_BA		0xF0000000	/* CAN Base Addres	*/
#define RTC_BA		0xF0000500	/* RTC Base Address	*/
#define NVRAM_BA	0xF0200000	/* NVRAM Base Address	*/

/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP	0x92015480
/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0CR	(FLASH0_BA | 0x9A000)

/* Memory Bank 1 (Flash Bank 1) initialization */
#define CONFIG_SYS_EBC_PB1AP	0x92015480
/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_EBC_PB1CR	(FLASH1_BA | 0x9A000)

/* Memory Bank 2 (CAN0, 1, RTC) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
#define CONFIG_SYS_EBC_PB2AP	0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB2CR	(CAN_BA | 0x18000)

/* Memory Bank 3 -> unused */

/* Memory Bank 4 (NVRAM) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB4AP	0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB4CR	(NVRAM_BA | 0x18000)

/*
 * FPGA stuff
 */
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */
#define CONFIG_SYS_FPGA_DATA		0x01000000 /* JTAG TDO pin (output) */
#define CONFIG_SYS_FPGA_INIT		0x00010000 /* unused (ppc input) */
#define CONFIG_SYS_FPGA_DONE		0x00008000 /* JTAG TDI pin (input) */

/* pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000

/*
 * GPIOs
 */
#define CONFIG_SYS_VPEN			(0x80000000 >>  3) /* GPIO3 */
#define CONFIG_SYS_NONMONARCH		(0x80000000 >> 14) /* GPIO14 */
#define CONFIG_SYS_XEREADY		(0x80000000 >> 15) /* GPIO15 */
#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 19) /* GPIO19 */
#define CONFIG_SYS_SELF_RST		(0x80000000 >> 21) /* GPIO21 */
#define CONFIG_SYS_REV1_2		(0x80000000 >> 23) /* GPIO23 */

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */

/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

/* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR

/* End of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

#endif /* __CONFIG_H */
Commit	Line	Data
071d897c	1	/*
a20b27a3	2	* (C) Copyright 2001-2004
071d897c SR	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
c553b5f4	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
071d897c SR	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
071d897c SR	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
071d897c SR	29	*/
	30
	31	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	32	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	33	#define CONFIG_PMC405 1 /* ...on a PMC405 board */
071d897c	34
2ae18241 WD	35	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
2ae18241 WD	36
c837dcb1 WD	37	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	38	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
071d897c	39
a20b27a3	40	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
071d897c SR	41
	42	#define CONFIG_BAUDRATE 9600
	43	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	44
2f6eb917 MF	45	/* Only interrupt boot if space is pressed. */
	46	#define CONFIG_AUTOBOOT_KEYED 1
	47	#define CONFIG_AUTOBOOT_PROMPT \
	48	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
	49	#undef CONFIG_AUTOBOOT_DELAY_STR
	50	#define CONFIG_AUTOBOOT_STOP_STR " "
	51
c553b5f4 MF	52	#undef CONFIG_BOOTARGS
c553b5f4 MF	53	#undef CONFIG_BOOTCOMMAND
a20b27a3	54
c553b5f4	55	#define CONFIG_PREBOOT /* enable preboot variable */
071d897c	56
2f6eb917 MF	57	#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
2f6eb917 MF	58
071d897c	59	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
c553b5f4	60	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
071d897c	61
2076d0a1 SR	62	#undef CONFIG_HAS_ETH1
2076d0a1 SR	63
96e21f86	64	#define CONFIG_PPC4xx_EMAC
071d897c	65	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	66	#define CONFIG_PHY_ADDR 0 /* PHY address */
c553b5f4 MF	67	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
c553b5f4 MF	68	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
acf02697	69
a1aa0bb5 JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
acf02697 JL	78	/*
	79	* Command line configuration.
	80	*/
	81	#include <config_cmd_default.h>
	82
	83	#define CONFIG_CMD_BSP
	84	#define CONFIG_CMD_PCI
	85	#define CONFIG_CMD_IRQ
	86	#define CONFIG_CMD_ELF
	87	#define CONFIG_CMD_DATE
	88	#define CONFIG_CMD_JFFS2
	89	#define CONFIG_CMD_MII
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_CMD_PING
	92	#define CONFIG_CMD_UNIVERSE
	93	#define CONFIG_CMD_EEPROM
	94
071d897c SR	95	#define CONFIG_MAC_PARTITION
	96	#define CONFIG_DOS_PARTITION
	97
c553b5f4	98	#undef CONFIG_WATCHDOG /* watchdog disabled */
071d897c	99
c553b5f4 MF	100	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
c553b5f4 MF	101	#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
071d897c	102
c837dcb1	103	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
071d897c SR	104
	105	/*
	106	* Miscellaneous configurable options
	107	*/
c553b5f4 MF	108	#define CONFIG_SYS_LONGHELP /* undef to save memory */
c553b5f4 MF	109	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
071d897c	110
c553b5f4	111	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
071d897c	112
acf02697	113	#if defined(CONFIG_CMD_KGDB)
c553b5f4	114	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
071d897c	115	#else
2f6eb917	116	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
071d897c	117	#endif
c553b5f4 MF	118	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	119	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	120	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
071d897c	121
c553b5f4	122	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
071d897c	123
c553b5f4	124	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
071d897c	125
c553b5f4	126	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
a20b27a3	127
c553b5f4 MF	128	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
c553b5f4 MF	129	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
071d897c	130
550650dd SR	131	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	132	#define CONFIG_SYS_NS16550
	133	#define CONFIG_SYS_NS16550_SERIAL
	134	#define CONFIG_SYS_NS16550_REG_SIZE 1
	135	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	136
c553b5f4	137	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
2f6eb917	138	#define CONFIG_SYS_BASE_BAUD 806400
071d897c SR	139
071d897c SR	140	/* The following table includes the supported baudrates */
6d0f6bcf	141	#define CONFIG_SYS_BAUDRATE_TABLE \
2f6eb917	142	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
071d897c	143
6d0f6bcf	144	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
c553b5f4	145	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
071d897c	146
c553b5f4	147	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
071d897c	148
2f6eb917	149	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
c553b5f4	150	#define CONFIG_LOOPW 1 /* enable loopw command */
a20b27a3	151
071d897c SR	152	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
071d897c SR	153
c837dcb1	154	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
53cf9435	155
c553b5f4	156	#define CONFIG_SYS_RX_ETH_BUFFER 16
53cf9435	157
c553b5f4	158	/*
071d897c	159	* PCI stuff
071d897c	160	*/
c553b5f4 MF	161	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	162	#define PCI_HOST_FORCE 1 /* configure as pci host */
	163	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
a20b27a3	164
c553b5f4	165	#define CONFIG_PCI /* include pci support */
842033e6	166	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c553b5f4 MF	167	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	168	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	169	/* resource configuration */
a20b27a3	170
c553b5f4	171	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
a20b27a3	172
c553b5f4	173	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
a20b27a3	174
c553b5f4 MF	175	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	176	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
	177	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
6d0f6bcf	178	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
2076d0a1	179
c553b5f4 MF	180	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
	181
	182	#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
	183	#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable */
	184	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	185	#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
	186	#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
	187	#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
	188
82379b55 MF	189	#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
82379b55 MF	190
c553b5f4	191	/*
071d897c SR	192	* Start addresses for the final memory configuration
071d897c SR	193	* (Set up by the startup code)
6d0f6bcf	194	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
071d897c	195	*/
6d0f6bcf	196	#define CONFIG_SYS_SDRAM_BASE 0x00000000
14d0a02a WD	197	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
14d0a02a WD	198	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
c553b5f4	199	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
071d897c	200
2f6eb917 MF	201	#define CONFIG_PRAM 0 /* use pram variable to overwrite */
2f6eb917 MF	202
071d897c SR	203	/*
	204	* For booting Linux, the board info and command line data
	205	* have to be in the first 8 MB of memory, since this is
	206	* the maximum mapped by the Linux kernel during initialization.
	207	*/
c553b5f4	208	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
071d897c	209
c553b5f4	210	/*
071d897c SR	211	* FLASH organization
071d897c SR	212	*/
6d0f6bcf JCPV	213	#define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	214	#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
071d897c	215
c553b5f4 MF	216	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
	217	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	218	#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
2f6eb917	219	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
c553b5f4 MF	220	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
	221	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
	222	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
	223	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
	224	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	225	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
071d897c	226
c553b5f4	227	/*
071d897c SR	228	* Environment Variable setup
071d897c SR	229	*/
bb1f8b4f	230	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
071d897c	231
c553b5f4 MF	232	/* environment starts at the beginning of the EEPROM */
	233	#define CONFIG_ENV_OFFSET 0x000
	234	#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
	235
	236	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
	237	#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
071d897c	238
c553b5f4	239	/*
071d897c SR	240	* I2C EEPROM (CAT24WC16) for environment
071d897c SR	241	*/
880540de DE	242	#define CONFIG_SYS_I2C
	243	#define CONFIG_SYS_I2C_PPC4XX
	244	#define CONFIG_SYS_I2C_PPC4XX_CH0
	245	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	246	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
071d897c	247
2f6eb917	248	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
c553b5f4 MF	249	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c553b5f4 MF	250	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf	251	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
2f6eb917 MF	252	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
	253	/* 16 byte page write mode using*/
	254	/* last 4 bits of the address */
	255
c553b5f4	256	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
071d897c	257
c553b5f4	258	/*
071d897c SR	259	* External Bus Controller (EBC) Setup
071d897c SR	260	*/
c553b5f4 MF	261	#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
	262	#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
	263	#define CAN_BA 0xF0000000 /* CAN Base Addres */
	264	#define RTC_BA 0xF0000500 /* RTC Base Address */
	265	#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
071d897c	266
c553b5f4	267	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf	268	#define CONFIG_SYS_EBC_PB0AP 0x92015480
c553b5f4 MF	269	/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
c553b5f4 MF	270	#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA \| 0x9A000)
071d897c	271
c553b5f4	272	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf	273	#define CONFIG_SYS_EBC_PB1AP 0x92015480
c553b5f4 MF	274	/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
c553b5f4 MF	275	#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA \| 0x9A000)
071d897c	276
c553b5f4 MF	277	/* Memory Bank 2 (CAN0, 1, RTC) initialization */
	278	/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
	279	#define CONFIG_SYS_EBC_PB2AP 0x03000440
	280	/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	281	#define CONFIG_SYS_EBC_PB2CR (CAN_BA \| 0x18000)
071d897c	282
2076d0a1 SR	283	/* Memory Bank 3 -> unused */
2076d0a1 SR	284
c553b5f4 MF	285	/* Memory Bank 4 (NVRAM) initialization */
	286	/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
	287	#define CONFIG_SYS_EBC_PB4AP 0x03000440
	288	/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	289	#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA \| 0x18000)
071d897c	290
c553b5f4	291	/*
2853d29b SR	292	* FPGA stuff
2853d29b SR	293	*/
2853d29b	294	/* FPGA program pin configuration */
c553b5f4 MF	295	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
	296	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
	297	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
	298	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
	299	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
2853d29b	300
c553b5f4 MF	301	/* pass Ethernet MAC to VxWorks */
c553b5f4 MF	302	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
a20b27a3	303
c553b5f4	304	/*
2076d0a1 SR	305	* GPIOs
2076d0a1 SR	306	*/
2f6eb917	307	#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
c553b5f4 MF	308	#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
	309	#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
	310	#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
	311	#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
	312	#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
2076d0a1	313
c553b5f4	314	/*
071d897c SR	315	* Definitions for initial stack pointer and data area (in data cache)
	316	*/
	317
c553b5f4	318	/* use on chip memory (OCM) for temperary stack until sdram is tested */
6d0f6bcf	319	#define CONFIG_SYS_TEMP_STACK_OCM 1
071d897c SR	320
071d897c SR	321	/* On Chip Memory location */
6d0f6bcf JCPV	322	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	323	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	324
c553b5f4 MF	325	/* inside of SDRAM */
	326	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
	327
	328	/* End of used area in RAM */
553f0982	329	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
c553b5f4	330
553f0982	331	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
25ddd1fb	332	GENERATED_GBL_DATA_SIZE)
6d0f6bcf	333	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
071d897c	334
2f6eb917 MF	335	#define CONFIG_OF_LIBFDT
	336	#define CONFIG_OF_BOARD_SETUP
	337
c553b5f4	338	#endif /* __CONFIG_H */