[people/ms/u-boot.git] / include / configs / PN62.h

/*
 * (C) Copyright 2002
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8240		1
#define CONFIG_PN62		1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_CONS_INDEX	1


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_BSP

#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_SOURCE


#define CONFIG_BAUDRATE		19200	/* console baudrate		*/

#define CONFIG_BOOTDELAY	1	/* autoboot after n seconds	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_SERVERIP		10.0.0.201
#define CONFIG_IPADDR		10.0.0.200
#define CONFIG_ROOTPATH		"/opt/eldk/ppc_82xx"
#define CONFIG_NETMASK		255.255.255.0
#undef CONFIG_BOOTARGS
#if 0
/* Boot Linux with NFS root filesystem */
#define CONFIG_BOOTCOMMAND \
			"setenv verify y;" \
			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
			"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
			"loadp 100000; bootm"
			/* "tftpboot 100000 uImage; bootm" */
#else
/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
#define CONFIG_BOOTCOMMAND \
			"setenv verify n;" \
			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
			"root=/dev/ram rw " \
			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
			"loadp 200000; bootm"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_PRAM		1024		/* reserve 1 MB protected RAM	*/

#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/

#define CONFIG_HAS_ETH1		1		/* add support for eth1addr	*/

#define CONFIG_SHOW_BOOT_PROGRESS 1		/* Show boot progress on LEDs   */

/*
 * PCI stuff
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP				/* we need Plug 'n Play		*/
#if 0
#define CONFIG_PCI_SCAN_SHOW			/* show PCI auto-scan at boot	*/
#endif

/*
 * Networking stuff
 */

#define CONFIG_PCNET				/* there are 2 AMD PCnet 79C973	*/
#define CONFIG_PCNET_79C973

#define _IO_BASE		0xfe000000	/* points to PCI I/O space	*/


/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000

#define CONFIG_SYS_RESET_ADDRESS	0xfff00100

#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)


#define CONFIG_SYS_NO_FLASH		1		/* There is no FLASH memory	*/

#define CONFIG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/

/*
 * Serial port configuration
 */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		1843200

#define CONFIG_SYS_NS16550_COM1	0xff800008
#define CONFIG_SYS_NS16550_COM2	0xff800000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3

#define CONFIG_SYS_EUMB_ADDR		0xFCE00000

/* MCCR1 */
#define CONFIG_SYS_ROMNAL		3	/* rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL		7	/* rom/flash access time		*/

/* MCCR2 */
#define CONFIG_SYS_ASRISE		6	/* ASRISE in clocks			*/
#define CONFIG_SYS_ASFALL		12	/* ASFALL in clocks			*/
#define CONFIG_SYS_REFINT		5600	/* REFINT in clocks			*/

/* MCCR3 */
#define CONFIG_SYS_BSTOPRE		0x3cf	/* Burst To Precharge			*/
#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		3	/* data latency from read command	*/

/* MCCR4 */
#define CONFIG_SYS_PRETOACT		1	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1

/* Memory bank settings:
 *
 * only bits 20-29 are actually used from these vales to set the
 * start/qend address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x00000000
#define CONFIG_SYS_BANK1_END		0x00000000
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x00000000
#define CONFIG_SYS_BANK2_END		0x00000000
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x00000000
#define CONFIG_SYS_BANK3_END		0x00000000
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0

/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 * are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI memory space */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/* ------------------------------------------------------------------------- */
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC824X 1
	23	#define CONFIG_MPC8240 1
	24	#define CONFIG_PN62 1
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	27
c609719b WD	28	#define CONFIG_CONS_INDEX 1
	29
	30
a1aa0bb5 JL	31	/*
	32	* BOOTP options
	33	*/
	34	#define CONFIG_BOOTP_BOOTFILESIZE
	35	#define CONFIG_BOOTP_BOOTPATH
	36	#define CONFIG_BOOTP_GATEWAY
	37	#define CONFIG_BOOTP_HOSTNAME
	38
	39
acf02697 JL	40	/*
	41	* Command line configuration.
	42	*/
	43	#include <config_cmd_default.h>
	44
	45	#define CONFIG_CMD_PCI
	46	#define CONFIG_CMD_BSP
	47
acf02697 JL	48	#undef CONFIG_CMD_FLASH
acf02697 JL	49	#undef CONFIG_CMD_IMLS
74de7aef WD	50	#undef CONFIG_CMD_LOADS
	51	#undef CONFIG_CMD_SAVEENV
	52	#undef CONFIG_CMD_SOURCE
c609719b	53
c609719b WD	54
	55	#define CONFIG_BAUDRATE 19200 /* console baudrate */
	56
	57	#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
	58
	59	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	60
	61	#define CONFIG_SERVERIP 10.0.0.201
53677ef1	62	#define CONFIG_IPADDR 10.0.0.200
8b3637c6	63	#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx"
c609719b WD	64	#define CONFIG_NETMASK 255.255.255.0
	65	#undef CONFIG_BOOTARGS
	66	#if 0
	67	/* Boot Linux with NFS root filesystem */
	68	#define CONFIG_BOOTCOMMAND \
	69	"setenv verify y;" \
53677ef1	70	"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
fe126d8b WD	71	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	72	"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
c609719b	73	"loadp 100000; bootm"
3bac3513	74	/* "tftpboot 100000 uImage; bootm" */
c609719b WD	75	#else
	76	/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
	77	#define CONFIG_BOOTCOMMAND \
	78	"setenv verify n;" \
53677ef1	79	"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
c609719b	80	"root=/dev/ram rw " \
fe126d8b	81	"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
c609719b WD	82	"loadp 200000; bootm"
	83	#endif
	84
c609719b WD	85	/*
	86	* Miscellaneous configurable options
	87	*/
6d0f6bcf JCPV	88	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
	89	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	90	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	91	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	92	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	93	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	94	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
	95	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	96
	97	#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
	98
	99	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
	100
e2ffd59b WD	101	#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
e2ffd59b WD	102
c609719b WD	103	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	104
	105	/*
	106	* PCI stuff
	107	*/
	108	#define CONFIG_PCI /* include pci support */
842033e6	109	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c609719b WD	110	#define CONFIG_PCI_PNP /* we need Plug 'n Play */
	111	#if 0
	112	#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
	113	#endif
	114
	115	/*
	116	* Networking stuff
	117	*/
c609719b WD	118
	119	#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
	120	#define CONFIG_PCNET_79C973
	121
	122	#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
	123
	124
	125	/*
	126	* Start addresses for the final memory configuration
	127	* (Set up by the startup code)
6d0f6bcf	128	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	131	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
c609719b	132
6d0f6bcf	133	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
c609719b	134
6d0f6bcf JCPV	135	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	136	#define CONFIG_SYS_MONITOR_LEN 0x00030000
14d0a02a	137	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	138
c609719b	139
6d0f6bcf	140	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	141	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	142	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
c609719b WD	143
c609719b WD	144
6d0f6bcf	145	#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
c609719b	146
93f6d725	147	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
0e8d1586 JCPV	148	#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
0e8d1586 JCPV	149	#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
c609719b	150
6d0f6bcf	151	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
c609719b	152
6d0f6bcf JCPV	153	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	154	#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
c609719b WD	155
	156	/*
	157	* Serial port configuration
	158	*/
c609719b	159
6d0f6bcf JCPV	160	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	161	#define CONFIG_SYS_NS16550_SERIAL
c609719b	162
6d0f6bcf	163	#define CONFIG_SYS_NS16550_REG_SIZE 1
c609719b	164
6d0f6bcf	165	#define CONFIG_SYS_NS16550_CLK 1843200
c609719b	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_NS16550_COM1 0xff800008
6d0f6bcf JCPV	168	#define CONFIG_SYS_NS16550_COM2 0xff800000
c609719b WD	169
	170	/*
	171	* Low Level Configuration Settings
	172	* (address mappings, register initial values, etc.)
	173	* You should know what you are doing if you make changes here.
	174	*/
	175
	176	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	177	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
	178
6d0f6bcf	179	#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
c609719b WD	180
c609719b WD	181	/* MCCR1 */
6d0f6bcf JCPV	182	#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
6d0f6bcf JCPV	183	#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
c609719b WD	184
c609719b WD	185	/* MCCR2 */
6d0f6bcf JCPV	186	#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
	187	#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
	188	#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
c609719b WD	189
c609719b WD	190	/* MCCR3 */
6d0f6bcf JCPV	191	#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
	192	#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
	193	#define CONFIG_SYS_RDLAT 3 /* data latency from read command */
c609719b WD	194
c609719b WD	195	/* MCCR4 */
6d0f6bcf JCPV	196	#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
	197	#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
	198	#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
	199	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
	200	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
	201	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
	202	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
c609719b WD	203
	204	/* Memory bank settings:
	205	*
	206	* only bits 20-29 are actually used from these vales to set the
	207	* start/qend address the upper two bits will be 0, and the lower 20
	208	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	209	* end address
	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_BANK0_START 0x00000000
	212	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	213	#define CONFIG_SYS_BANK0_ENABLE 1
	214	#define CONFIG_SYS_BANK1_START 0x00000000
	215	#define CONFIG_SYS_BANK1_END 0x00000000
	216	#define CONFIG_SYS_BANK1_ENABLE 0
	217	#define CONFIG_SYS_BANK2_START 0x00000000
	218	#define CONFIG_SYS_BANK2_END 0x00000000
	219	#define CONFIG_SYS_BANK2_ENABLE 0
	220	#define CONFIG_SYS_BANK3_START 0x00000000
	221	#define CONFIG_SYS_BANK3_END 0x00000000
	222	#define CONFIG_SYS_BANK3_ENABLE 0
	223	#define CONFIG_SYS_BANK4_START 0x00000000
	224	#define CONFIG_SYS_BANK4_END 0x00000000
	225	#define CONFIG_SYS_BANK4_ENABLE 0
	226	#define CONFIG_SYS_BANK5_START 0x00000000
	227	#define CONFIG_SYS_BANK5_END 0x00000000
	228	#define CONFIG_SYS_BANK5_ENABLE 0
	229	#define CONFIG_SYS_BANK6_START 0x00000000
	230	#define CONFIG_SYS_BANK6_END 0x00000000
	231	#define CONFIG_SYS_BANK6_ENABLE 0
	232	#define CONFIG_SYS_BANK7_START 0x00000000
	233	#define CONFIG_SYS_BANK7_END 0x00000000
	234	#define CONFIG_SYS_BANK7_ENABLE 0
c609719b WD	235
	236	/*
	237	* Memory bank enable bitmask, specifying which of the banks defined above
	238	* are actually present. MSB is for bank #7, LSB is for bank #0.
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_BANK_ENABLE 0x01
c609719b	241
6d0f6bcf	242	#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
c609719b	243	/* see 8240 book for bit definitions */
6d0f6bcf	244	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
c609719b WD	245	/* currently accessed page in memory */
	246	/* see 8240 book for details */
	247
	248	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	249	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	250	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	253	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
c609719b WD	254
c609719b WD	255	/* PCI memory space */
6d0f6bcf JCPV	256	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	257	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	258
c609719b WD	259	/* Config addrs, etc */
6d0f6bcf JCPV	260	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	261	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	262
	263	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	264	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	265	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	266	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	267	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	268	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	269	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	270	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	271
	272	/*
	273	* For booting Linux, the board info and command line data
	274	* have to be in the first 8 MB of memory, since this is
	275	* the maximum mapped by the Linux kernel during initialization.
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	278
	279	/*
	280	* Cache Configuration
	281	*/
6d0f6bcf	282	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
acf02697	283	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	284	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	285	#endif
c609719b WD	286
c609719b	287	#endif /* __CONFIG_H */