[people/ms/u-boot.git] / include / configs / QS860T.h

/*
 * (C) Copyright 2003
 * MuLogic B.V.
 *
 * (C) Copyright 2002
 * Simple Network Magic Corporation
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* various debug settings */
#undef CFG_DEVICE_NULLDEV		/* null device */
#undef CONFIG_SILENT_CONSOLE		/* silent console */
#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
#undef DEBUG				/* debug output code */
#undef DEBUG_FLASH			/* debug flash code */
#undef FLASH_DEBUG			/* debug fash code */
#undef DEBUG_ENV			/* debug environment code */

#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */


/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU */
#define CONFIG_QS860T		1	/* ...on a QS860T module */

#define CONFIG_FEC_ENET		1	/* FEC 10/100BaseT ethernet */
#define FEC_INTERRUPT		SIU_LEVEL1
#undef CONFIG_SCC1_ENET			/* SCC1 10BaseT ethernet */
#define CFG_DISCOVER_PHY

#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC */
#undef CONFIG_8xx_CONS_NONE

#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

/* Pass clocks to Linux 2.4.18 in Hz */
#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT		"echo;" \
	"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
	"echo"

#undef CONFIG_BOOTARGS
/* TODO compare against CADM860 */
#define CONFIG_BOOTCOMMAND	"bootp; " \
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */

#undef CONFIG_WATCHDOG			/* watchdog disabled */

#undef CONFIG_STATUS_LED		/* Status LED disabled */

#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */

#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
	CFG_CMD_REGINFO	| \
	CFG_CMD_IMMAP	| \
	CFG_CMD_ASKENV	| \
	CFG_CMD_NET	| \
	CFG_CMD_DHCP	| \
	CFG_CMD_DATE	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>


/* TODO */
#if 0
/* Look at these */
CONFIG_IPADDR
CONFIG_SERVERIP
CONFIG_I2C
CONFIG_SPI
#endif

/*
 * Environment variable storage is in NVRAM
 */
#define CFG_ENV_IS_IN_NVRAM	1
#define CFG_ENV_SIZE		0x00001000	/* We use only the last 4K for PPCBoot */
#define CFG_ENV_ADDR		0xD100E000

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP				/* undef to save memory */
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */

#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2	"> "

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */

/* TODO - size? */
#define CFG_MEMTEST_START	0x0400000	/* memtest works */
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF00000

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/* TODO flash parameters */
/*-----------------------------------------------------------------------
 * FLASH organization for Intel Strataflash
 */
#define CFG_FLASH_16BIT		1		/* 16-bit wide flash memory */
#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	64		/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */

#undef	CFG_ENV_IS_IN_FLASH

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control 11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
#else
#define CFG_SYPCR	0xFFFFFF88
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration 11-6
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	0x00620000

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control 11-26
 *-----------------------------------------------------------------------
 */
#define CFG_TBSCR	0x00C3

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register 11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control 11-31
 *-----------------------------------------------------------------------
 */
#define CFG_PISCR	0x0082

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
 *-----------------------------------------------------------------------
 */
#define CFG_PLPRCR	0x0090D000

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	0x02000000


/*-----------------------------------------------------------------------
 * Debug Enable Register
 * 0x73E67C0F - All interrupts handled by BDM
 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
 *-----------------------------------------------------------------------
#define CFG_DER			0x73E67C0F
*/
#define CFG_DER			0x0082400F


/*-----------------------------------------------------------------------
 * Memory Controller Initialization Constants
 *-----------------------------------------------------------------------
 */

/*
 * BR0 and OR0 (AMD 512K Socketed FLASH)
 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
 */
#define CFG_PRELIM_OR_AM
#define CFG_OR_TIMING_FLASH

#define FLASH_BASE0_PRELIM	0xFFF00001
#define CFG_OR0_PRELIM		0xFFF80D42
#define CFG_BR0_PRELIM		0xFFF00401


/*
 * BR1 and OR1 (Intel 8M StrataFLASH)
 * Base address = 0xD000_0000 - 0xD07F_FFFF
 */

#define FLASH_BASE1_PRELIM	0xD0000000
#define CFG_OR1_PRELIM		0xFF800D42
#define CFG_BR1_PRELIM		0xD0000801
/* #define CFG_OR1		0xFF800D42 */
/* #define CFG_BR1		0xD0000801 */


/*
 * BR2 and OR2 (SDRAM)
 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
 *
 */
#define SDRAM_BASE		0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */

/* SDRAM timing */
#define SDRAM_TIMING		0x00000A00

/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
#define CFG_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */

/* For boards with 64M of SDRAM */
#define SDRAM_64M_MAX_SIZE	0x04000000	/* max 64MB SDRAM */
/* TODO - determine real value */
#define CFG_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */

#define CFG_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
#define CFG_BR2			(SDRAM_BASE | 0x000000C1)


/*
 * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
 * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
 * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
 * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
 * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
 *
 */

#define CFG_OR3_PRELIM		0xFFC00DF6
#define CFG_BR3_PRELIM		0xD1000401
/* #define CFG_OR3		0xFFC00DF6 */
/* #define CFG_BR3		0xD1000401 */


/*
 * BR4 and OR4 (Unused)
 * Base address = 0xE000_0000 - 0xE3FF_FFFF
 *
 */

#define CFG_OR4_PRELIM		0xFF000000
#define CFG_BR4_PRELIM		0xE0000000
/* #define CFG_OR4		0xFF000000 */
/* #define CFG_BR4		0xE0000000 */


/*
 * BR5 and OR5 (Expansion bus)
 * Base address = 0xE400_0000 - 0xE7FF_FFFF
 *
 */

#define CFG_OR5_PRELIM		0xFF000000
#define CFG_BR5_PRELIM		0xE4000000
/* #define CFG_OR5		0xFF000000 */
/* #define CFG_BR5		0xE4000000 */


/*
 * BR6 and OR6 (Expansion bus)
 * Base address = 0xE800_0000 - 0xEBFF_FFFF
 *
 */

#define CFG_OR6_PRELIM		0xFF000000
#define CFG_BR6_PRELIM		0xE8000000
/* #define CFG_OR6		0xFF000000 */
/* #define CFG_BR6		0xE8000000 */


/*
 * BR7 and OR7 (Expansion bus)
 * Base address = 0xEC00_0000 - 0xEFFF_FFFF
 *
 */

#define CFG_OR7_PRELIM		0xFF000000
#define CFG_BR7_PRELIM		0xE8000000
/* #define CFG_OR7		0xFF000000 */
/* #define CFG_BR7		0xE8000000 */


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

/*
 * Sanity checks
 */
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
3bbc899f WD	1	/*
	2	* (C) Copyright 2003
	3	* MuLogic B.V.
	4	*
	5	* (C) Copyright 2002
	6	* Simple Network Magic Corporation
	7	*
	8	* (C) Copyright 2000
	9	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* board/config.h - configuration options, board specific
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* various debug settings */
	38	#undef CFG_DEVICE_NULLDEV /* null device */
	39	#undef CONFIG_SILENT_CONSOLE /* silent console */
	40	#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
	41	#undef DEBUG /* debug output code */
	42	#undef DEBUG_FLASH /* debug flash code */
	43	#undef FLASH_DEBUG /* debug fash code */
	44	#undef DEBUG_ENV /* debug environment code */
	45
	46	#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
	47	#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
	48
	49
3bbc899f WD	50	/*
	51	* High Level Configuration Options
	52	* (easy to change)
	53	*/
	54
	55	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	56	#define CONFIG_QS860T 1 /* ...on a QS860T module */
	57
	58	#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
	59	#define FEC_INTERRUPT SIU_LEVEL1
	60	#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
	61	#define CFG_DISCOVER_PHY
	62
	63	#undef CONFIG_8xx_CONS_SMC1
	64	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */
	65	#undef CONFIG_8xx_CONS_NONE
	66
	67	#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
	68
	69	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	70
	71	/* Pass clocks to Linux 2.4.18 in Hz */
	72	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
	73
	74	#define CONFIG_PREBOOT "echo;" \
	75	"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
	76	"echo"
	77
	78	#undef CONFIG_BOOTARGS
	79	/* TODO compare against CADM860 */
	80	#define CONFIG_BOOTCOMMAND "bootp; " \
	81	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	82	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	83	"bootm"
	84
	85	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	86	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	87
	88	#undef CONFIG_WATCHDOG /* watchdog disabled */
	89
	90	#undef CONFIG_STATUS_LED /* Status LED disabled */
	91
	92	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	93
	94	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	95
	96	#define CONFIG_MAC_PARTITION
	97	#define CONFIG_DOS_PARTITION
	98
	99	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	100
	101	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	102	CFG_CMD_REGINFO \| \
	103	CFG_CMD_IMMAP \| \
	104	CFG_CMD_ASKENV \| \
	105	CFG_CMD_NET \| \
	106	CFG_CMD_DHCP \| \
	107	CFG_CMD_DATE )
	108
	109	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	110	#include <cmd_confdefs.h>
	111
	112
	113	/* TODO */
114	#if 0
115	/* Look at these */
116	CONFIG_IPADDR
117	CONFIG_SERVERIP
118	CONFIG_I2C
119	CONFIG_SPI
120	#endif
121
122	/*
123	* Environment variable storage is in NVRAM
124	*/
125	#define CFG_ENV_IS_IN_NVRAM 1
126	#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */
127	#define CFG_ENV_ADDR 0xD100E000
128
129	/*
130	* Miscellaneous configurable options
131	*/
132	#define CFG_LONGHELP /* undef to save memory */
133	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
134
135	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
136	#define CFG_PROMPT_HUSH_PS2 "> "
137
138	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
139	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
140	#else
141	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
142	#endif
143	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
144	#define CFG_MAXARGS 16 /* max number of command args */
145	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
146
147	/* TODO - size? */
148	#define CFG_MEMTEST_START 0x0400000 /* memtest works */
149	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
150
151	#define CFG_LOAD_ADDR 0x100000 /* default load address */
152
153	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
154
155	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156
157	/*-----------------------------------------------------------------------
158	* Low Level Configuration Settings
159	* (address mappings, register initial values, etc.)
160	* You should know what you are doing if you make changes here.
161	*/
162	/*-----------------------------------------------------------------------
163	* Internal Memory Mapped Register
164	*/
165	#define CFG_IMMR 0xF0000000
166
167	/*-----------------------------------------------------------------------
168	* Definitions for initial stack pointer and data area (in DPRAM)
169	*/
170	#define CFG_INIT_RAM_ADDR CFG_IMMR
171	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176	/*-----------------------------------------------------------------------
177	* Start addresses for the final memory configuration
178	* (Set up by the startup code)
179	* Please note that CFG_SDRAM_BASE _must_ start at 0
180	*/
181	#define CFG_SDRAM_BASE 0x00000000
182	#define CFG_FLASH_BASE 0xFFF00000
183
184	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
185	#define CFG_MONITOR_BASE CFG_FLASH_BASE
186	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
187
188	/*
189	* For booting Linux, the board info and command line data
190	* have to be in the first 8 MB of memory, since this is
191	* the maximum mapped by the Linux kernel during initialization.
192	*/
193	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
194
195	/* TODO flash parameters */
196	/*-----------------------------------------------------------------------
197	* FLASH organization for Intel Strataflash
198	*/
199	#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */
200	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
201	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
202
203	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
205
206	#undef CFG_ENV_IS_IN_FLASH
207
208	/*-----------------------------------------------------------------------
209	* Cache Configuration
210	*/
211	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
212	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
213	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
214	#endif
215
216	/*-----------------------------------------------------------------------
217	* SYPCR - System Protection Control 11-9
218	* SYPCR can only be written once after reset!
219	*-----------------------------------------------------------------------
220	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
221	*/
222	#if defined(CONFIG_WATCHDOG)
223	#define CFG_SYPCR (0xFFFFFF88 \| SYPCR_SWE \| SYPCR_SWRI)
224	#else
225	#define CFG_SYPCR 0xFFFFFF88
226	#endif
227
228	/*-----------------------------------------------------------------------
229	* SIUMCR - SIU Module Configuration 11-6
230	*-----------------------------------------------------------------------
231	*/
232	#define CFG_SIUMCR 0x00620000
233
234	/*-----------------------------------------------------------------------
235	* TBSCR - Time Base Status and Control 11-26
236	*-----------------------------------------------------------------------
237	*/
238	#define CFG_TBSCR 0x00C3
239
240	/*-----------------------------------------------------------------------
241	* RTCSC - Real-Time Clock Status and Control Register 11-27
242	*-----------------------------------------------------------------------
243	*/
244	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
245
246	/*-----------------------------------------------------------------------
247	* PISCR - Periodic Interrupt Status and Control 11-31
248	*-----------------------------------------------------------------------
249	*/
250	#define CFG_PISCR 0x0082
251
252	/*-----------------------------------------------------------------------
253	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
254	*-----------------------------------------------------------------------
255	*/
256	#define CFG_PLPRCR 0x0090D000
257
258	/*-----------------------------------------------------------------------
259	* SCCR - System Clock and reset Control Register 15-27
260	*-----------------------------------------------------------------------
261	*/
262	#define SCCR_MASK SCCR_EBDF11
263	#define CFG_SCCR 0x02000000
264
265
266	/*-----------------------------------------------------------------------
267	* Debug Enable Register
268	* 0x73E67C0F - All interrupts handled by BDM
269	* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
270	*-----------------------------------------------------------------------
271	#define CFG_DER 0x73E67C0F
272	*/
273	#define CFG_DER 0x0082400F
274
275
276	/*-----------------------------------------------------------------------
277	* Memory Controller Initialization Constants
278	*-----------------------------------------------------------------------
279	*/
280
281	/*
282	* BR0 and OR0 (AMD 512K Socketed FLASH)
283	* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
284	*/
285	#define CFG_PRELIM_OR_AM
286	#define CFG_OR_TIMING_FLASH
287
288	#define FLASH_BASE0_PRELIM 0xFFF00001
289	#define CFG_OR0_PRELIM 0xFFF80D42
290	#define CFG_BR0_PRELIM 0xFFF00401
291
292
293	/*
294	* BR1 and OR1 (Intel 8M StrataFLASH)
295	* Base address = 0xD000_0000 - 0xD07F_FFFF
296	*/
297
298	#define FLASH_BASE1_PRELIM 0xD0000000
299	#define CFG_OR1_PRELIM 0xFF800D42
300	#define CFG_BR1_PRELIM 0xD0000801
301	/* #define CFG_OR1 0xFF800D42 */
302	/* #define CFG_BR1 0xD0000801 */
303
304
305	/*
306	* BR2 and OR2 (SDRAM)
307	* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
308	* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
309	* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
310	*
311	*/
312	#define SDRAM_BASE 0x00000000 /* SDRAM bank */
313	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
314
315	/* SDRAM timing */
316	#define SDRAM_TIMING 0x00000A00
317
318	/* For boards with 16M of SDRAM */
319	#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
320	#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */
321
322	/* For boards with 64M of SDRAM */
323	#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */
324	/* TODO - determine real value */
325	#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */
326
327	#define CFG_OR2 (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING)
328	#define CFG_BR2 (SDRAM_BASE \| 0x000000C1)
329
330
331	/*
332	* BR3 and OR3 (NVRAM, Sipex, NAND Flash)
333	* Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
334	* Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
335	* Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
336	* Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
337	*
338	*/
339
340	#define CFG_OR3_PRELIM 0xFFC00DF6
341	#define CFG_BR3_PRELIM 0xD1000401
342	/* #define CFG_OR3 0xFFC00DF6 */
343	/* #define CFG_BR3 0xD1000401 */
344
345
346	/*
347	* BR4 and OR4 (Unused)
348	* Base address = 0xE000_0000 - 0xE3FF_FFFF
349	*
350	*/
351
352	#define CFG_OR4_PRELIM 0xFF000000
353	#define CFG_BR4_PRELIM 0xE0000000
354	/* #define CFG_OR4 0xFF000000 */
355	/* #define CFG_BR4 0xE0000000 */
356
357
358	/*
359	* BR5 and OR5 (Expansion bus)
360	* Base address = 0xE400_0000 - 0xE7FF_FFFF
361	*
362	*/
363
364	#define CFG_OR5_PRELIM 0xFF000000
365	#define CFG_BR5_PRELIM 0xE4000000
366	/* #define CFG_OR5 0xFF000000 */
367	/* #define CFG_BR5 0xE4000000 */
368
369
3bbc899f WD	370	/*
	371	* BR6 and OR6 (Expansion bus)
	372	* Base address = 0xE800_0000 - 0xEBFF_FFFF
	373	*
	374	*/
	375
	376	#define CFG_OR6_PRELIM 0xFF000000
	377	#define CFG_BR6_PRELIM 0xE8000000
	378	/* #define CFG_OR6 0xFF000000 */
	379	/* #define CFG_BR6 0xE8000000 */
	380
	381
3bbc899f WD	382	/*
	383	* BR7 and OR7 (Expansion bus)
	384	* Base address = 0xEC00_0000 - 0xEFFF_FFFF
	385	*
	386	*/
	387
	388	#define CFG_OR7_PRELIM 0xFF000000
	389	#define CFG_BR7_PRELIM 0xE8000000
	390	/* #define CFG_OR7 0xFF000000 */
	391	/* #define CFG_BR7 0xE8000000 */
	392
	393
3bbc899f WD	394	/*
	395	* Internal Definitions
	396	*
	397	* Boot Flags
	398	*/
	399	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	400	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	401
	402	/*
	403	* Sanity checks
	404	*/
	405	#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
	406	#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
	407	#endif
	408
	409	#endif /* __CONFIG_H */