[people/ms/u-boot.git] / include / configs / RRvision.h

/*
 * (C) Copyright 2000, 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_RRVISION		1	/* ...on a RRvision board	*/

#define CONFIG_8xx_GCLK_FREQ 64000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"setenv stdout serial"

#undef	CONFIG_BOOTARGS
#define CONFIG_ETHADDR                00:50:C2:00:E0:70
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_IPADDR                 10.0.0.5
#define CONFIG_SERVERIP               10.0.0.2
#define CONFIG_NETMASK                255.0.0.0
#define CONFIG_ROOTPATH               /opt/eldk/ppc_8xx
#define CONFIG_BOOTCOMMAND            "run flash_self"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip)"	\
		":$(gatewayip):$(netmask):$(hostname):$(netdev):off\0"	\
	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
	"update=protect off 1:0-8;era 1:0-8;"				\
		"cp.b 100000 40000000 $(filesize);"			\
		"setenv filesize;saveenv\0"				\
	"kernel_addr=40040000\0"					\
	"ramdisk_addr=40100000\0"					\
	"kernel_img=/tftpboot/uImage\0"					\
	"kernel_load=tftp 200000 $(kernel_img)\0"			\
	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
	"flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0"	\
	"flash_self=run ramargs addip addtty;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"


#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_STATUS_LED		/* disturbs display		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


#if 1
#define CONFIG_VIDEO		1	/* To enable the video initialization */

/* Video related */
#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x2A	/* ALSB to ground */
#endif

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C         	/* I2C bit-banged		*/

# define CFG_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
# define CFG_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */


#define CONFIG_COMMANDS	    ( ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IDE	| \
				CFG_CMD_DATE	) & \
			     ~( CFG_CMD_PCMCIA  | \
			        CFG_CMD_IDE	) )

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

/* timeout values are in ticks = ms */
#define CFG_FLASH_ERASE_TOUT	(120*CFG_HZ)	/* Timeout for Flash Erase	*/
#define CFG_FLASH_WRITE_TOUT	(1 * CFG_HZ)	/* Timeout for Flash Write	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */

/* for 64 MHz, we use a 16 MHz clock * 4 */
#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#define CFG_MAMR_PTA		129

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	37	#define CONFIG_RRVISION 1 /* ...on a RRvision board */
	38
	39	#define CONFIG_8xx_GCLK_FREQ 64000000
	40
	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
	44	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	49	#endif
	50
	51	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	52
	53	#define CONFIG_PREBOOT "setenv stdout serial"
	54
	55	#undef CONFIG_BOOTARGS
	56	#define CONFIG_ETHADDR 00:50:C2:00:E0:70
	57	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
	58	#define CONFIG_IPADDR 10.0.0.5
	59	#define CONFIG_SERVERIP 10.0.0.2
	60	#define CONFIG_NETMASK 255.0.0.0
	61	#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx
	62	#define CONFIG_BOOTCOMMAND "run flash_self"
	63
	64	#define CONFIG_EXTRA_ENV_SETTINGS \
65	"netdev=eth0\0" \
66	"ramargs=setenv bootargs root=/dev/ram rw\0" \
67	"nfsargs=setenv bootargs root=/dev/nfs rw " \
68	"nfsroot=$(serverip):$(rootpath)\0" \
69	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip)" \
70	":$(gatewayip):$(netmask):$(hostname):$(netdev):off\0" \
71	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
72	"load=tftp 100000 /tftpboot/u-boot.bin\0" \
73	"update=protect off 1:0-8;era 1:0-8;" \
74	"cp.b 100000 40000000 $(filesize);" \
75	"setenv filesize;saveenv\0" \
76	"kernel_addr=40040000\0" \
77	"ramdisk_addr=40100000\0" \
3bac3513	78	"kernel_img=/tftpboot/uImage\0" \
e2211743 WD	79	"kernel_load=tftp 200000 $(kernel_img)\0" \
	80	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
	81	"flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \
	82	"flash_self=run ramargs addip addtty;" \
	83	"bootm $(kernel_addr) $(ramdisk_addr)\0"
	84
	85
	86	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	87	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	88
	89	#undef CONFIG_WATCHDOG /* watchdog disabled */
	90
	91	#undef CONFIG_STATUS_LED /* disturbs display */
	92
	93	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	94
	95	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	96
	97	#define CONFIG_MAC_PARTITION
	98	#define CONFIG_DOS_PARTITION
	99
	100	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	101
	102
	103	#if 1
	104	#define CONFIG_VIDEO 1 /* To enable the video initialization */
	105
	106	/* Video related */
	107	#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
	108	#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
	109	#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x2A /* ALSB to ground */
	110	#endif
	111
	112	/* enable I2C and select the hardware/software driver */
	113	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	114	#define CONFIG_SOFT_I2C /* I2C bit-banged */
	115
	116	# define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */
	117	# define CFG_I2C_SLAVE 0xFE
	118
	119	#ifdef CONFIG_SOFT_I2C
	120	/*
	121	* Software (bit-bang) I2C driver configuration
	122	*/
	123	#define PB_SCL 0x00000020 /* PB 26 */
	124	#define PB_SDA 0x00000010 /* PB 27 */
	125
	126	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	127	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	128	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	129	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	130	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	131	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	132	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	133	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	134	#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
	135	#endif /* CONFIG_SOFT_I2C */
	136
	137
	138
	139	#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL \| \
	140	CFG_CMD_DHCP \| \
	141	CFG_CMD_I2C \| \
	142	CFG_CMD_IDE \| \
143	CFG_CMD_DATE ) & \
144	~( CFG_CMD_PCMCIA \| \
145	CFG_CMD_IDE ) )
146
147	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
148	#include <cmd_confdefs.h>
149
150	/*
151	* Miscellaneous configurable options
152	*/
153	#define CFG_LONGHELP /* undef to save memory */
154	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
155	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
156	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
157	#else
158	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
159	#endif
160	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
161	#define CFG_MAXARGS 16 /* max number of command args */
162	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
163
164	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
165	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
166
167	#define CFG_LOAD_ADDR 0x100000 /* default load address */
168
169	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
170
171	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
172
173	/*
174	* Low Level Configuration Settings
175	* (address mappings, register initial values, etc.)
176	* You should know what you are doing if you make changes here.
177	*/
178	/*-----------------------------------------------------------------------
179	* Internal Memory Mapped Register
180	*/
181	#define CFG_IMMR 0xFFF00000
182
183	/*-----------------------------------------------------------------------
184	* Definitions for initial stack pointer and data area (in DPRAM)
185	*/
186	#define CFG_INIT_RAM_ADDR CFG_IMMR
187	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
188	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
189	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
190	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
191
192	/*-----------------------------------------------------------------------
193	* Start addresses for the final memory configuration
194	* (Set up by the startup code)
195	* Please note that CFG_SDRAM_BASE _must_ start at 0
196	*/
197	#define CFG_SDRAM_BASE 0x00000000
198	#define CFG_FLASH_BASE 0x40000000
199	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
200	#define CFG_MONITOR_BASE CFG_FLASH_BASE
201	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
202
203	/*
204	* For booting Linux, the board info and command line data
205	* have to be in the first 8 MB of memory, since this is
206	* the maximum mapped by the Linux kernel during initialization.
207	*/
208	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
209
210	/*-----------------------------------------------------------------------
211	* FLASH organization
212	*/
213	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
214	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
215
216	/* timeout values are in ticks = ms */
217	#define CFG_FLASH_ERASE_TOUT (120CFG_HZ) / Timeout for Flash Erase */
218	#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */
219
220	#define CFG_ENV_IS_IN_FLASH 1
221	#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
222	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
223
224	/* Address and size of Redundant Environment Sector */
225	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
226	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
227
228	/*-----------------------------------------------------------------------
229	* Cache Configuration
230	*/
231	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
232	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
233	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
234	#endif
235
236	/*-----------------------------------------------------------------------
237	* SYPCR - System Protection Control 11-9
238	* SYPCR can only be written once after reset!
239	*-----------------------------------------------------------------------
240	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
241	*/
242	#if defined(CONFIG_WATCHDOG)
243	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
244	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
245	#else
246	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
247	#endif
248
249	/*-----------------------------------------------------------------------
250	* SIUMCR - SIU Module Configuration 11-6
251	*-----------------------------------------------------------------------
252	* PCMCIA config., multi-function pin tri-state
253	*/
254	#ifndef CONFIG_CAN_DRIVER
255	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
256	#else /* we must activate GPL5 in the SIUMCR for CAN */
257	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
258	#endif /* CONFIG_CAN_DRIVER */
259
260	/*-----------------------------------------------------------------------
261	* TBSCR - Time Base Status and Control 11-26
262	*-----------------------------------------------------------------------
263	* Clear Reference Interrupt Status, Timebase freezing enabled
264	*/
265	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
266
267	/*-----------------------------------------------------------------------
268	* RTCSC - Real-Time Clock Status and Control Register 11-27
269	*-----------------------------------------------------------------------
270	*/
271	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
272
273	/*-----------------------------------------------------------------------
274	* PISCR - Periodic Interrupt Status and Control 11-31
275	*-----------------------------------------------------------------------
276	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
277	*/
278	#define CFG_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
279
280	/*-----------------------------------------------------------------------
281	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
282	*-----------------------------------------------------------------------
283	* Reset PLL lock status sticky bit, timer expired status bit and timer
284	* interrupt status bit
285	*/
286
287	/* for 64 MHz, we use a 16 MHz clock * 4 */
288	#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
289
290	/*-----------------------------------------------------------------------
291	* SCCR - System Clock and reset Control Register 15-27
292	*-----------------------------------------------------------------------
293	* Set clock output, timebase and RTC source and divider,
294	* power management and some other internal clocks
295	*/
296	#define SCCR_MASK SCCR_EBDF11
297	#define CFG_SCCR (/* SCCR_TBS \| */ SCCR_RTSEL \| SCCR_RTDIV \| \
298	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
299	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
300	SCCR_DFALCD00)
301
302	/*-----------------------------------------------------------------------
303	* PCMCIA stuff
304	*-----------------------------------------------------------------------
305	*
306	*/
307	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
308	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
309	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
310	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
311	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
312	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
313	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
314	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
315
316	/*-----------------------------------------------------------------------
317	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318	*-----------------------------------------------------------------------
319	*/
320
321	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
322
323	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324	#undef CONFIG_IDE_LED /* LED for ide not supported */
325	#undef CONFIG_IDE_RESET /* reset for ide not supported */
326
327	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
328	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
329
330	#define CFG_ATA_IDE0_OFFSET 0x0000
331
332	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
333
334	/* Offset for data I/O */
335	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
336
337	/* Offset for normal register accesses */
338	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
339
340	/* Offset for alternate registers */
341	#define CFG_ATA_ALT_OFFSET 0x0100
342
343	/*-----------------------------------------------------------------------
344	*
345	*-----------------------------------------------------------------------
346	*
347	*/
e2211743 WD	348	#define CFG_DER 0
	349
	350	/*
	351	* Init Memory Controller:
	352	*
	353	* BR0/1 (FLASH)
	354	*/
	355
	356	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	357
	358	/* used to re-map FLASH both when starting from SRAM or FLASH:
	359	* restrict access enough to keep SRAM working (if any)
	360	* but not too much to meddle with FLASH accesses
	361	*/
	362	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	363	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	364
	365	/*
	366	* FLASH timing:
	367	*/
	368	/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
	369	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
	370	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
	371
	372	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	373	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	374	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
	375
	376	/*
	377	* BR2/3 and OR2/3 (SDRAM)
	378	*
	379	*/
	380	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	381	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	382	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	383
	384	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	385	#define CFG_OR_TIMING_SDRAM 0x00000A00
	386
	387	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	388	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	389
	390	#ifndef CONFIG_CAN_DRIVER
	391	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
	392	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	393	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
	394	#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	395	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	396	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \| OR_BI)
	397	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
	398	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	399	#endif /* CONFIG_CAN_DRIVER */
	400
	401	/*
	402	* Memory Periodic Timer Prescaler
	403	*
	404	* The Divider for PTA (refresh timer) configuration is based on an
	405	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	406	* the number of chip selects (NCS) and the actually needed refresh
	407	* rate is done by setting MPTPR.
	408	*
	409	* PTA is calculated from
	410	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	411	*
412	* gclk CPU clock (not bus clock!)
413	* Trefresh Refresh cycle * 4 (four word bursts used)
414	*
415	* 4096 Rows from SDRAM example configuration
416	* 1000 factor s -> ms
417	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
418	* 4 Number of refresh cycles per period
419	* 64 Refresh cycle in ms per number of rows
420	* --------------------------------------------
421	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
422	*
423	* 50 MHz => 50.000.000 / Divider = 98
424	* 66 Mhz => 66.000.000 / Divider = 129
425	* 80 Mhz => 80.000.000 / Divider = 156
426	*/
427	#define CFG_MAMR_PTA 129
428
429	/*
430	* For 16 MBit, refresh rates could be 31.3 us
431	* (= 64 ms / 2K = 125 / quad bursts).
432	* For a simpler initialization, 15.6 us is used instead.
433	*
434	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
435	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
436	*/
437	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
438	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
439
440	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
441	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
442	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
443
444	/*
445	* MAMR settings for SDRAM
446	*/
447
448	/* 8 column SDRAM */
449	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
450	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
451	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
452	/* 9 column SDRAM */
453	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
454	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
455	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
456
457
458	/*
459	* Internal Definitions
460	*
461	* Boot Flags
462	*/
463	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
464	#define BOOTFLAG_WARM 0x02 /* Software reboot */
465
466	#endif /* __CONFIG_H */