[people/ms/u-boot.git] / include / configs / SM850.h

/*
 * (C) Copyright 2000-2008
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef TQM8xxL_80MHz	/*	1	/ * define for 80 MHz CPU only	*/

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_SM850		1	/*...on a MPC850 Service Module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10
#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_STATUS_LED		/* Status LED not enabled	*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DATE


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET	0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CONFIG_SYS_PLPRCR							\
		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#else
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#endif	/* TQM8xxL_80MHz */

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#else			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#endif	/* TQM8xxL_80MHz */

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
75dc29eb	1	/*
7c803be2	2	* (C) Copyright 2000-2008
75dc29eb WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
75dc29eb WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
75dc29eb WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	23	#define CONFIG_SM850 1 /...on a MPC850 Service Module /
	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	26
75dc29eb	27	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
3cb7a480 WD	28	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	29	#define CONFIG_SYS_MAXIDLE 10
75dc29eb	30	#define CONFIG_BAUDRATE 115200
75dc29eb	31	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
75dc29eb WD	32
	33	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	34
	35	#define CONFIG_BOARD_TYPES 1 /* support board types */
	36
	37	#undef CONFIG_BOOTARGS
	38	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	39	"bootp; " \
	40	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	41	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
75dc29eb WD	42	"bootm"
	43
	44	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	45	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75dc29eb WD	46
	47	#undef CONFIG_WATCHDOG /* watchdog disabled */
	48
	49	#undef CONFIG_STATUS_LED /* Status LED not enabled */
	50
	51	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	52
18225e8d JL	53	/*
	54	* BOOTP options
	55	*/
	56	#define CONFIG_BOOTP_SUBNETMASK
	57	#define CONFIG_BOOTP_GATEWAY
	58	#define CONFIG_BOOTP_HOSTNAME
	59	#define CONFIG_BOOTP_BOOTPATH
	60	#define CONFIG_BOOTP_BOOTFILESIZE
	61
75dc29eb WD	62
	63	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	64
75dc29eb	65
fe7f782d JL	66	/*
	67	* Command line configuration.
	68	*/
	69	#include <config_cmd_default.h>
	70
	71	#define CONFIG_CMD_DHCP
	72	#define CONFIG_CMD_DATE
	73
75dc29eb WD	74
	75	/*
	76	* Miscellaneous configurable options
	77	*/
6d0f6bcf JCPV	78	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	79	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
fe7f782d	80	#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
6d0f6bcf	81	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
75dc29eb	82	#else
6d0f6bcf	83	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
75dc29eb	84	#endif
6d0f6bcf JCPV	85	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	86	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	87	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
75dc29eb	88
6d0f6bcf JCPV	89	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	90	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
75dc29eb	91
6d0f6bcf	92	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
75dc29eb	93
6d0f6bcf	94	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
75dc29eb	95
75dc29eb WD	96	/*
	97	* Low Level Configuration Settings
	98	* (address mappings, register initial values, etc.)
	99	* You should know what you are doing if you make changes here.
	100	*/
	101	/*-----------------------------------------------------------------------
	102	* Internal Memory Mapped Register
	103	*/
6d0f6bcf	104	#define CONFIG_SYS_IMMR 0xFFF00000
75dc29eb WD	105
	106	/*-----------------------------------------------------------------------
	107	* Definitions for initial stack pointer and data area (in DPRAM)
	108	*/
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	110	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	111	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	112	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
75dc29eb WD	113
	114	/*-----------------------------------------------------------------------
	115	* Start addresses for the final memory configuration
	116	* (Set up by the startup code)
6d0f6bcf	117	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
75dc29eb	118	*/
6d0f6bcf JCPV	119	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_BASE 0x40000000
75dc29eb	121	#if defined(DEBUG)
6d0f6bcf	122	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
75dc29eb	123	#else
6d0f6bcf	124	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
75dc29eb	125	#endif
6d0f6bcf JCPV	126	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	127	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
75dc29eb WD	128
	129	/*
	130	* For booting Linux, the board info and command line data
	131	* have to be in the first 8 MB of memory, since this is
	132	* the maximum mapped by the Linux kernel during initialization.
	133	*/
6d0f6bcf	134	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
75dc29eb WD	135
	136	/*-----------------------------------------------------------------------
	137	* FLASH organization
	138	*/
7c803be2	139	/* use CFI flash driver */
6d0f6bcf	140	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
7c803be2	141	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	142	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
	143	#define CONFIG_SYS_FLASH_EMPTY_INFO
	144	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	145	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	146	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
75dc29eb	147
5a1aceb0	148	#define CONFIG_ENV_IS_IN_FLASH 1
7c803be2	149	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586	150	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
75dc29eb	151
7c803be2 WD	152	#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
7c803be2 WD	153
75dc29eb WD	154	/*-----------------------------------------------------------------------
	155	* Hardware Information Block
	156	*/
6d0f6bcf JCPV	157	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	158	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	159	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
75dc29eb WD	160
	161	/*-----------------------------------------------------------------------
	162	* Cache Configuration
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
fe7f782d	165	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	166	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
75dc29eb WD	167	#endif
	168
	169	/*-----------------------------------------------------------------------
	170	* SYPCR - System Protection Control 11-9
	171	* SYPCR can only be written once after reset!
	172	*-----------------------------------------------------------------------
	173	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	174	*/
	175	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	176	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
75dc29eb WD	177	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
75dc29eb WD	178	#else
6d0f6bcf	179	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
75dc29eb WD	180	#endif
	181
	182	/*-----------------------------------------------------------------------
	183	* SIUMCR - SIU Module Configuration 11-6
	184	*-----------------------------------------------------------------------
	185	* PCMCIA config., multi-function pin tri-state
	186	*/
	187	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	188	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
75dc29eb	189	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	190	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
75dc29eb WD	191	#endif /* CONFIG_CAN_DRIVER */
	192
	193	/*-----------------------------------------------------------------------
	194	* TBSCR - Time Base Status and Control 11-26
	195	*-----------------------------------------------------------------------
	196	* Clear Reference Interrupt Status, Timebase freezing enabled
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
75dc29eb WD	199
	200	/*-----------------------------------------------------------------------
	201	* RTCSC - Real-Time Clock Status and Control Register 11-27
	202	*-----------------------------------------------------------------------
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
75dc29eb WD	205
	206	/*-----------------------------------------------------------------------
	207	* PISCR - Periodic Interrupt Status and Control 11-31
	208	*-----------------------------------------------------------------------
	209	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	210	*/
6d0f6bcf	211	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
75dc29eb WD	212
	213	/*-----------------------------------------------------------------------
	214	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	215	*-----------------------------------------------------------------------
	216	* Reset PLL lock status sticky bit, timer expired status bit and timer
	217	* interrupt status bit
	218	*
	219	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	220	*/
	221	#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
6d0f6bcf	222	#define CONFIG_SYS_PLPRCR \
75dc29eb WD	223	( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
75dc29eb WD	224	#else
6d0f6bcf	225	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
75dc29eb WD	226	#endif /* TQM8xxL_80MHz */
	227
	228	/*-----------------------------------------------------------------------
	229	* SCCR - System Clock and reset Control Register 15-27
	230	*-----------------------------------------------------------------------
	231	* Set clock output, timebase and RTC source and divider,
	232	* power management and some other internal clocks
	233	*/
	234	#define SCCR_MASK SCCR_EBDF11
	235	#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
6d0f6bcf	236	#define CONFIG_SYS_SCCR (/* SCCR_TBS \| */ \
75dc29eb WD	237	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	238	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	239	SCCR_DFALCD00)
	240	#else /* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	241	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
75dc29eb WD	242	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	243	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	244	SCCR_DFALCD00)
	245	#endif /* TQM8xxL_80MHz */
	246
	247	/*-----------------------------------------------------------------------
	248	* PCMCIA stuff
	249	*-----------------------------------------------------------------------
	250	*
	251	*/
6d0f6bcf JCPV	252	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	253	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	254	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	255	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	256	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	257	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	258	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	259	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
75dc29eb WD	260
	261	/*-----------------------------------------------------------------------
	262	*
	263	*-----------------------------------------------------------------------
	264	*
	265	*/
6d0f6bcf	266	#define CONFIG_SYS_DER 0
75dc29eb WD	267
	268	/*
	269	* Init Memory Controller:
	270	*
	271	* BR0/1 and OR0/1 (FLASH)
	272	*/
	273
	274	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	275	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	276
	277	/* used to re-map FLASH both when starting from SRAM or FLASH:
	278	* restrict access enough to keep SRAM working (if any)
	279	* but not too much to meddle with FLASH accesses
	280	*/
6d0f6bcf JCPV	281	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	282	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
75dc29eb WD	283
75dc29eb WD	284	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	285	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
75dc29eb WD	286	OR_SCY_5_CLK \| OR_EHTR)
75dc29eb WD	287
6d0f6bcf JCPV	288	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	289	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	290	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
75dc29eb	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	293	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	294	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
75dc29eb WD	295
	296	/*
	297	* BR2/3 and OR2/3 (SDRAM)
	298	*
	299	*/
	300	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	301	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	302	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	303
	304	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	305	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
75dc29eb	306
6d0f6bcf JCPV	307	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	308	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
75dc29eb WD	309
75dc29eb WD	310	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	311	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	312	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
75dc29eb	313	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	314	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	315	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	316	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	317	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
75dc29eb WD	318	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	319	#endif /* CONFIG_CAN_DRIVER */
	320
	321	/*
	322	* Memory Periodic Timer Prescaler
	323	*/
	324
	325	/* periodic timer for refresh */
6d0f6bcf	326	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
75dc29eb WD	327
75dc29eb WD	328	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	329	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	330	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
75dc29eb WD	331
75dc29eb WD	332	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	333	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	334	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
75dc29eb WD	335
	336	/*
	337	* MAMR settings for SDRAM
	338	*/
	339
	340	/* 8 column SDRAM */
6d0f6bcf	341	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
75dc29eb WD	342	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	343	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	344	/* 9 column SDRAM */
6d0f6bcf	345	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
75dc29eb WD	346	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	347	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	348
7026ead0 HS	349	/* pass open firmware flat tree */
	350	#define CONFIG_OF_LIBFDT 1
	351	#define CONFIG_OF_BOARD_SETUP 1
	352	#define CONFIG_HWCONFIG 1
	353
75dc29eb	354	#endif /* __CONFIG_H */