[people/ms/u-boot.git] / include / configs / Sandpoint8240.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8240		1
#define CONFIG_SANDPOINT	1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"

#if 0
#define USE_DINK32		1
#else
#undef USE_DINK32
#endif

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"net_self=tftp ${kernel_addr} ${bootfile};"			\
		"tftp ${ramdisk_addr} ${ramdisk};"			\
		"run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
		"run nfsargs addip;bootm\0"				\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/SP8240/uImage\0"				\
	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
	"kernel_addr=200000\0"						\
	"ramdisk_addr=400000\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP


#define CONFIG_DRAM_SPEED	100		/* MHz				*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#undef CONFIG_PCI_PNP


#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define	PCI_ENET1_IOADDR	0x81000000
#define	PCI_ENET1_MEMADDR	0x81000000


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	0x00090000
#define CONFIG_SYS_RAMBOOT		1
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00030000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE


#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#endif

#define CONFIG_SYS_FLASH_BASE		0xFFF00000
#if 0
#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
#else
#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
#endif
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

#define CONFIG_SYS_ISA_MEM		0xFD000000
#define CONFIG_SYS_ISA_IO		0xFE000000

#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support */
#undef  CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_SPEED	400000

#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly.  Please review!"
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
#define I2C_READ		((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
				else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
				else    iop->pdat &= ~0x00020000
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */


#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/


#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */


/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/

#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

/*
 * NS87308 Configuration
 */
#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */

#define CONFIG_SYS_NS87308_BADDR_10	1

#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
				  CONFIG_SYS_NS87308_UART2   | \
				  CONFIG_SYS_NS87308_POWRMAN | \
				  CONFIG_SYS_NS87308_RTC_APC )

#undef  CONFIG_SYS_NS87308_PS2MOD

#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
#define CONFIG_SYS_NS87308_CS0_CONF	0x30
#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
#define CONFIG_SYS_NS87308_CS1_CONF	0x30
#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
#define CONFIG_SYS_NS87308_CS2_CONF	0x30

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		1843200

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1

#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/

#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */

/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/

#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1

/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x3ff00000
#define CONFIG_SYS_BANK1_END		0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */

#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#undef	NR_8259_INTS
#define NR_8259_INTS		1


#define CONFIG_DISK_SPINUP_TIME 1000000


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
414eec35	2	* (C) Copyright 2001-2005
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
c609719b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/* ------------------------------------------------------------------------- */
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
c609719b WD	22	#define CONFIG_MPC8240 1
	23	#define CONFIG_SANDPOINT 1
	24
2ae18241	25	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
de550d6b	26	#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
2ae18241	27
c609719b WD	28	#if 0
	29	#define USE_DINK32 1
	30	#else
	31	#undef USE_DINK32
	32	#endif
	33
	34	#define CONFIG_CONS_INDEX 1
149dded2 WD	35	#define CONFIG_BAUDRATE 9600
	36
	37	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	38
	39	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	40
	41	#define CONFIG_PREBOOT "echo;" \
	42	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
	43	"echo"
	44
	45	#undef CONFIG_BOOTARGS
	46
	47	#define CONFIG_EXTRA_ENV_SETTINGS \
	48	"netdev=eth0\0" \
	49	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	50	"nfsroot=${serverip}:${rootpath}\0" \
149dded2	51	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	52	"addip=setenv bootargs ${bootargs} " \
	53	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	54	":${hostname}:${netdev}:off panic=1\0" \
	55	"net_self=tftp ${kernel_addr} ${bootfile};" \
	56	"tftp ${ramdisk_addr} ${ramdisk};" \
149dded2	57	"run ramargs addip;" \
fe126d8b WD	58	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	59	"net_nfs=tftp ${kernel_addr} ${bootfile};" \
149dded2 WD	60	"run nfsargs addip;bootm\0" \
	61	"rootpath=/opt/eldk/ppc_82xx\0" \
	62	"bootfile=/tftpboot/SP8240/uImage\0" \
	63	"ramdisk=/tftpboot/SP8240/uRamdisk\0" \
	64	"kernel_addr=200000\0" \
	65	"ramdisk_addr=400000\0" \
	66	""
	67	#define CONFIG_BOOTCOMMAND "run flash_self"
c609719b	68
fe7f782d	69
a1aa0bb5 JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
	78
fe7f782d JL	79	/*
	80	* Command line configuration.
	81	*/
	82	#include <config_cmd_default.h>
	83
	84	#define CONFIG_CMD_DHCP
	85	#define CONFIG_CMD_ELF
	86	#define CONFIG_CMD_I2C
	87	#define CONFIG_CMD_SDRAM
	88	#define CONFIG_CMD_EEPROM
	89	#define CONFIG_CMD_NFS
	90	#define CONFIG_CMD_PCI
	91	#define CONFIG_CMD_SNTP
	92
c609719b	93
149dded2	94	#define CONFIG_DRAM_SPEED 100 /* MHz */
c609719b WD	95
	96	/*
	97	* Miscellaneous configurable options
	98	*/
6d0f6bcf	99	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	100	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	101	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	102	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	103	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	104	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
c609719b WD	105
	106	/*-----------------------------------------------------------------------
	107	* PCI stuff
	108	*-----------------------------------------------------------------------
	109	*/
	110	#define CONFIG_PCI /* include pci support */
842033e6	111	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c609719b WD	112	#undef CONFIG_PCI_PNP
c609719b WD	113
c609719b WD	114
c609719b WD	115	#define CONFIG_EEPRO100
6d0f6bcf	116	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
c609719b WD	117
	118	#define PCI_ENET0_IOADDR 0x80000000
	119	#define PCI_ENET0_MEMADDR 0x80000000
	120	#define PCI_ENET1_IOADDR 0x81000000
	121	#define PCI_ENET1_MEMADDR 0x81000000
	122
	123
	124	/*-----------------------------------------------------------------------
	125	* Start addresses for the final memory configuration
	126	* (Set up by the startup code)
6d0f6bcf	127	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	128	*/
6d0f6bcf JCPV	129	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	130	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
c609719b	131
6d0f6bcf	132	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b WD	133
c609719b WD	134	#if defined (USE_DINK32)
6d0f6bcf JCPV	135	#define CONFIG_SYS_MONITOR_LEN 0x00030000
	136	#define CONFIG_SYS_MONITOR_BASE 0x00090000
	137	#define CONFIG_SYS_RAMBOOT 1
	138	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
553f0982	139	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
25ddd1fb	140	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	141	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	142	#else
6d0f6bcf JCPV	143	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	144	#define CONFIG_SYS_MONITOR_LEN 0x00030000
14d0a02a	145	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	146
c609719b	147
6d0f6bcf	148	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	149	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	150	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
c609719b WD	151
	152	#endif
	153
6d0f6bcf	154	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
c609719b	155	#if 0
6d0f6bcf	156	#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
c609719b	157	#else
6d0f6bcf	158	#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
c609719b	159	#endif
5a1aceb0	160	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	161	#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
0e8d1586 JCPV	162	#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
c609719b	163
6d0f6bcf	164	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
c609719b	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	167	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
c609719b	168
6d0f6bcf	169	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
c609719b	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_ISA_MEM 0xFD000000
6d0f6bcf JCPV	172	#define CONFIG_SYS_ISA_IO 0xFE000000
c609719b	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
c609719b WD	176	#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
	177	#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
	178
	179	/*
	180	* select i2c support configuration
	181	*
	182	* Supported configurations are {none, software, hardware} drivers.
	183	* If the software driver is chosen, there are some additional
	184	* configuration items that the driver uses to drive the port pins.
	185	*/
ea818dbb HS	186	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
	187	#undef CONFIG_SYS_I2C_SOFT
	188	#define CONFIG_SYS_I2C_SLAVE 0x7F
	189	#define CONFIG_SYS_I2C_SPEED 400000
c609719b	190
ea818dbb	191	#ifdef CONFIG_SYS_I2C_SOFT
c609719b	192	#error "Soft I2C is not configured properly. Please review!"
ea818dbb HS	193	#define CONFIG_SYS_I2C
	194	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	195	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
c609719b WD	196	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	197	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	198	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	199	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	200	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	201	else iop->pdat &= ~0x00010000
	202	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	203	else iop->pdat &= ~0x00020000
	204	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
ea818dbb	205	#endif /* CONFIG_SYS_I2C_SOFT */
c609719b WD	206
c609719b WD	207
6d0f6bcf JCPV	208	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
	209	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	210	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
	211	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
c609719b WD	212
c609719b WD	213
6d0f6bcf	214	#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
c609719b WD	215
	216	/*-----------------------------------------------------------------------
	217	* Definitions for initial stack pointer and data area (in DPRAM)
	218	*/
	219
	220
57d6c589	221	/* #define CONFIG_WINBOND_83C553 1 / has a winbond bridge /
6d0f6bcf JCPV	222	#define CONFIG_SYS_USE_WINBOND_IDE 0 /use winbond 83c553 internal IDE ctrlr /
	223	#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /pci-isa bridge config addr /
	224	#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /ide config addr /
c609719b	225
6d0f6bcf JCPV	226	#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
6d0f6bcf JCPV	227	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS2) / max. 2 drives per IDE bus */
c609719b WD	228
	229	/*
	230	* NS87308 Configuration
	231	*/
55d6d2d3	232	#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
c609719b	233
6d0f6bcf	234	#define CONFIG_SYS_NS87308_BADDR_10 1
c609719b	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 \| \
	237	CONFIG_SYS_NS87308_UART2 \| \
	238	CONFIG_SYS_NS87308_POWRMAN \| \
	239	CONFIG_SYS_NS87308_RTC_APC )
c609719b	240
6d0f6bcf	241	#undef CONFIG_SYS_NS87308_PS2MOD
c609719b	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
	244	#define CONFIG_SYS_NS87308_CS0_CONF 0x30
	245	#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
	246	#define CONFIG_SYS_NS87308_CS1_CONF 0x30
	247	#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
	248	#define CONFIG_SYS_NS87308_CS2_CONF 0x30
c609719b WD	249
	250	/*
	251	* NS16550 Configuration
	252	*/
6d0f6bcf JCPV	253	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	254	#define CONFIG_SYS_NS16550_SERIAL
c609719b	255
6d0f6bcf	256	#define CONFIG_SYS_NS16550_REG_SIZE 1
c609719b	257
6d0f6bcf	258	#define CONFIG_SYS_NS16550_CLK 1843200
c609719b	259
6d0f6bcf JCPV	260	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
6d0f6bcf JCPV	261	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
c609719b WD	262
	263	/*
	264	* Low Level Configuration Settings
	265	* (address mappings, register initial values, etc.)
	266	* You should know what you are doing if you make changes here.
	267	*/
	268
	269	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
7cb22f97	270	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
c609719b	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_ROMNAL 7 /rom/flash next access time /
6d0f6bcf JCPV	273	#define CONFIG_SYS_ROMFAL 11 /rom/flash access time /
c609719b	274
6d0f6bcf	275	#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
c609719b WD	276
c609719b WD	277	/* the following are for SDRAM only*/
6d0f6bcf JCPV	278	#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
	279	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
	280	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
	281	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	282	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	283	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	284	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	285	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	286	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
	287
	288	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
c609719b WD	289
	290	/* memory bank settings*/
	291	/*
	292	* only bits 20-29 are actually used from these vales to set the
	293	* start/end address the upper two bits will be 0, and the lower 20
	294	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	295	* end address
	296	*/
6d0f6bcf JCPV	297	#define CONFIG_SYS_BANK0_START 0x00000000
	298	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	299	#define CONFIG_SYS_BANK0_ENABLE 1
	300	#define CONFIG_SYS_BANK1_START 0x3ff00000
	301	#define CONFIG_SYS_BANK1_END 0x3fffffff
	302	#define CONFIG_SYS_BANK1_ENABLE 0
	303	#define CONFIG_SYS_BANK2_START 0x3ff00000
	304	#define CONFIG_SYS_BANK2_END 0x3fffffff
	305	#define CONFIG_SYS_BANK2_ENABLE 0
	306	#define CONFIG_SYS_BANK3_START 0x3ff00000
	307	#define CONFIG_SYS_BANK3_END 0x3fffffff
	308	#define CONFIG_SYS_BANK3_ENABLE 0
	309	#define CONFIG_SYS_BANK4_START 0x00000000
	310	#define CONFIG_SYS_BANK4_END 0x00000000
	311	#define CONFIG_SYS_BANK4_ENABLE 0
	312	#define CONFIG_SYS_BANK5_START 0x00000000
	313	#define CONFIG_SYS_BANK5_END 0x00000000
	314	#define CONFIG_SYS_BANK5_ENABLE 0
	315	#define CONFIG_SYS_BANK6_START 0x00000000
	316	#define CONFIG_SYS_BANK6_END 0x00000000
	317	#define CONFIG_SYS_BANK6_ENABLE 0
	318	#define CONFIG_SYS_BANK7_START 0x00000000
	319	#define CONFIG_SYS_BANK7_END 0x00000000
	320	#define CONFIG_SYS_BANK7_ENABLE 0
c609719b WD	321	/*
	322	* Memory bank enable bitmask, specifying which of the banks defined above
	323	are actually present. MSB is for bank #7, LSB is for bank #0.
	324	*/
6d0f6bcf	325	#define CONFIG_SYS_BANK_ENABLE 0x01
c609719b	326
6d0f6bcf	327	#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
c609719b	328	/* see 8240 book for bit definitions */
6d0f6bcf	329	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
c609719b WD	330	/* currently accessed page in memory */
	331	/* see 8240 book for details */
	332
	333	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	334	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	335	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	336
	337	/* stack in DCACHE @ 1GB (no backing mem) */
	338	#if defined(USE_DINK32)
6d0f6bcf JCPV	339	#define CONFIG_SYS_IBAT1L (0x40000000 \| BATL_PP_00 )
6d0f6bcf JCPV	340	#define CONFIG_SYS_IBAT1U (0x40000000 \| BATU_BL_128K )
c609719b	341	#else
6d0f6bcf JCPV	342	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	343	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
c609719b WD	344	#endif
	345
	346	/* PCI memory */
6d0f6bcf JCPV	347	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	348	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	349
c609719b WD	350	/* Flash, config addrs, etc */
6d0f6bcf JCPV	351	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	352	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	353
	354	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	355	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	356	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	357	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	358	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	359	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	360	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	361	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	362
	363	/*
	364	* For booting Linux, the board info and command line data
	365	* have to be in the first 8 MB of memory, since this is
	366	* the maximum mapped by the Linux kernel during initialization.
	367	*/
6d0f6bcf	368	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	369	/*-----------------------------------------------------------------------
	370	* FLASH organization
	371	*/
6d0f6bcf JCPV	372	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	373	#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
c609719b	374
6d0f6bcf JCPV	375	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	376	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	377
	378	/*-----------------------------------------------------------------------
	379	* Cache Configuration
	380	*/
6d0f6bcf	381	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
fe7f782d	382	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	383	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	384	#endif
c609719b WD	385
c609719b WD	386	/* values according to the manual */
	387
	388	#define CONFIG_DRAM_50MHZ 1
	389	#define CONFIG_SDRAM_50MHZ
	390
	391	#undef NR_8259_INTS
	392	#define NR_8259_INTS 1
	393
	394
	395	#define CONFIG_DISK_SPINUP_TIME 1000000
	396
	397
	398	#endif /* __CONFIG_H */