]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/Sandpoint8240.h
- CFG_RX_ETH_BUFFER added.
[people/ms/u-boot.git] / include / configs / Sandpoint8240.h
CommitLineData
c609719b
WD
1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_SANDPOINT 1
41
42#if 0
43#define USE_DINK32 1
44#else
45#undef USE_DINK32
46#endif
47
48#define CONFIG_CONS_INDEX 1
49#define CONFIG_BAUDRATE 115200
50#define CONFIG_DRAM_SPEED 100 /* MHz */
51
52#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_AUTOSCRIPT) | \
53 CFG_CMD_ELF | \
54 CFG_CMD_I2C | \
55 CFG_CMD_SDRAM | \
56 CFG_CMD_EEPROM | \
57 CFG_CMD_PCI )
58
59/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
60#include <cmd_confdefs.h>
61
62
63/*
64 * Miscellaneous configurable options
65 */
66#define CFG_LONGHELP 1 /* undef to save memory */
67#define CFG_PROMPT "=> " /* Monitor Command Prompt */
68#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
69#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
70#define CFG_MAXARGS 16 /* max number of command args */
71#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
72#define CFG_LOAD_ADDR 0x00100000 /* default load address */
73#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
74
75/*-----------------------------------------------------------------------
76 * PCI stuff
77 *-----------------------------------------------------------------------
78 */
79#define CONFIG_PCI /* include pci support */
80#undef CONFIG_PCI_PNP
81
82#define CONFIG_NET_MULTI /* Multi ethernet cards support */
83
84#define CONFIG_EEPRO100
53cf9435 85#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
c609719b
WD
86
87#define PCI_ENET0_IOADDR 0x80000000
88#define PCI_ENET0_MEMADDR 0x80000000
89#define PCI_ENET1_IOADDR 0x81000000
90#define PCI_ENET1_MEMADDR 0x81000000
91
92
93/*-----------------------------------------------------------------------
94 * Start addresses for the final memory configuration
95 * (Set up by the startup code)
96 * Please note that CFG_SDRAM_BASE _must_ start at 0
97 */
98#define CFG_SDRAM_BASE 0x00000000
99#define CFG_MAX_RAM_SIZE 0x10000000
100
101#define CFG_RESET_ADDRESS 0xFFF00100
102
103#if defined (USE_DINK32)
104#define CFG_MONITOR_LEN 0x00030000
105#define CFG_MONITOR_BASE 0x00090000
106#define CFG_RAMBOOT 1
107#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
108#define CFG_INIT_RAM_END 0x10000
109#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
110#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
111#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
112#else
113#undef CFG_RAMBOOT
114#define CFG_MONITOR_LEN 0x00030000
115#define CFG_MONITOR_BASE TEXT_BASE
116
117/*#define CFG_GBL_DATA_SIZE 256*/
118#define CFG_GBL_DATA_SIZE 128
119
120#define CFG_INIT_RAM_ADDR 0x40000000
121#define CFG_INIT_RAM_END 0x1000
122#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
123
124#endif
125
126#define CFG_FLASH_BASE 0xFFF00000
127#if 0
128#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
129#else
130#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
131#endif
132#define CFG_ENV_IS_IN_FLASH 1
133#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
134#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
135
136#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
137
138#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
139#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
140
141#define CFG_EUMB_ADDR 0xFC000000
142
143#define CFG_ISA_MEM 0xFD000000
144#define CFG_ISA_IO 0xFE000000
145
146#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
147#define CFG_FLASH_RANGE_SIZE 0x01000000
148#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
149#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
150
151/*
152 * select i2c support configuration
153 *
154 * Supported configurations are {none, software, hardware} drivers.
155 * If the software driver is chosen, there are some additional
156 * configuration items that the driver uses to drive the port pins.
157 */
158#define CONFIG_HARD_I2C 1 /* To enable I2C support */
159#undef CONFIG_SOFT_I2C /* I2C bit-banged */
160#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
161#define CFG_I2C_SLAVE 0x7F
162
163#ifdef CONFIG_SOFT_I2C
164#error "Soft I2C is not configured properly. Please review!"
165#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
166#define I2C_ACTIVE (iop->pdir |= 0x00010000)
167#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
168#define I2C_READ ((iop->pdat & 0x00010000) != 0)
169#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
170 else iop->pdat &= ~0x00010000
171#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
172 else iop->pdat &= ~0x00020000
173#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
174#endif /* CONFIG_SOFT_I2C */
175
176
177#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
178#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
179#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
180#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
181
182
183#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
184#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
185
186/*-----------------------------------------------------------------------
187 * Definitions for initial stack pointer and data area (in DPRAM)
188 */
189
190
191#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
192#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
193#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
194#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
195
196#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
197#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
198
199/*
200 * NS87308 Configuration
201 */
202#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
203
204#define CFG_NS87308_BADDR_10 1
205
206#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
207 CFG_NS87308_UART2 | \
208 CFG_NS87308_POWRMAN | \
209 CFG_NS87308_RTC_APC )
210
211#undef CFG_NS87308_PS2MOD
212
213#define CFG_NS87308_CS0_BASE 0x0076
214#define CFG_NS87308_CS0_CONF 0x30
215#define CFG_NS87308_CS1_BASE 0x0075
216#define CFG_NS87308_CS1_CONF 0x30
217#define CFG_NS87308_CS2_BASE 0x0074
218#define CFG_NS87308_CS2_CONF 0x30
219
220/*
221 * NS16550 Configuration
222 */
223#define CFG_NS16550
224#define CFG_NS16550_SERIAL
225
226#define CFG_NS16550_REG_SIZE 1
227
228#define CFG_NS16550_CLK 1843200
229
230#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
231#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
232
233/*
234 * Low Level Configuration Settings
235 * (address mappings, register initial values, etc.)
236 * You should know what you are doing if you make changes here.
237 */
238
239#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
240#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
241
242#define CFG_ROMNAL 7 /*rom/flash next access time */
243#define CFG_ROMFAL 11 /*rom/flash access time */
244
245#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
246
247/* the following are for SDRAM only*/
248#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
249#define CFG_REFREC 8 /* Refresh to activate interval */
250#define CFG_RDLAT 4 /* data latency from read command */
251#define CFG_PRETOACT 3 /* Precharge to activate interval */
252#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
253#define CFG_ACTORW 3 /* Activate to R/W */
254#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
255#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
256#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
257
258#define CFG_REGISTERD_TYPE_BUFFER 1
259
260/* memory bank settings*/
261/*
262 * only bits 20-29 are actually used from these vales to set the
263 * start/end address the upper two bits will be 0, and the lower 20
264 * bits will be set to 0x00000 for a start address, or 0xfffff for an
265 * end address
266 */
267#define CFG_BANK0_START 0x00000000
268#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
269#define CFG_BANK0_ENABLE 1
270#define CFG_BANK1_START 0x3ff00000
271#define CFG_BANK1_END 0x3fffffff
272#define CFG_BANK1_ENABLE 0
273#define CFG_BANK2_START 0x3ff00000
274#define CFG_BANK2_END 0x3fffffff
275#define CFG_BANK2_ENABLE 0
276#define CFG_BANK3_START 0x3ff00000
277#define CFG_BANK3_END 0x3fffffff
278#define CFG_BANK3_ENABLE 0
279#define CFG_BANK4_START 0x00000000
280#define CFG_BANK4_END 0x00000000
281#define CFG_BANK4_ENABLE 0
282#define CFG_BANK5_START 0x00000000
283#define CFG_BANK5_END 0x00000000
284#define CFG_BANK5_ENABLE 0
285#define CFG_BANK6_START 0x00000000
286#define CFG_BANK6_END 0x00000000
287#define CFG_BANK6_ENABLE 0
288#define CFG_BANK7_START 0x00000000
289#define CFG_BANK7_END 0x00000000
290#define CFG_BANK7_ENABLE 0
291/*
292 * Memory bank enable bitmask, specifying which of the banks defined above
293 are actually present. MSB is for bank #7, LSB is for bank #0.
294 */
295#define CFG_BANK_ENABLE 0x01
296
297#define CFG_ODCR 0xff /* configures line driver impedances, */
298 /* see 8240 book for bit definitions */
299#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
300 /* currently accessed page in memory */
301 /* see 8240 book for details */
302
303/* SDRAM 0 - 256MB */
304#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
305#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
306
307/* stack in DCACHE @ 1GB (no backing mem) */
308#if defined(USE_DINK32)
309#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
310#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
311#else
312#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
313#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
314#endif
315
316/* PCI memory */
317#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
318#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
319
320/* Flash, config addrs, etc */
321#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
322#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
323
324#define CFG_DBAT0L CFG_IBAT0L
325#define CFG_DBAT0U CFG_IBAT0U
326#define CFG_DBAT1L CFG_IBAT1L
327#define CFG_DBAT1U CFG_IBAT1U
328#define CFG_DBAT2L CFG_IBAT2L
329#define CFG_DBAT2U CFG_IBAT2U
330#define CFG_DBAT3L CFG_IBAT3L
331#define CFG_DBAT3U CFG_IBAT3U
332
333/*
334 * For booting Linux, the board info and command line data
335 * have to be in the first 8 MB of memory, since this is
336 * the maximum mapped by the Linux kernel during initialization.
337 */
338#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
339/*-----------------------------------------------------------------------
340 * FLASH organization
341 */
342#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
343#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
344
345#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
346#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
347
348/*-----------------------------------------------------------------------
349 * Cache Configuration
350 */
351#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
352#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
353# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
354#endif
355
356
357/*
358 * Internal Definitions
359 *
360 * Boot Flags
361 */
362#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
363#define BOOTFLAG_WARM 0x02 /* Software reboot */
364
365
366/* values according to the manual */
367
368#define CONFIG_DRAM_50MHZ 1
369#define CONFIG_SDRAM_50MHZ
370
371#undef NR_8259_INTS
372#define NR_8259_INTS 1
373
374
375#define CONFIG_DISK_SPINUP_TIME 1000000
376
377
378#endif /* __CONFIG_H */