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48c6f328 SL |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * T1024/T1023 RDB board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __T1024RDB_H | |
12 | #define __T1024RDB_H | |
13 | ||
14 | /* High Level Configuration Options */ | |
48c6f328 SL |
15 | #define CONFIG_BOOKE |
16 | #define CONFIG_E500 /* BOOKE e500 family */ | |
17 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
18 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
19 | #define CONFIG_MP /* support multiple processors */ | |
48c6f328 SL |
20 | #define CONFIG_ENABLE_36BIT_PHYS |
21 | ||
22 | #ifdef CONFIG_PHYS_64BIT | |
23 | #define CONFIG_ADDR_MAP 1 | |
24 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
25 | #endif | |
26 | ||
27 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
28 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
29 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
30 | ||
31 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
32 | #define CONFIG_ENV_OVERWRITE | |
33 | ||
ef6c55a2 AB |
34 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
35 | ||
48c6f328 | 36 | /* support deep sleep */ |
e8a7f1c3 | 37 | #ifdef CONFIG_PPC_T1024 |
48c6f328 | 38 | #define CONFIG_DEEP_SLEEP |
e8a7f1c3 | 39 | #endif |
f49b8c1b | 40 | #if defined(CONFIG_DEEP_SLEEP) |
f49b8c1b | 41 | #define CONFIG_BOARD_EARLY_INIT_F |
42 | #endif | |
48c6f328 SL |
43 | |
44 | #ifdef CONFIG_RAMBOOT_PBL | |
45 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg | |
48c6f328 SL |
46 | #define CONFIG_SPL_FLUSH_IMAGE |
47 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
48c6f328 | 48 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
f49b8c1b | 49 | #define CONFIG_SYS_TEXT_BASE 0x30001000 |
48c6f328 SL |
50 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
51 | #define CONFIG_SPL_PAD_TO 0x40000 | |
52 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
53 | #define RESET_VECTOR_OFFSET 0x27FFC | |
54 | #define BOOT_PAGE_OFFSET 0x27000 | |
55 | #ifdef CONFIG_SPL_BUILD | |
56 | #define CONFIG_SPL_SKIP_RELOCATE | |
57 | #define CONFIG_SPL_COMMON_INIT_DDR | |
58 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
59 | #define CONFIG_SYS_NO_FLASH | |
60 | #endif | |
61 | ||
62 | #ifdef CONFIG_NAND | |
48c6f328 | 63 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
f49b8c1b | 64 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
65 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
48c6f328 SL |
66 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
67 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
ec90ac73 ZQ |
68 | #if defined(CONFIG_T1024RDB) |
69 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg | |
70 | #elif defined(CONFIG_T1023RDB) | |
71 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg | |
72 | #endif | |
48c6f328 SL |
73 | #define CONFIG_SPL_NAND_BOOT |
74 | #endif | |
75 | ||
76 | #ifdef CONFIG_SPIFLASH | |
f49b8c1b | 77 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
48c6f328 SL |
78 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
79 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
f49b8c1b | 80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
48c6f328 SL |
82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
83 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
84 | #ifndef CONFIG_SPL_BUILD | |
85 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
86 | #endif | |
ec90ac73 ZQ |
87 | #if defined(CONFIG_T1024RDB) |
88 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg | |
89 | #elif defined(CONFIG_T1023RDB) | |
90 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg | |
91 | #endif | |
48c6f328 SL |
92 | #define CONFIG_SPL_SPI_BOOT |
93 | #endif | |
94 | ||
95 | #ifdef CONFIG_SDCARD | |
f49b8c1b | 96 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
48c6f328 SL |
97 | #define CONFIG_SPL_MMC_MINIMAL |
98 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
f49b8c1b | 99 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
100 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
48c6f328 SL |
101 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
102 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
103 | #ifndef CONFIG_SPL_BUILD | |
104 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
105 | #endif | |
ec90ac73 ZQ |
106 | #if defined(CONFIG_T1024RDB) |
107 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg | |
108 | #elif defined(CONFIG_T1023RDB) | |
109 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg | |
110 | #endif | |
48c6f328 SL |
111 | #define CONFIG_SPL_MMC_BOOT |
112 | #endif | |
113 | ||
114 | #endif /* CONFIG_RAMBOOT_PBL */ | |
115 | ||
116 | #ifndef CONFIG_SYS_TEXT_BASE | |
117 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
118 | #endif | |
119 | ||
120 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
121 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
122 | #endif | |
123 | ||
124 | #ifndef CONFIG_SYS_NO_FLASH | |
125 | #define CONFIG_FLASH_CFI_DRIVER | |
126 | #define CONFIG_SYS_FLASH_CFI | |
127 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
128 | #endif | |
129 | ||
130 | /* PCIe Boot - Master */ | |
131 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
132 | /* | |
133 | * for slave u-boot IMAGE instored in master memory space, | |
134 | * PHYS must be aligned based on the SIZE | |
135 | */ | |
136 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
137 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
138 | #ifdef CONFIG_PHYS_64BIT | |
139 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull | |
140 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
141 | #else | |
142 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 | |
143 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 | |
144 | #endif | |
145 | /* | |
146 | * for slave UCODE and ENV instored in master memory space, | |
147 | * PHYS must be aligned based on the SIZE | |
148 | */ | |
149 | #ifdef CONFIG_PHYS_64BIT | |
150 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull | |
151 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull | |
152 | #else | |
153 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 | |
154 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 | |
155 | #endif | |
156 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
157 | /* slave core release by master*/ | |
158 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
159 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
160 | ||
161 | /* PCIe Boot - Slave */ | |
162 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
163 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
164 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
165 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
166 | /* Set 1M boot space for PCIe boot */ | |
167 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
168 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
169 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
170 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
171 | #define CONFIG_SYS_NO_FLASH | |
172 | #endif | |
173 | ||
174 | #if defined(CONFIG_SPIFLASH) | |
175 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
176 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
177 | #define CONFIG_ENV_SPI_BUS 0 | |
178 | #define CONFIG_ENV_SPI_CS 0 | |
179 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
180 | #define CONFIG_ENV_SPI_MODE 0 | |
181 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
182 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
e8a7f1c3 | 183 | #if defined(CONFIG_T1024RDB) |
48c6f328 | 184 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
e8a7f1c3 SL |
185 | #elif defined(CONFIG_T1023RDB) |
186 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
187 | #endif | |
48c6f328 SL |
188 | #elif defined(CONFIG_SDCARD) |
189 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
190 | #define CONFIG_ENV_IS_IN_MMC | |
191 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
192 | #define CONFIG_ENV_SIZE 0x2000 | |
193 | #define CONFIG_ENV_OFFSET (512 * 0x800) | |
194 | #elif defined(CONFIG_NAND) | |
195 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
196 | #define CONFIG_ENV_IS_IN_NAND | |
197 | #define CONFIG_ENV_SIZE 0x2000 | |
e8a7f1c3 | 198 | #if defined(CONFIG_T1024RDB) |
48c6f328 | 199 | #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) |
e8a7f1c3 SL |
200 | #elif defined(CONFIG_T1023RDB) |
201 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
202 | #endif | |
48c6f328 SL |
203 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
204 | #define CONFIG_ENV_IS_IN_REMOTE | |
205 | #define CONFIG_ENV_ADDR 0xffe20000 | |
206 | #define CONFIG_ENV_SIZE 0x2000 | |
207 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
208 | #define CONFIG_ENV_SIZE 0x2000 | |
209 | #else | |
210 | #define CONFIG_ENV_IS_IN_FLASH | |
211 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
212 | #define CONFIG_ENV_SIZE 0x2000 | |
213 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
214 | #endif | |
215 | ||
48c6f328 SL |
216 | #ifndef __ASSEMBLY__ |
217 | unsigned long get_board_sys_clk(void); | |
218 | unsigned long get_board_ddr_clk(void); | |
219 | #endif | |
220 | ||
221 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
e8a7f1c3 | 222 | #define CONFIG_DDR_CLK_FREQ 100000000 |
48c6f328 SL |
223 | |
224 | /* | |
225 | * These can be toggled for performance analysis, otherwise use default. | |
226 | */ | |
227 | #define CONFIG_SYS_CACHE_STASHING | |
228 | #define CONFIG_BACKSIDE_L2_CACHE | |
229 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
230 | #define CONFIG_BTB /* toggle branch predition */ | |
231 | #define CONFIG_DDR_ECC | |
232 | #ifdef CONFIG_DDR_ECC | |
233 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
234 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
235 | #endif | |
236 | ||
237 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
238 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
239 | #define CONFIG_SYS_ALT_MEMTEST | |
240 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
241 | ||
242 | /* | |
243 | * Config the L3 Cache as L3 SRAM | |
244 | */ | |
245 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
246 | #define CONFIG_SYS_L3_SIZE (256 << 10) | |
247 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
248 | #ifdef CONFIG_RAMBOOT_PBL | |
249 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
250 | #endif | |
251 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
252 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
253 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
254 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
255 | ||
256 | #ifdef CONFIG_PHYS_64BIT | |
257 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
258 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
259 | #endif | |
260 | ||
261 | /* EEPROM */ | |
262 | #define CONFIG_ID_EEPROM | |
263 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
264 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
265 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
266 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
267 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
268 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
269 | ||
270 | /* | |
271 | * DDR Setup | |
272 | */ | |
273 | #define CONFIG_VERY_BIG_RAM | |
274 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
275 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
276 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
277 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
e8a7f1c3 SL |
278 | #define CONFIG_FSL_DDR_INTERACTIVE |
279 | #if defined(CONFIG_T1024RDB) | |
48c6f328 SL |
280 | #define CONFIG_DDR_SPD |
281 | #define CONFIG_SYS_FSL_DDR3 | |
48c6f328 SL |
282 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
283 | #define SPD_EEPROM_ADDRESS 0x51 | |
48c6f328 | 284 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
e8a7f1c3 SL |
285 | #elif defined(CONFIG_T1023RDB) |
286 | #define CONFIG_SYS_FSL_DDR4 | |
287 | #define CONFIG_SYS_DDR_RAW_TIMING | |
288 | #define CONFIG_SYS_SDRAM_SIZE 2048 | |
289 | #endif | |
48c6f328 SL |
290 | |
291 | /* | |
292 | * IFC Definitions | |
293 | */ | |
294 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
295 | #ifdef CONFIG_PHYS_64BIT | |
296 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
297 | #else | |
298 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
299 | #endif | |
300 | ||
301 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
302 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
303 | CSPR_PORT_SIZE_16 | \ | |
304 | CSPR_MSEL_NOR | \ | |
305 | CSPR_V) | |
306 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
307 | ||
308 | /* NOR Flash Timing Params */ | |
e8a7f1c3 | 309 | #if defined(CONFIG_T1024RDB) |
48c6f328 | 310 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
e8a7f1c3 | 311 | #elif defined(CONFIG_T1023RDB) |
ff7ea2d1 | 312 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ |
e8a7f1c3 SL |
313 | CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) |
314 | #endif | |
48c6f328 SL |
315 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
316 | FTIM0_NOR_TEADC(0x5) | \ | |
317 | FTIM0_NOR_TEAHC(0x5)) | |
318 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
319 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
320 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
321 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
322 | FTIM2_NOR_TCH(0x4) | \ | |
323 | FTIM2_NOR_TWPH(0x0E) | \ | |
324 | FTIM2_NOR_TWP(0x1c)) | |
325 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
326 | ||
327 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
328 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
329 | ||
330 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
331 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
332 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
333 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
334 | ||
335 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
336 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
337 | ||
e8a7f1c3 | 338 | #ifdef CONFIG_T1024RDB |
48c6f328 SL |
339 | /* CPLD on IFC */ |
340 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
341 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
342 | #define CONFIG_SYS_CSPR2_EXT (0xf) | |
343 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ | |
344 | | CSPR_PORT_SIZE_8 \ | |
345 | | CSPR_MSEL_GPCM \ | |
346 | | CSPR_V) | |
347 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
348 | #define CONFIG_SYS_CSOR2 0x0 | |
349 | ||
350 | /* CPLD Timing parameters for IFC CS2 */ | |
351 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
352 | FTIM0_GPCM_TEADC(0x0e) | \ | |
353 | FTIM0_GPCM_TEAHC(0x0e)) | |
354 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
355 | FTIM1_GPCM_TRAD(0x1f)) | |
356 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
357 | FTIM2_GPCM_TCH(0x8) | \ | |
358 | FTIM2_GPCM_TWP(0x1f)) | |
359 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
e8a7f1c3 | 360 | #endif |
48c6f328 SL |
361 | |
362 | /* NAND Flash on IFC */ | |
363 | #define CONFIG_NAND_FSL_IFC | |
364 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
365 | #ifdef CONFIG_PHYS_64BIT | |
366 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
367 | #else | |
368 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
369 | #endif | |
370 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
371 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
372 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
373 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
374 | | CSPR_V) | |
375 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
376 | ||
e8a7f1c3 | 377 | #if defined(CONFIG_T1024RDB) |
48c6f328 SL |
378 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
379 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
380 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
381 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
382 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
383 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
384 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
e8a7f1c3 SL |
385 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
386 | #elif defined(CONFIG_T1023RDB) | |
7842950f JS |
387 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
388 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
389 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
e8a7f1c3 SL |
390 | | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ |
391 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
392 | | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ | |
393 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
394 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
395 | #endif | |
48c6f328 SL |
396 | |
397 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
48c6f328 SL |
398 | /* ONFI NAND Flash mode0 Timing Params */ |
399 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
400 | FTIM0_NAND_TWP(0x18) | \ | |
401 | FTIM0_NAND_TWCHT(0x07) | \ | |
402 | FTIM0_NAND_TWH(0x0a)) | |
403 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
404 | FTIM1_NAND_TWBE(0x39) | \ | |
405 | FTIM1_NAND_TRR(0x0e) | \ | |
406 | FTIM1_NAND_TRP(0x18)) | |
407 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
408 | FTIM2_NAND_TREH(0x0a) | \ | |
409 | FTIM2_NAND_TWHRE(0x1e)) | |
410 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
411 | ||
412 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
413 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
414 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
48c6f328 SL |
415 | #define CONFIG_CMD_NAND |
416 | ||
48c6f328 SL |
417 | #if defined(CONFIG_NAND) |
418 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
419 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
420 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
421 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
422 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
423 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
424 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
425 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
426 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
427 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
428 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
429 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
430 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
431 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
432 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
433 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
434 | #else | |
435 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
436 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
437 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
438 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
439 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
440 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
441 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
442 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
443 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
444 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
445 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
446 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
447 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
448 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
449 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
450 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
451 | #endif | |
452 | ||
453 | #ifdef CONFIG_SPL_BUILD | |
454 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
455 | #else | |
456 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
457 | #endif | |
458 | ||
459 | #if defined(CONFIG_RAMBOOT_PBL) | |
460 | #define CONFIG_SYS_RAMBOOT | |
461 | #endif | |
462 | ||
463 | #define CONFIG_BOARD_EARLY_INIT_R | |
464 | #define CONFIG_MISC_INIT_R | |
465 | ||
466 | #define CONFIG_HWCONFIG | |
467 | ||
468 | /* define to use L1 as initial stack */ | |
469 | #define CONFIG_L1_INIT_RAM | |
470 | #define CONFIG_SYS_INIT_RAM_LOCK | |
471 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
472 | #ifdef CONFIG_PHYS_64BIT | |
473 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 474 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
48c6f328 SL |
475 | /* The assembler doesn't like typecast */ |
476 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
477 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
478 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
479 | #else | |
b3142e2c | 480 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ |
48c6f328 SL |
481 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
482 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
483 | #endif | |
484 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
485 | ||
486 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
487 | GENERATED_GBL_DATA_SIZE) | |
488 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
489 | ||
490 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) | |
491 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
492 | ||
493 | /* Serial Port */ | |
494 | #define CONFIG_CONS_INDEX 1 | |
48c6f328 SL |
495 | #define CONFIG_SYS_NS16550_SERIAL |
496 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
497 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
498 | ||
499 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
500 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
501 | ||
502 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
503 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
504 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
505 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
506 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
507 | ||
48c6f328 SL |
508 | /* Video */ |
509 | #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ | |
510 | #ifdef CONFIG_FSL_DIU_FB | |
511 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
48c6f328 SL |
512 | #define CONFIG_CMD_BMP |
513 | #define CONFIG_CFB_CONSOLE | |
514 | #define CONFIG_VIDEO_SW_CURSOR | |
515 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
516 | #define CONFIG_VIDEO_LOGO | |
517 | #define CONFIG_VIDEO_BMP_LOGO | |
518 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
519 | /* | |
520 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
521 | * disable empty flash sector detection, which is I/O-intensive. | |
522 | */ | |
523 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
524 | #endif | |
525 | ||
48c6f328 SL |
526 | /* I2C */ |
527 | #define CONFIG_SYS_I2C | |
528 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
529 | #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ | |
530 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
531 | #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ | |
532 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
533 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
534 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
535 | ||
ff7ea2d1 SL |
536 | #define I2C_PCA6408_BUS_NUM 1 |
537 | #define I2C_PCA6408_ADDR 0x20 | |
48c6f328 SL |
538 | |
539 | /* I2C bus multiplexer */ | |
540 | #define I2C_MUX_CH_DEFAULT 0x8 | |
541 | ||
542 | /* | |
543 | * RTC configuration | |
544 | */ | |
545 | #define RTC | |
546 | #define CONFIG_RTC_DS1337 1 | |
547 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
548 | ||
549 | /* | |
550 | * eSPI - Enhanced SPI | |
551 | */ | |
48c6f328 SL |
552 | #define CONFIG_SPI_FLASH_BAR |
553 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
554 | #define CONFIG_SF_DEFAULT_MODE 0 | |
555 | ||
556 | /* | |
557 | * General PCIe | |
558 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
559 | */ | |
560 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
b38eaec5 RD |
561 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
562 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
563 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
48c6f328 | 564 | #ifdef CONFIG_PPC_T1040 |
b38eaec5 | 565 | #define CONFIG_PCIE4 /* PCIE controller 4 */ |
48c6f328 SL |
566 | #endif |
567 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
568 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
569 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
570 | ||
571 | #ifdef CONFIG_PCI | |
572 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
573 | #ifdef CONFIG_PCIE1 | |
574 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
575 | #ifdef CONFIG_PHYS_64BIT | |
576 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
577 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
578 | #else | |
579 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
580 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
581 | #endif | |
582 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
583 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
584 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
585 | #ifdef CONFIG_PHYS_64BIT | |
586 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
587 | #else | |
588 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
589 | #endif | |
590 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
591 | #endif | |
592 | ||
593 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
594 | #ifdef CONFIG_PCIE2 | |
595 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
596 | #ifdef CONFIG_PHYS_64BIT | |
597 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
598 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
599 | #else | |
600 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 | |
601 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 | |
602 | #endif | |
603 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
604 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
605 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
606 | #ifdef CONFIG_PHYS_64BIT | |
607 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
608 | #else | |
609 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
610 | #endif | |
611 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
612 | #endif | |
613 | ||
614 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
615 | #ifdef CONFIG_PCIE3 | |
616 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
617 | #ifdef CONFIG_PHYS_64BIT | |
618 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
619 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
620 | #else | |
621 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 | |
622 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 | |
623 | #endif | |
624 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
625 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
626 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
627 | #ifdef CONFIG_PHYS_64BIT | |
628 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
629 | #else | |
630 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
631 | #endif | |
632 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
633 | #endif | |
634 | ||
635 | /* controller 4, Base address 203000, to be removed */ | |
636 | #ifdef CONFIG_PCIE4 | |
637 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
638 | #ifdef CONFIG_PHYS_64BIT | |
639 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
640 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
641 | #else | |
642 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 | |
643 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 | |
644 | #endif | |
645 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
646 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
647 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
648 | #ifdef CONFIG_PHYS_64BIT | |
649 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
650 | #else | |
651 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 | |
652 | #endif | |
653 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
654 | #endif | |
655 | ||
656 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
48c6f328 SL |
657 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
658 | #define CONFIG_DOS_PARTITION | |
659 | #endif /* CONFIG_PCI */ | |
660 | ||
661 | /* | |
662 | * USB | |
663 | */ | |
664 | #define CONFIG_HAS_FSL_DR_USB | |
665 | ||
666 | #ifdef CONFIG_HAS_FSL_DR_USB | |
667 | #define CONFIG_USB_EHCI | |
48c6f328 SL |
668 | #define CONFIG_USB_EHCI_FSL |
669 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
48c6f328 SL |
670 | #endif |
671 | ||
672 | /* | |
673 | * SDHC | |
674 | */ | |
675 | #define CONFIG_MMC | |
676 | #ifdef CONFIG_MMC | |
677 | #define CONFIG_FSL_ESDHC | |
678 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
48c6f328 | 679 | #define CONFIG_GENERIC_MMC |
48c6f328 SL |
680 | #define CONFIG_DOS_PARTITION |
681 | #endif | |
682 | ||
683 | /* Qman/Bman */ | |
684 | #ifndef CONFIG_NOBQFMAN | |
685 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
2a8b3422 | 686 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
48c6f328 SL |
687 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
688 | #ifdef CONFIG_PHYS_64BIT | |
689 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
690 | #else | |
691 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
692 | #endif | |
693 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
694 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
695 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
696 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
697 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
698 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
699 | CONFIG_SYS_BMAN_CENA_SIZE) | |
700 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
701 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
2a8b3422 | 702 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
48c6f328 SL |
703 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
704 | #ifdef CONFIG_PHYS_64BIT | |
705 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
706 | #else | |
707 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
708 | #endif | |
709 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
710 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
711 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
712 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
713 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
714 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
715 | CONFIG_SYS_QMAN_CENA_SIZE) | |
716 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
717 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
48c6f328 SL |
718 | |
719 | #define CONFIG_SYS_DPAA_FMAN | |
720 | ||
ff7ea2d1 | 721 | #ifdef CONFIG_T1024RDB |
48c6f328 SL |
722 | #define CONFIG_QE |
723 | #define CONFIG_U_QE | |
ff7ea2d1 | 724 | #endif |
48c6f328 SL |
725 | /* Default address of microcode for the Linux FMan driver */ |
726 | #if defined(CONFIG_SPIFLASH) | |
727 | /* | |
728 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
729 | * env, so we got 0x110000. | |
730 | */ | |
731 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
732 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 | |
733 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
734 | #elif defined(CONFIG_SDCARD) | |
735 | /* | |
736 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
737 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is | |
738 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). | |
739 | */ | |
740 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
741 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) | |
742 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
743 | #elif defined(CONFIG_NAND) | |
744 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
e8a7f1c3 | 745 | #if defined(CONFIG_T1024RDB) |
48c6f328 SL |
746 | #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
747 | #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
e8a7f1c3 SL |
748 | #elif defined(CONFIG_T1023RDB) |
749 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
750 | #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
751 | #endif | |
48c6f328 SL |
752 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
753 | /* | |
754 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
755 | * in two corenet boards, slave's ucode could be stored in master's memory | |
756 | * space, the address can be mapped from slave TLB->slave LAW-> | |
757 | * slave SRIO or PCIE outbound window->master inbound window-> | |
758 | * master LAW->the ucode address in master's memory space. | |
759 | */ | |
760 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
761 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 | |
762 | #else | |
763 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
764 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 | |
765 | #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 | |
766 | #endif | |
767 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
768 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
769 | #endif /* CONFIG_NOBQFMAN */ | |
770 | ||
771 | #ifdef CONFIG_SYS_DPAA_FMAN | |
772 | #define CONFIG_FMAN_ENET | |
773 | #define CONFIG_PHYLIB_10G | |
774 | #define CONFIG_PHY_REALTEK | |
e26416a3 | 775 | #define CONFIG_PHY_AQUANTIA |
e8a7f1c3 | 776 | #if defined(CONFIG_T1024RDB) |
48c6f328 SL |
777 | #define RGMII_PHY1_ADDR 0x2 |
778 | #define RGMII_PHY2_ADDR 0x6 | |
e8a7f1c3 | 779 | #define SGMII_AQR_PHY_ADDR 0x2 |
48c6f328 | 780 | #define FM1_10GEC1_PHY_ADDR 0x1 |
e8a7f1c3 SL |
781 | #elif defined(CONFIG_T1023RDB) |
782 | #define RGMII_PHY1_ADDR 0x1 | |
783 | #define SGMII_RTK_PHY_ADDR 0x3 | |
784 | #define SGMII_AQR_PHY_ADDR 0x2 | |
785 | #endif | |
48c6f328 SL |
786 | #endif |
787 | ||
788 | #ifdef CONFIG_FMAN_ENET | |
789 | #define CONFIG_MII /* MII PHY management */ | |
790 | #define CONFIG_ETHPRIME "FM1@DTSEC4" | |
791 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
792 | #endif | |
793 | ||
794 | /* | |
795 | * Dynamic MTD Partition support with mtdparts | |
796 | */ | |
797 | #ifndef CONFIG_SYS_NO_FLASH | |
798 | #define CONFIG_MTD_DEVICE | |
799 | #define CONFIG_MTD_PARTITIONS | |
800 | #define CONFIG_CMD_MTDPARTS | |
801 | #define CONFIG_FLASH_CFI_MTD | |
802 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ | |
803 | "spi0=spife110000.1" | |
804 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ | |
805 | "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ | |
806 | "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ | |
807 | "1m(uboot),5m(kernel),128k(dtb),-(user)" | |
808 | #endif | |
809 | ||
810 | /* | |
811 | * Environment | |
812 | */ | |
813 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
814 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
815 | ||
816 | /* | |
817 | * Command line configuration. | |
818 | */ | |
48c6f328 | 819 | #define CONFIG_CMD_DATE |
48c6f328 | 820 | #define CONFIG_CMD_EEPROM |
48c6f328 | 821 | #define CONFIG_CMD_ERRATA |
48c6f328 | 822 | #define CONFIG_CMD_IRQ |
48c6f328 | 823 | #define CONFIG_CMD_REGINFO |
48c6f328 SL |
824 | |
825 | #ifdef CONFIG_PCI | |
826 | #define CONFIG_CMD_PCI | |
48c6f328 SL |
827 | #endif |
828 | ||
829 | /* | |
830 | * Miscellaneous configurable options | |
831 | */ | |
832 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
833 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
834 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
835 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
48c6f328 SL |
836 | #ifdef CONFIG_CMD_KGDB |
837 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
838 | #else | |
839 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
840 | #endif | |
841 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
842 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
843 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
844 | ||
845 | /* | |
846 | * For booting Linux, the board info and command line data | |
847 | * have to be in the first 64 MB of memory, since this is | |
848 | * the maximum mapped by the Linux kernel during initialization. | |
849 | */ | |
850 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
851 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
852 | ||
853 | #ifdef CONFIG_CMD_KGDB | |
854 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
855 | #endif | |
856 | ||
857 | /* | |
858 | * Environment Configuration | |
859 | */ | |
860 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
861 | #define CONFIG_BOOTFILE "uImage" | |
e8a7f1c3 | 862 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
48c6f328 | 863 | #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ |
48c6f328 SL |
864 | #define CONFIG_BAUDRATE 115200 |
865 | #define __USB_PHY_TYPE utmi | |
866 | ||
867 | #ifdef CONFIG_PPC_T1024 | |
e8a7f1c3 SL |
868 | #define CONFIG_BOARDNAME t1024rdb |
869 | #define BANK_INTLV cs0_cs1 | |
48c6f328 | 870 | #else |
e8a7f1c3 SL |
871 | #define CONFIG_BOARDNAME t1023rdb |
872 | #define BANK_INTLV null | |
48c6f328 SL |
873 | #endif |
874 | ||
875 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
876 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
e8a7f1c3 | 877 | "bank_intlv=" __stringify(BANK_INTLV) "\0" \ |
48c6f328 SL |
878 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ |
879 | "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ | |
880 | "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ | |
881 | __stringify(CONFIG_BOARDNAME) ".dtb\0" \ | |
882 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
883 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
884 | "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ | |
885 | "netdev=eth0\0" \ | |
886 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
887 | "protect off $ubootaddr +$filesize && " \ | |
888 | "erase $ubootaddr +$filesize && " \ | |
889 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
890 | "protect on $ubootaddr +$filesize && " \ | |
891 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
892 | "consoledev=ttyS0\0" \ | |
893 | "ramdiskaddr=2000000\0" \ | |
b24a4f62 | 894 | "fdtaddr=1e00000\0" \ |
48c6f328 SL |
895 | "bdev=sda3\0" |
896 | ||
897 | #define CONFIG_LINUX \ | |
898 | "setenv bootargs root=/dev/ram rw " \ | |
899 | "console=$consoledev,$baudrate $othbootargs;" \ | |
900 | "setenv ramdiskaddr 0x02000000;" \ | |
901 | "setenv fdtaddr 0x00c00000;" \ | |
902 | "setenv loadaddr 0x1000000;" \ | |
903 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
904 | ||
48c6f328 SL |
905 | #define CONFIG_NFSBOOTCOMMAND \ |
906 | "setenv bootargs root=/dev/nfs rw " \ | |
907 | "nfsroot=$serverip:$rootpath " \ | |
908 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
909 | "console=$consoledev,$baudrate $othbootargs;" \ | |
910 | "tftp $loadaddr $bootfile;" \ | |
911 | "tftp $fdtaddr $fdtfile;" \ | |
912 | "bootm $loadaddr - $fdtaddr" | |
913 | ||
914 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
915 | ||
ef6c55a2 AB |
916 | /* Hash command with SHA acceleration supported in hardware */ |
917 | #ifdef CONFIG_FSL_CAAM | |
918 | #define CONFIG_CMD_HASH | |
919 | #define CONFIG_SHA_HW_ACCEL | |
920 | #endif | |
921 | ||
48c6f328 | 922 | #include <asm/fsl_secure_boot.h> |
ef6c55a2 | 923 | |
48c6f328 | 924 | #endif /* __T1024RDB_H */ |