projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d436078 | 1 | /* |
| c60dee03 | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
| 7d436078 PK |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef __CONFIG_H | |
| 24 | #define __CONFIG_H | |
| 25 | ||
| 26 | /* | |
| 27 | * T1040 QDS board configuration file | |
| 28 | */ | |
| 7d436078 PK |
29 | |
| 30 | #ifdef CONFIG_RAMBOOT_PBL | |
| 31 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
| 32 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
| e4536f8e MY |
33 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg |
| 34 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg | |
| 7d436078 PK |
35 | #endif |
| 36 | ||
| 37 | /* High Level Configuration Options */ | |
| 7d436078 | 38 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 7d436078 PK |
39 | #define CONFIG_MP /* support multiple processors */ |
| 40 | ||
| 48f6a9a2 TY |
41 | /* support deep sleep */ |
| 42 | #define CONFIG_DEEP_SLEEP | |
| 48f6a9a2 | 43 | |
| 7d436078 | 44 | #ifndef CONFIG_SYS_TEXT_BASE |
| e222b1f3 | 45 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| 7d436078 PK |
46 | #endif |
| 47 | ||
| 48 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 49 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 50 | #endif | |
| 51 | ||
| 52 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
| 51370d56 | 53 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
| 737537ef | 54 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| 7d436078 | 55 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| b38eaec5 RD |
56 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 57 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 58 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 59 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
| 7d436078 PK |
60 | |
| 61 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 62 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 63 | ||
| 7d436078 PK |
64 | #define CONFIG_ENV_OVERWRITE |
| 65 | ||
| e856bdcf | 66 | #ifndef CONFIG_MTD_NOR_FLASH |
| 7d436078 PK |
67 | #define CONFIG_ENV_IS_NOWHERE |
| 68 | #else | |
| 69 | #define CONFIG_FLASH_CFI_DRIVER | |
| 70 | #define CONFIG_SYS_FLASH_CFI | |
| 71 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 72 | #endif | |
| 73 | ||
| e856bdcf | 74 | #ifdef CONFIG_MTD_NOR_FLASH |
| 7d436078 PK |
75 | #if defined(CONFIG_SPIFLASH) |
| 76 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 77 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 78 | #define CONFIG_ENV_SPI_BUS 0 | |
| 79 | #define CONFIG_ENV_SPI_CS 0 | |
| 80 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 81 | #define CONFIG_ENV_SPI_MODE 0 | |
| 82 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 83 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 84 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 85 | #elif defined(CONFIG_SDCARD) | |
| 86 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 87 | #define CONFIG_ENV_IS_IN_MMC | |
| 88 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 89 | #define CONFIG_ENV_SIZE 0x2000 | |
| e222b1f3 | 90 | #define CONFIG_ENV_OFFSET (512 * 1658) |
| 7d436078 PK |
91 | #elif defined(CONFIG_NAND) |
| 92 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 93 | #define CONFIG_ENV_IS_IN_NAND | |
| 94 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| e222b1f3 | 95 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 7d436078 PK |
96 | #else |
| 97 | #define CONFIG_ENV_IS_IN_FLASH | |
| 98 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 99 | #define CONFIG_ENV_SIZE 0x2000 | |
| 100 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 101 | #endif | |
| e856bdcf | 102 | #else /* CONFIG_MTD_NOR_FLASH */ |
| 7d436078 PK |
103 | #define CONFIG_ENV_SIZE 0x2000 |
| 104 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 105 | #endif | |
| 106 | ||
| 107 | #ifndef __ASSEMBLY__ | |
| 108 | unsigned long get_board_sys_clk(void); | |
| 109 | unsigned long get_board_ddr_clk(void); | |
| 110 | #endif | |
| 111 | ||
| 112 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
| 113 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 114 | ||
| 115 | /* | |
| 116 | * These can be toggled for performance analysis, otherwise use default. | |
| 117 | */ | |
| 118 | #define CONFIG_SYS_CACHE_STASHING | |
| 119 | #define CONFIG_BACKSIDE_L2_CACHE | |
| 120 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
| 121 | #define CONFIG_BTB /* toggle branch predition */ | |
| 122 | #define CONFIG_DDR_ECC | |
| 123 | #ifdef CONFIG_DDR_ECC | |
| 124 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 125 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 126 | #endif | |
| 127 | ||
| 128 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 129 | ||
| 130 | #define CONFIG_ADDR_MAP | |
| 131 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
| 132 | ||
| 133 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 134 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 135 | #define CONFIG_SYS_ALT_MEMTEST | |
| 136 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 137 | ||
| 138 | /* | |
| 139 | * Config the L3 Cache as L3 SRAM | |
| 140 | */ | |
| 141 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
| 142 | ||
| 143 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
| 144 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
| 145 | ||
| 146 | /* EEPROM */ | |
| 147 | #define CONFIG_ID_EEPROM | |
| 148 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 149 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 150 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 151 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 152 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 153 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 154 | ||
| 155 | /* | |
| 156 | * DDR Setup | |
| 157 | */ | |
| 158 | #define CONFIG_VERY_BIG_RAM | |
| 159 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 160 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 161 | ||
| 7d436078 | 162 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 2eb3ac7f | 163 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 7d436078 PK |
164 | |
| 165 | #define CONFIG_DDR_SPD | |
| 1b2af9b4 | 166 | #define CONFIG_FSL_DDR_INTERACTIVE |
| 7d436078 PK |
167 | |
| 168 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 169 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 170 | ||
| 171 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
| 172 | ||
| 173 | /* | |
| 174 | * IFC Definitions | |
| 175 | */ | |
| 176 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
| 177 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 178 | ||
| 179 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
| 180 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 181 | + 0x8000000) | \ | |
| 182 | CSPR_PORT_SIZE_16 | \ | |
| 183 | CSPR_MSEL_NOR | \ | |
| 184 | CSPR_V) | |
| 185 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
| 186 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 187 | CSPR_PORT_SIZE_16 | \ | |
| 188 | CSPR_MSEL_NOR | \ | |
| 189 | CSPR_V) | |
| 190 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
| 377ffcfa SS |
191 | |
| 192 | /* | |
| 193 | * TDM Definition | |
| 194 | */ | |
| 195 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
| 196 | ||
| 7d436078 PK |
197 | /* NOR Flash Timing Params */ |
| 198 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
| 199 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 200 | FTIM0_NOR_TEADC(0x5) | \ | |
| 201 | FTIM0_NOR_TEAHC(0x5)) | |
| 202 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 203 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
| 204 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 205 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 206 | FTIM2_NOR_TCH(0x4) | \ | |
| 207 | FTIM2_NOR_TWPH(0x0E) | \ | |
| 208 | FTIM2_NOR_TWP(0x1c)) | |
| 209 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 210 | ||
| 211 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 212 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 213 | ||
| 214 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 215 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 216 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 217 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 218 | ||
| 219 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 220 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 221 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
| 222 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
| 223 | #define QIXIS_BASE 0xffdf0000 | |
| 224 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) | |
| 225 | #define QIXIS_LBMAP_SWITCH 0x06 | |
| 226 | #define QIXIS_LBMAP_MASK 0x0f | |
| 227 | #define QIXIS_LBMAP_SHIFT 0 | |
| 228 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 229 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 230 | #define QIXIS_RST_CTL_RESET 0x31 | |
| 231 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 232 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 233 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 8c618dd6 | 234 | #define QIXIS_RST_FORCE_MEM 0x01 |
| 7d436078 PK |
235 | |
| 236 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
| 237 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
| 238 | | CSPR_PORT_SIZE_8 \ | |
| 239 | | CSPR_MSEL_GPCM \ | |
| 240 | | CSPR_V) | |
| 241 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
| 242 | #define CONFIG_SYS_CSOR3 0x0 | |
| 243 | /* QIXIS Timing parameters for IFC CS3 */ | |
| 244 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 245 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 246 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 247 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
| 248 | FTIM1_GPCM_TRAD(0x3f)) | |
| 249 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| 562de1d6 | 250 | FTIM2_GPCM_TCH(0x8) | \ |
| 7d436078 PK |
251 | FTIM2_GPCM_TWP(0x1f)) |
| 252 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 253 | ||
| 254 | #define CONFIG_NAND_FSL_IFC | |
| 255 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 256 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
| 257 | ||
| 258 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
| 259 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 260 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
| 261 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
| 262 | | CSPR_V) | |
| 263 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 264 | ||
| 265 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 266 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 267 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 268 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 269 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 270 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
| 271 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
| 272 | ||
| 273 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 274 | ||
| 275 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 276 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
| 277 | FTIM0_NAND_TWP(0x18) | \ | |
| 278 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 279 | FTIM0_NAND_TWH(0x0a)) | |
| 280 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 281 | FTIM1_NAND_TWBE(0x39) | \ | |
| 282 | FTIM1_NAND_TRR(0x0e) | \ | |
| 283 | FTIM1_NAND_TRP(0x18)) | |
| 284 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 285 | FTIM2_NAND_TREH(0x0a) | \ | |
| 286 | FTIM2_NAND_TWHRE(0x1e)) | |
| 287 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 288 | ||
| 289 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
| 290 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 291 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 7d436078 PK |
292 | #define CONFIG_CMD_NAND |
| 293 | ||
| 294 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 295 | ||
| 296 | #if defined(CONFIG_NAND) | |
| 297 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 298 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 299 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 300 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 301 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 302 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 303 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 304 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 305 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 306 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 307 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 308 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 309 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 310 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 311 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 312 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 313 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 314 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| 315 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 316 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 317 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 318 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 319 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 320 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 321 | #else | |
| 322 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 323 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 324 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 325 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 326 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 327 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 328 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 329 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 330 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 331 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 332 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 333 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 334 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 335 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 336 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 337 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 338 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 339 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 340 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 341 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 342 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 343 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 344 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 345 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 346 | #endif | |
| 347 | ||
| 348 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
| 349 | ||
| 350 | #if defined(CONFIG_RAMBOOT_PBL) | |
| 351 | #define CONFIG_SYS_RAMBOOT | |
| 352 | #endif | |
| 353 | ||
| 354 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 355 | #define CONFIG_MISC_INIT_R | |
| 356 | ||
| 357 | #define CONFIG_HWCONFIG | |
| 358 | ||
| 359 | /* define to use L1 as initial stack */ | |
| 360 | #define CONFIG_L1_INIT_RAM | |
| 361 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 362 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
| 363 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| b3142e2c | 364 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
| 7d436078 PK |
365 | /* The assembler doesn't like typecast */ |
| 366 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 367 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 368 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 369 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 370 | ||
| 371 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 372 | GENERATED_GBL_DATA_SIZE) | |
| 373 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 374 | ||
| 9307cbab | 375 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 337b0c52 | 376 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| 7d436078 PK |
377 | |
| 378 | /* Serial Port - controlled on board with jumper J8 | |
| 379 | * open - index 2 | |
| 380 | * shorted - index 1 | |
| 381 | */ | |
| 382 | #define CONFIG_CONS_INDEX 1 | |
| 7d436078 PK |
383 | #define CONFIG_SYS_NS16550_SERIAL |
| 384 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 385 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
| 386 | ||
| 387 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 388 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 389 | ||
| 390 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
| 391 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
| 392 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
| 393 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
| 7d436078 | 394 | |
| 337b0c52 PJ |
395 | /* Video */ |
| 396 | #define CONFIG_FSL_DIU_FB | |
| 397 | #ifdef CONFIG_FSL_DIU_FB | |
| c53711bb | 398 | #define CONFIG_FSL_DIU_CH7301 |
| 337b0c52 | 399 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
| 337b0c52 | 400 | #define CONFIG_CMD_BMP |
| 337b0c52 PJ |
401 | #define CONFIG_VIDEO_LOGO |
| 402 | #define CONFIG_VIDEO_BMP_LOGO | |
| 403 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
| 404 | /* | |
| 405 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
| 406 | * disable empty flash sector detection, which is I/O-intensive. | |
| 407 | */ | |
| 408 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
| 409 | #endif | |
| 410 | ||
| 7d436078 PK |
411 | /* I2C */ |
| 412 | #define CONFIG_SYS_I2C | |
| 413 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
| 2eb3ac7f | 414 | #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ |
| b0d97cd2 SL |
415 | #define CONFIG_SYS_FSL_I2C2_SPEED 50000 |
| 416 | #define CONFIG_SYS_FSL_I2C3_SPEED 50000 | |
| 417 | #define CONFIG_SYS_FSL_I2C4_SPEED 50000 | |
| 7d436078 | 418 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 7d436078 | 419 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| b0d97cd2 SL |
420 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
| 421 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
| 7d436078 | 422 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| b0d97cd2 SL |
423 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
| 424 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
| 425 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
| 7d436078 PK |
426 | |
| 427 | #define I2C_MUX_PCA_ADDR 0x77 | |
| 428 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ | |
| 429 | ||
| 7d436078 PK |
430 | /* I2C bus multiplexer */ |
| 431 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| 337b0c52 PJ |
432 | #define I2C_MUX_CH_DIU 0xC |
| 433 | ||
| 434 | /* LDI/DVI Encoder for display */ | |
| 435 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
| 436 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 7d436078 PK |
437 | |
| 438 | /* | |
| 439 | * RTC configuration | |
| 440 | */ | |
| 441 | #define RTC | |
| 442 | #define CONFIG_RTC_DS3231 1 | |
| 443 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 444 | ||
| 445 | /* | |
| 446 | * eSPI - Enhanced SPI | |
| 447 | */ | |
| 7d436078 PK |
448 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 449 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 450 | ||
| 451 | /* | |
| 452 | * General PCI | |
| 453 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 454 | */ | |
| 455 | ||
| 456 | #ifdef CONFIG_PCI | |
| 457 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
| 458 | #ifdef CONFIG_PCIE1 | |
| 459 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 460 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
| 461 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 462 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
| 463 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
| 464 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 465 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
| 466 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 467 | #endif | |
| 468 | ||
| 469 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
| 470 | #ifdef CONFIG_PCIE2 | |
| 471 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
| 472 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
| 473 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
| 474 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 475 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
| 476 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 477 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
| 478 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 479 | #endif | |
| 480 | ||
| 481 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
| 482 | #ifdef CONFIG_PCIE3 | |
| 483 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
| 484 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 485 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 486 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 487 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
| 488 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 489 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
| 490 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 491 | #endif | |
| 492 | ||
| 493 | /* controller 4, Base address 203000 */ | |
| 494 | #ifdef CONFIG_PCIE4 | |
| 495 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
| 496 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
| 497 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
| 498 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
| 499 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
| 500 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
| 501 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
| 502 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
| 503 | #endif | |
| 504 | ||
| 7d436078 | 505 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 7d436078 PK |
506 | #endif /* CONFIG_PCI */ |
| 507 | ||
| 508 | /* SATA */ | |
| 509 | #define CONFIG_FSL_SATA_V2 | |
| 510 | #ifdef CONFIG_FSL_SATA_V2 | |
| 511 | #define CONFIG_LIBATA | |
| 512 | #define CONFIG_FSL_SATA | |
| 513 | ||
| 514 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 515 | #define CONFIG_SATA1 | |
| 516 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 517 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 518 | #define CONFIG_SATA2 | |
| 519 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 520 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 521 | ||
| 522 | #define CONFIG_LBA48 | |
| 523 | #define CONFIG_CMD_SATA | |
| 7d436078 PK |
524 | #endif |
| 525 | ||
| 526 | /* | |
| 527 | * USB | |
| 528 | */ | |
| 529 | #define CONFIG_HAS_FSL_DR_USB | |
| 530 | ||
| 531 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 532 | #define CONFIG_USB_EHCI | |
| 533 | ||
| 534 | #ifdef CONFIG_USB_EHCI | |
| 7d436078 PK |
535 | #define CONFIG_USB_EHCI_FSL |
| 536 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 7d436078 PK |
537 | #endif |
| 538 | #endif | |
| 539 | ||
| 7d436078 PK |
540 | #ifdef CONFIG_MMC |
| 541 | #define CONFIG_FSL_ESDHC | |
| 12486f38 | 542 | #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 7d436078 | 543 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| fa1e035e | 544 | #define CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 7d436078 PK |
545 | #endif |
| 546 | ||
| 547 | /* Qman/Bman */ | |
| 548 | #ifndef CONFIG_NOBQFMAN | |
| 549 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
| 2a8b3422 | 550 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
| 7d436078 PK |
551 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 552 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
| 553 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
554 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 555 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
| 556 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
| 557 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 558 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
| 559 | CONFIG_SYS_BMAN_CENA_SIZE) | |
| 560 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
| 561 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
| 2a8b3422 | 562 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
| 7d436078 PK |
563 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 564 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
| 565 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
| 3fa66db4 JL |
566 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 567 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
| 568 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
| 569 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 570 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
| 571 | CONFIG_SYS_QMAN_CENA_SIZE) | |
| 572 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
| 573 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
| 7d436078 PK |
574 | |
| 575 | #define CONFIG_SYS_DPAA_FMAN | |
| 576 | #define CONFIG_SYS_DPAA_PME | |
| 577 | ||
| 6259e291 ZQ |
578 | #define CONFIG_QE |
| 579 | #define CONFIG_U_QE | |
| 7d436078 PK |
580 | /* Default address of microcode for the Linux Fman driver */ |
| 581 | #if defined(CONFIG_SPIFLASH) | |
| 582 | /* | |
| 583 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
| 584 | * env, so we got 0x110000. | |
| 585 | */ | |
| 586 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
| dcf1d774 | 587 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
| 7d436078 PK |
588 | #elif defined(CONFIG_SDCARD) |
| 589 | /* | |
| 590 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| e222b1f3 PK |
591 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
| 592 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
| 7d436078 PK |
593 | */ |
| 594 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
| dcf1d774 | 595 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
| 7d436078 PK |
596 | #elif defined(CONFIG_NAND) |
| 597 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
| dcf1d774 | 598 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
| 7d436078 PK |
599 | #else |
| 600 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
| dcf1d774 | 601 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
| 6259e291 | 602 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
| 7d436078 PK |
603 | #endif |
| 604 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
| 605 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 606 | #endif /* CONFIG_NOBQFMAN */ | |
| 607 | ||
| 608 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 609 | #define CONFIG_FMAN_ENET | |
| 610 | #define CONFIG_PHYLIB_10G | |
| 611 | #define CONFIG_PHY_VITESSE | |
| 612 | #define CONFIG_PHY_REALTEK | |
| 613 | #define CONFIG_PHY_TERANETICS | |
| 614 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
| 615 | #define SGMII_CARD_PORT2_PHY_ADDR 0x10 | |
| 616 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
| 617 | #define SGMII_CARD_PORT4_PHY_ADDR 0x11 | |
| 618 | #endif | |
| 619 | ||
| 620 | #ifdef CONFIG_FMAN_ENET | |
| 5b7672fc PK |
621 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 |
| 622 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 | |
| 7d436078 PK |
623 | |
| 624 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
| 625 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
| 626 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
| 627 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
| 628 | ||
| 629 | #define CONFIG_MII /* MII PHY management */ | |
| 630 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
| 631 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 632 | #endif | |
| 633 | ||
| a83fccc2 CC |
634 | /* Enable VSC9953 L2 Switch driver */ |
| 635 | #define CONFIG_VSC9953 | |
| 4c1ceb69 | 636 | #define CONFIG_CMD_ETHSW |
| a83fccc2 CC |
637 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 |
| 638 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 | |
| 639 | ||
| 68b74739 PK |
640 | /* |
| 641 | * Dynamic MTD Partition support with mtdparts | |
| 642 | */ | |
| e856bdcf | 643 | #ifdef CONFIG_MTD_NOR_FLASH |
| 68b74739 PK |
644 | #define CONFIG_MTD_DEVICE |
| 645 | #define CONFIG_MTD_PARTITIONS | |
| 646 | #define CONFIG_CMD_MTDPARTS | |
| 647 | #define CONFIG_FLASH_CFI_MTD | |
| 648 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ | |
| 649 | "spi0=spife110000.0" | |
| 650 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ | |
| 651 | "128k(dtb),96m(fs),-(user);"\ | |
| 652 | "fff800000.flash:2m(uboot),9m(kernel),"\ | |
| 653 | "128k(dtb),96m(fs),-(user);spife110000.0:" \ | |
| 654 | "2m(uboot),9m(kernel),128k(dtb),-(user)" | |
| 655 | #endif | |
| 656 | ||
| 7d436078 PK |
657 | /* |
| 658 | * Environment | |
| 659 | */ | |
| 660 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 661 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 662 | ||
| 663 | /* | |
| 664 | * Command line configuration. | |
| 665 | */ | |
| 7d436078 | 666 | #define CONFIG_CMD_DATE |
| 7d436078 | 667 | #define CONFIG_CMD_EEPROM |
| 7d436078 | 668 | #define CONFIG_CMD_ERRATA |
| 7d436078 | 669 | #define CONFIG_CMD_IRQ |
| 7d436078 | 670 | #define CONFIG_CMD_REGINFO |
| 7d436078 PK |
671 | |
| 672 | #ifdef CONFIG_PCI | |
| 673 | #define CONFIG_CMD_PCI | |
| 7d436078 PK |
674 | #endif |
| 675 | ||
| 737537ef RG |
676 | /* Hash command with SHA acceleration supported in hardware */ |
| 677 | #ifdef CONFIG_FSL_CAAM | |
| 678 | #define CONFIG_CMD_HASH | |
| 679 | #define CONFIG_SHA_HW_ACCEL | |
| 680 | #endif | |
| 681 | ||
| 7d436078 PK |
682 | /* |
| 683 | * Miscellaneous configurable options | |
| 684 | */ | |
| 685 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 686 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 687 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| 688 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 7d436078 PK |
689 | #ifdef CONFIG_CMD_KGDB |
| 690 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 691 | #else | |
| 692 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 693 | #endif | |
| 694 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 695 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 696 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 7d436078 PK |
697 | |
| 698 | /* | |
| 699 | * For booting Linux, the board info and command line data | |
| 700 | * have to be in the first 64 MB of memory, since this is | |
| 701 | * the maximum mapped by the Linux kernel during initialization. | |
| 702 | */ | |
| 703 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
| 704 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 705 | ||
| 706 | #ifdef CONFIG_CMD_KGDB | |
| 707 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 7d436078 PK |
708 | #endif |
| 709 | ||
| 710 | /* | |
| 711 | * Environment Configuration | |
| 712 | */ | |
| 713 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 714 | #define CONFIG_BOOTFILE "uImage" | |
| 715 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
| 716 | ||
| 717 | /* default location for tftp and bootm */ | |
| 718 | #define CONFIG_LOADADDR 1000000 | |
| 719 | ||
| 7d436078 PK |
720 | |
| 721 | #define CONFIG_BAUDRATE 115200 | |
| 722 | ||
| 723 | #define __USB_PHY_TYPE utmi | |
| 724 | ||
| 725 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 1b2af9b4 | 726 | "hwconfig=fsl_ddr:bank_intlv=auto;" \ |
| 7d436078 PK |
727 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
| 728 | "netdev=eth0\0" \ | |
| 337b0c52 | 729 | "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ |
| 7d436078 PK |
730 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 731 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 732 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
| 733 | "protect off $ubootaddr +$filesize && " \ | |
| 734 | "erase $ubootaddr +$filesize && " \ | |
| 735 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 736 | "protect on $ubootaddr +$filesize && " \ | |
| 737 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 738 | "consoledev=ttyS0\0" \ | |
| 739 | "ramdiskaddr=2000000\0" \ | |
| 740 | "ramdiskfile=t1040qds/ramdisk.uboot\0" \ | |
| b24a4f62 | 741 | "fdtaddr=1e00000\0" \ |
| 7d436078 | 742 | "fdtfile=t1040qds/t1040qds.dtb\0" \ |
| 3246584d | 743 | "bdev=sda3\0" |
| 7d436078 PK |
744 | |
| 745 | #define CONFIG_LINUX \ | |
| 746 | "setenv bootargs root=/dev/ram rw " \ | |
| 747 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 748 | "setenv ramdiskaddr 0x02000000;" \ | |
| 749 | "setenv fdtaddr 0x00c00000;" \ | |
| 750 | "setenv loadaddr 0x1000000;" \ | |
| 751 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 752 | ||
| 753 | #define CONFIG_HDBOOT \ | |
| 754 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 755 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 756 | "tftp $loadaddr $bootfile;" \ | |
| 757 | "tftp $fdtaddr $fdtfile;" \ | |
| 758 | "bootm $loadaddr - $fdtaddr" | |
| 759 | ||
| 760 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 761 | "setenv bootargs root=/dev/nfs rw " \ | |
| 762 | "nfsroot=$serverip:$rootpath " \ | |
| 763 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 764 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 765 | "tftp $loadaddr $bootfile;" \ | |
| 766 | "tftp $fdtaddr $fdtfile;" \ | |
| 767 | "bootm $loadaddr - $fdtaddr" | |
| 768 | ||
| 769 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 770 | "setenv bootargs root=/dev/ram rw " \ | |
| 771 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 772 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 773 | "tftp $loadaddr $bootfile;" \ | |
| 774 | "tftp $fdtaddr $fdtfile;" \ | |
| 775 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 776 | ||
| 777 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
| 778 | ||
| 7d436078 | 779 | #include <asm/fsl_secure_boot.h> |
| ef6c55a2 | 780 | |
| 7d436078 | 781 | #endif /* __CONFIG_H */ |