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062ef1a6 | 1 | /* |
f4c3917a | 2 | + * Copyright 2014 Freescale Semiconductor, Inc. |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
062ef1a6 PJ |
6 | |
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | /* | |
f4c3917a | 11 | * T104x RDB board configuration file |
062ef1a6 | 12 | */ |
9f074e67 PK |
13 | #include <asm/config_mpc85xx.h> |
14 | ||
062ef1a6 | 15 | #ifdef CONFIG_RAMBOOT_PBL |
aa36c84e SG |
16 | |
17 | #ifndef CONFIG_SECURE_BOOT | |
18c01445 | 18 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
aa36c84e SG |
19 | #else |
20 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
21 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg | |
22 | #endif | |
23 | ||
18c01445 PK |
24 | #define CONFIG_SPL_FLUSH_IMAGE |
25 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
ce249d95 | 26 | #define CONFIG_SYS_TEXT_BASE 0x30001000 |
18c01445 PK |
27 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
28 | #define CONFIG_SPL_PAD_TO 0x40000 | |
29 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
30 | #ifdef CONFIG_SPL_BUILD | |
31 | #define CONFIG_SPL_SKIP_RELOCATE | |
32 | #define CONFIG_SPL_COMMON_INIT_DDR | |
33 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
18c01445 PK |
34 | #endif |
35 | #define RESET_VECTOR_OFFSET 0x27FFC | |
36 | #define BOOT_PAGE_OFFSET 0x27000 | |
37 | ||
38 | #ifdef CONFIG_NAND | |
aa36c84e SG |
39 | #ifdef CONFIG_SECURE_BOOT |
40 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
41 | /* | |
42 | * HDR would be appended at end of image and copied to DDR along | |
43 | * with U-Boot image. | |
44 | */ | |
45 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ | |
46 | CONFIG_U_BOOT_HDR_SIZE) | |
47 | #else | |
18c01445 | 48 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
aa36c84e | 49 | #endif |
ce249d95 TY |
50 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
18c01445 PK |
52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
6fcddd09 | 54 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
55 | #define CONFIG_SYS_FSL_PBL_RCW \ |
56 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg | |
57 | #endif | |
55ed8ae3 | 58 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
59 | #define CONFIG_SYS_FSL_PBL_RCW \ |
60 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | |
61 | #endif | |
0167369c | 62 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
63 | #define CONFIG_SYS_FSL_PBL_RCW \ |
64 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg | |
65 | #endif | |
a016735c | 66 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
67 | #define CONFIG_SYS_FSL_PBL_RCW \ |
68 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | |
69 | #endif | |
319ed24a | 70 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
71 | #define CONFIG_SYS_FSL_PBL_RCW \ |
72 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | |
73 | #endif | |
18c01445 PK |
74 | #define CONFIG_SPL_NAND_BOOT |
75 | #endif | |
76 | ||
77 | #ifdef CONFIG_SPIFLASH | |
ce249d95 | 78 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 PK |
79 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
ce249d95 TY |
81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
18c01445 PK |
83 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
84 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
85 | #ifndef CONFIG_SPL_BUILD | |
86 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
87 | #endif | |
6fcddd09 | 88 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
89 | #define CONFIG_SYS_FSL_PBL_RCW \ |
90 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg | |
91 | #endif | |
55ed8ae3 | 92 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
93 | #define CONFIG_SYS_FSL_PBL_RCW \ |
94 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | |
95 | #endif | |
0167369c | 96 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
97 | #define CONFIG_SYS_FSL_PBL_RCW \ |
98 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg | |
99 | #endif | |
a016735c | 100 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
101 | #define CONFIG_SYS_FSL_PBL_RCW \ |
102 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | |
103 | #endif | |
319ed24a | 104 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
105 | #define CONFIG_SYS_FSL_PBL_RCW \ |
106 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | |
107 | #endif | |
18c01445 PK |
108 | #define CONFIG_SPL_SPI_BOOT |
109 | #endif | |
110 | ||
111 | #ifdef CONFIG_SDCARD | |
ce249d95 | 112 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 PK |
113 | #define CONFIG_SPL_MMC_MINIMAL |
114 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
ce249d95 TY |
115 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
116 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
18c01445 PK |
117 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
118 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
119 | #ifndef CONFIG_SPL_BUILD | |
120 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
121 | #endif | |
6fcddd09 | 122 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
123 | #define CONFIG_SYS_FSL_PBL_RCW \ |
124 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg | |
125 | #endif | |
55ed8ae3 | 126 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
127 | #define CONFIG_SYS_FSL_PBL_RCW \ |
128 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | |
129 | #endif | |
0167369c | 130 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
131 | #define CONFIG_SYS_FSL_PBL_RCW \ |
132 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg | |
133 | #endif | |
a016735c | 134 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
135 | #define CONFIG_SYS_FSL_PBL_RCW \ |
136 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | |
137 | #endif | |
319ed24a | 138 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
139 | #define CONFIG_SYS_FSL_PBL_RCW \ |
140 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | |
141 | #endif | |
18c01445 PK |
142 | #define CONFIG_SPL_MMC_BOOT |
143 | #endif | |
144 | ||
062ef1a6 PJ |
145 | #endif |
146 | ||
147 | /* High Level Configuration Options */ | |
062ef1a6 | 148 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
062ef1a6 PJ |
149 | #define CONFIG_MP /* support multiple processors */ |
150 | ||
5303a3de TY |
151 | /* support deep sleep */ |
152 | #define CONFIG_DEEP_SLEEP | |
5303a3de | 153 | |
062ef1a6 | 154 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 155 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
062ef1a6 PJ |
156 | #endif |
157 | ||
158 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
159 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
160 | #endif | |
161 | ||
162 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 163 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
062ef1a6 | 164 | #define CONFIG_PCI_INDIRECT_BRIDGE |
b38eaec5 RD |
165 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
166 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
167 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
168 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
062ef1a6 PJ |
169 | |
170 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
171 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
172 | ||
062ef1a6 PJ |
173 | #define CONFIG_ENV_OVERWRITE |
174 | ||
e856bdcf | 175 | #ifdef CONFIG_MTD_NOR_FLASH |
062ef1a6 PJ |
176 | #define CONFIG_FLASH_CFI_DRIVER |
177 | #define CONFIG_SYS_FLASH_CFI | |
178 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
179 | #endif | |
180 | ||
062ef1a6 PJ |
181 | #if defined(CONFIG_SPIFLASH) |
182 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
062ef1a6 PJ |
183 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
184 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
185 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
186 | #elif defined(CONFIG_SDCARD) | |
187 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
062ef1a6 PJ |
188 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
189 | #define CONFIG_ENV_SIZE 0x2000 | |
18c01445 | 190 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
062ef1a6 | 191 | #elif defined(CONFIG_NAND) |
aa36c84e SG |
192 | #ifdef CONFIG_SECURE_BOOT |
193 | #define CONFIG_RAMBOOT_NAND | |
194 | #define CONFIG_BOOTSCRIPT_COPY_RAM | |
195 | #endif | |
062ef1a6 | 196 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
18c01445 | 197 | #define CONFIG_ENV_SIZE 0x2000 |
e222b1f3 | 198 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
062ef1a6 | 199 | #else |
062ef1a6 PJ |
200 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
201 | #define CONFIG_ENV_SIZE 0x2000 | |
202 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
203 | #endif | |
062ef1a6 PJ |
204 | |
205 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
206 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
207 | ||
208 | /* | |
209 | * These can be toggled for performance analysis, otherwise use default. | |
210 | */ | |
211 | #define CONFIG_SYS_CACHE_STASHING | |
212 | #define CONFIG_BACKSIDE_L2_CACHE | |
213 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
214 | #define CONFIG_BTB /* toggle branch predition */ | |
215 | #define CONFIG_DDR_ECC | |
216 | #ifdef CONFIG_DDR_ECC | |
217 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
218 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
219 | #endif | |
220 | ||
221 | #define CONFIG_ENABLE_36BIT_PHYS | |
222 | ||
223 | #define CONFIG_ADDR_MAP | |
224 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
225 | ||
226 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
227 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
228 | #define CONFIG_SYS_ALT_MEMTEST | |
229 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
230 | ||
231 | /* | |
232 | * Config the L3 Cache as L3 SRAM | |
233 | */ | |
234 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
aa36c84e SG |
235 | /* |
236 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence | |
237 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address | |
238 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. | |
239 | */ | |
240 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 | |
18c01445 | 241 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
aa36c84e | 242 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
18c01445 PK |
243 | #ifdef CONFIG_RAMBOOT_PBL |
244 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
245 | #endif | |
246 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
247 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
248 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
249 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
062ef1a6 PJ |
250 | |
251 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
252 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
253 | ||
254 | /* | |
255 | * DDR Setup | |
256 | */ | |
257 | #define CONFIG_VERY_BIG_RAM | |
258 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
259 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
260 | ||
062ef1a6 | 261 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
96ac18c9 | 262 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
062ef1a6 PJ |
263 | |
264 | #define CONFIG_DDR_SPD | |
062ef1a6 PJ |
265 | |
266 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
267 | #define SPD_EEPROM_ADDRESS 0x51 | |
268 | ||
269 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
270 | ||
271 | /* | |
272 | * IFC Definitions | |
273 | */ | |
274 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
275 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
276 | ||
277 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
278 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
279 | CSPR_PORT_SIZE_16 | \ | |
280 | CSPR_MSEL_NOR | \ | |
281 | CSPR_V) | |
282 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
377ffcfa SS |
283 | |
284 | /* | |
285 | * TDM Definition | |
286 | */ | |
287 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
288 | ||
062ef1a6 PJ |
289 | /* NOR Flash Timing Params */ |
290 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
291 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
292 | FTIM0_NOR_TEADC(0x5) | \ | |
293 | FTIM0_NOR_TEAHC(0x5)) | |
294 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
295 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
296 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
297 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
298 | FTIM2_NOR_TCH(0x4) | \ | |
299 | FTIM2_NOR_TWPH(0x0E) | \ | |
300 | FTIM2_NOR_TWP(0x1c)) | |
301 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
302 | ||
303 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
304 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
305 | ||
306 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
307 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
308 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
309 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
310 | ||
311 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
312 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
313 | ||
314 | /* CPLD on IFC */ | |
55153d6c PK |
315 | #define CPLD_LBMAP_MASK 0x3F |
316 | #define CPLD_BANK_SEL_MASK 0x07 | |
317 | #define CPLD_BANK_OVERRIDE 0x40 | |
318 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ | |
319 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ | |
320 | #define CPLD_LBMAP_RESET 0xFF | |
321 | #define CPLD_LBMAP_SHIFT 0x03 | |
4b6067ae | 322 | |
55ed8ae3 | 323 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
cf8ddacf | 324 | #define CPLD_DIU_SEL_DFP 0x80 |
319ed24a | 325 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
326 | #define CPLD_DIU_SEL_DFP 0xc0 |
327 | #endif | |
328 | ||
a016735c | 329 | #if defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae PJ |
330 | #define CPLD_INT_MASK_ALL 0xFF |
331 | #define CPLD_INT_MASK_THERM 0x80 | |
332 | #define CPLD_INT_MASK_DVI_DFP 0x40 | |
333 | #define CPLD_INT_MASK_QSGMII1 0x20 | |
334 | #define CPLD_INT_MASK_QSGMII2 0x10 | |
335 | #define CPLD_INT_MASK_SGMI1 0x08 | |
336 | #define CPLD_INT_MASK_SGMI2 0x04 | |
337 | #define CPLD_INT_MASK_TDMR1 0x02 | |
338 | #define CPLD_INT_MASK_TDMR2 0x01 | |
cf8ddacf | 339 | #endif |
55153d6c | 340 | |
062ef1a6 PJ |
341 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
342 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
9b444be3 | 343 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
062ef1a6 PJ |
344 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
345 | | CSPR_PORT_SIZE_8 \ | |
346 | | CSPR_MSEL_GPCM \ | |
347 | | CSPR_V) | |
348 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
349 | #define CONFIG_SYS_CSOR2 0x0 | |
350 | /* CPLD Timing parameters for IFC CS2 */ | |
351 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
352 | FTIM0_GPCM_TEADC(0x0e) | \ | |
353 | FTIM0_GPCM_TEAHC(0x0e)) | |
354 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
355 | FTIM1_GPCM_TRAD(0x1f)) | |
356 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 357 | FTIM2_GPCM_TCH(0x8) | \ |
062ef1a6 PJ |
358 | FTIM2_GPCM_TWP(0x1f)) |
359 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
360 | ||
361 | /* NAND Flash on IFC */ | |
362 | #define CONFIG_NAND_FSL_IFC | |
363 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
364 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
365 | ||
366 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
367 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
368 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
369 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
370 | | CSPR_V) | |
371 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
372 | ||
373 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
374 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
375 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
376 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
377 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
378 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
379 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
380 | ||
381 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
382 | ||
383 | /* ONFI NAND Flash mode0 Timing Params */ | |
384 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
385 | FTIM0_NAND_TWP(0x18) | \ | |
386 | FTIM0_NAND_TWCHT(0x07) | \ | |
387 | FTIM0_NAND_TWH(0x0a)) | |
388 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
389 | FTIM1_NAND_TWBE(0x39) | \ | |
390 | FTIM1_NAND_TRR(0x0e) | \ | |
391 | FTIM1_NAND_TRP(0x18)) | |
392 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
393 | FTIM2_NAND_TREH(0x0a) | \ | |
394 | FTIM2_NAND_TWHRE(0x1e)) | |
395 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
396 | ||
397 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
398 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
399 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
062ef1a6 PJ |
400 | |
401 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
402 | ||
403 | #if defined(CONFIG_NAND) | |
404 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
405 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
406 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
407 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
408 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
409 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
410 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
411 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
412 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
413 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
414 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
415 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
416 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
417 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
418 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
419 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
420 | #else | |
421 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
422 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
423 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
424 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
425 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
426 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
427 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
428 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
429 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
430 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
431 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
432 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
433 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
434 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
435 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
436 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
437 | #endif | |
438 | ||
18c01445 PK |
439 | #ifdef CONFIG_SPL_BUILD |
440 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
441 | #else | |
442 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
443 | #endif | |
062ef1a6 PJ |
444 | |
445 | #if defined(CONFIG_RAMBOOT_PBL) | |
446 | #define CONFIG_SYS_RAMBOOT | |
447 | #endif | |
448 | ||
9f074e67 PK |
449 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
450 | #if defined(CONFIG_NAND) | |
451 | #define CONFIG_A008044_WORKAROUND | |
452 | #endif | |
453 | #endif | |
454 | ||
062ef1a6 PJ |
455 | #define CONFIG_BOARD_EARLY_INIT_R |
456 | #define CONFIG_MISC_INIT_R | |
457 | ||
458 | #define CONFIG_HWCONFIG | |
459 | ||
460 | /* define to use L1 as initial stack */ | |
461 | #define CONFIG_L1_INIT_RAM | |
462 | #define CONFIG_SYS_INIT_RAM_LOCK | |
463 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
464 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 465 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
062ef1a6 PJ |
466 | /* The assembler doesn't like typecast */ |
467 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
468 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
469 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
470 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
471 | ||
472 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
473 | GENERATED_GBL_DATA_SIZE) | |
474 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
475 | ||
9307cbab | 476 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
062ef1a6 PJ |
477 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
478 | ||
479 | /* Serial Port - controlled on board with jumper J8 | |
480 | * open - index 2 | |
481 | * shorted - index 1 | |
482 | */ | |
483 | #define CONFIG_CONS_INDEX 1 | |
062ef1a6 PJ |
484 | #define CONFIG_SYS_NS16550_SERIAL |
485 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
486 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
487 | ||
488 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
489 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
490 | ||
491 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
492 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
493 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
494 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
062ef1a6 | 495 | |
319ed24a | 496 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
cf8ddacf JJ |
497 | /* Video */ |
498 | #define CONFIG_FSL_DIU_FB | |
499 | ||
500 | #ifdef CONFIG_FSL_DIU_FB | |
501 | #define CONFIG_FSL_DIU_CH7301 | |
502 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
cf8ddacf JJ |
503 | #define CONFIG_VIDEO_LOGO |
504 | #define CONFIG_VIDEO_BMP_LOGO | |
505 | #endif | |
506 | #endif | |
507 | ||
062ef1a6 PJ |
508 | /* I2C */ |
509 | #define CONFIG_SYS_I2C | |
510 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
511 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
b0d97cd2 SL |
512 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
513 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 | |
514 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 | |
062ef1a6 | 515 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
062ef1a6 | 516 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
b0d97cd2 SL |
517 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
518 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
062ef1a6 | 519 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
b0d97cd2 SL |
520 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
521 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
522 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
062ef1a6 PJ |
523 | |
524 | /* I2C bus multiplexer */ | |
525 | #define I2C_MUX_PCA_ADDR 0x70 | |
526 | #define I2C_MUX_CH_DEFAULT 0x8 | |
f4c3917a | 527 | |
78e56995 YS |
528 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
529 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
530 | defined(CONFIG_TARGET_T1042D4RDB) | |
cf8ddacf JJ |
531 | /* LDI/DVI Encoder for display */ |
532 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
533 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
534 | ||
f4c3917a | 535 | /* |
536 | * RTC configuration | |
537 | */ | |
538 | #define RTC | |
539 | #define CONFIG_RTC_DS1337 1 | |
540 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
062ef1a6 | 541 | |
f4c3917a | 542 | /*DVI encoder*/ |
543 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 | |
544 | #endif | |
062ef1a6 PJ |
545 | |
546 | /* | |
547 | * eSPI - Enhanced SPI | |
548 | */ | |
7172de33 | 549 | #define CONFIG_SPI_FLASH_BAR |
062ef1a6 PJ |
550 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
551 | #define CONFIG_SF_DEFAULT_MODE 0 | |
9b444be3 PJ |
552 | #define CONFIG_ENV_SPI_BUS 0 |
553 | #define CONFIG_ENV_SPI_CS 0 | |
554 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
555 | #define CONFIG_ENV_SPI_MODE 0 | |
062ef1a6 PJ |
556 | |
557 | /* | |
558 | * General PCI | |
559 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
560 | */ | |
561 | ||
562 | #ifdef CONFIG_PCI | |
563 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
564 | #ifdef CONFIG_PCIE1 | |
565 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
566 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
567 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
568 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
569 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
570 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
571 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
572 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
573 | #endif | |
574 | ||
575 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
576 | #ifdef CONFIG_PCIE2 | |
577 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
578 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
579 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
580 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
581 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
582 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
583 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
584 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
585 | #endif | |
586 | ||
587 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
588 | #ifdef CONFIG_PCIE3 | |
589 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
590 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
591 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
592 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
593 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
594 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
595 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
596 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
597 | #endif | |
598 | ||
599 | /* controller 4, Base address 203000 */ | |
600 | #ifdef CONFIG_PCIE4 | |
601 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
602 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
603 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
604 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
605 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
606 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
607 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
608 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
609 | #endif | |
610 | ||
062ef1a6 | 611 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
062ef1a6 PJ |
612 | #endif /* CONFIG_PCI */ |
613 | ||
614 | /* SATA */ | |
615 | #define CONFIG_FSL_SATA_V2 | |
616 | #ifdef CONFIG_FSL_SATA_V2 | |
062ef1a6 PJ |
617 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
618 | #define CONFIG_SATA1 | |
619 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
620 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
621 | ||
622 | #define CONFIG_LBA48 | |
062ef1a6 PJ |
623 | #endif |
624 | ||
625 | /* | |
626 | * USB | |
627 | */ | |
628 | #define CONFIG_HAS_FSL_DR_USB | |
629 | ||
630 | #ifdef CONFIG_HAS_FSL_DR_USB | |
8850c5d5 | 631 | #ifdef CONFIG_USB_EHCI_HCD |
062ef1a6 PJ |
632 | #define CONFIG_USB_EHCI_FSL |
633 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
e6a727ff | 634 | #define CONFIG_EHCI_DESC_BIG_ENDIAN |
062ef1a6 PJ |
635 | #endif |
636 | #endif | |
637 | ||
062ef1a6 PJ |
638 | #ifdef CONFIG_MMC |
639 | #define CONFIG_FSL_ESDHC | |
640 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
062ef1a6 PJ |
641 | #endif |
642 | ||
643 | /* Qman/Bman */ | |
644 | #ifndef CONFIG_NOBQFMAN | |
645 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
2a8b3422 | 646 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
647 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
648 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
649 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
650 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
651 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
652 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
653 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
654 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
655 | CONFIG_SYS_BMAN_CENA_SIZE) | |
656 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
657 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
2a8b3422 | 658 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
659 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
660 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
661 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
662 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
663 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
664 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
665 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
666 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
667 | CONFIG_SYS_QMAN_CENA_SIZE) | |
668 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
669 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
062ef1a6 PJ |
670 | |
671 | #define CONFIG_SYS_DPAA_FMAN | |
672 | #define CONFIG_SYS_DPAA_PME | |
673 | ||
59ff5d33 ZQ |
674 | #define CONFIG_QE |
675 | #define CONFIG_U_QE | |
676 | ||
062ef1a6 PJ |
677 | /* Default address of microcode for the Linux Fman driver */ |
678 | #if defined(CONFIG_SPIFLASH) | |
679 | /* | |
680 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
681 | * env, so we got 0x110000. | |
682 | */ | |
683 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 684 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
062ef1a6 PJ |
685 | #elif defined(CONFIG_SDCARD) |
686 | /* | |
687 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
18c01445 PK |
688 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
689 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
062ef1a6 PJ |
690 | */ |
691 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
18c01445 | 692 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
062ef1a6 PJ |
693 | #elif defined(CONFIG_NAND) |
694 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
18c01445 | 695 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
062ef1a6 PJ |
696 | #else |
697 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 698 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
18c01445 PK |
699 | #endif |
700 | ||
18c01445 PK |
701 | #if defined(CONFIG_SPIFLASH) |
702 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
703 | #elif defined(CONFIG_SDCARD) | |
704 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
705 | #elif defined(CONFIG_NAND) | |
706 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
707 | #else | |
59ff5d33 | 708 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
062ef1a6 | 709 | #endif |
18c01445 | 710 | |
062ef1a6 PJ |
711 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
712 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
713 | #endif /* CONFIG_NOBQFMAN */ | |
714 | ||
715 | #ifdef CONFIG_SYS_DPAA_FMAN | |
716 | #define CONFIG_FMAN_ENET | |
717 | #define CONFIG_PHY_VITESSE | |
718 | #define CONFIG_PHY_REALTEK | |
719 | #endif | |
720 | ||
721 | #ifdef CONFIG_FMAN_ENET | |
0167369c | 722 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
4b6067ae | 723 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
a016735c | 724 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
94af6842 | 725 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
319ed24a | 726 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
727 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
728 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 | |
729 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 | |
730 | #endif | |
731 | ||
78e56995 | 732 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
733 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
734 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 | |
735 | #else | |
736 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 | |
737 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 | |
f4c3917a | 738 | #endif |
062ef1a6 | 739 | |
db4a1767 | 740 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
6fcddd09 | 741 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
db4a1767 | 742 | #define CONFIG_VSC9953 |
6fcddd09 | 743 | #ifdef CONFIG_TARGET_T1040RDB |
db4a1767 CC |
744 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
745 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 | |
4b6067ae PJ |
746 | #else |
747 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 | |
748 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c | |
749 | #endif | |
db4a1767 CC |
750 | #endif |
751 | ||
062ef1a6 | 752 | #define CONFIG_MII /* MII PHY management */ |
714fd406 | 753 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
062ef1a6 PJ |
754 | #endif |
755 | ||
756 | /* | |
757 | * Environment | |
758 | */ | |
759 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
760 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
761 | ||
062ef1a6 PJ |
762 | /* |
763 | * Miscellaneous configurable options | |
764 | */ | |
765 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
766 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
767 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
768 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
062ef1a6 PJ |
769 | |
770 | /* | |
771 | * For booting Linux, the board info and command line data | |
772 | * have to be in the first 64 MB of memory, since this is | |
773 | * the maximum mapped by the Linux kernel during initialization. | |
774 | */ | |
775 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
776 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
777 | ||
778 | #ifdef CONFIG_CMD_KGDB | |
779 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
062ef1a6 PJ |
780 | #endif |
781 | ||
68b74739 PK |
782 | /* |
783 | * Dynamic MTD Partition support with mtdparts | |
784 | */ | |
e856bdcf | 785 | #ifdef CONFIG_MTD_NOR_FLASH |
68b74739 PK |
786 | #define CONFIG_MTD_DEVICE |
787 | #define CONFIG_MTD_PARTITIONS | |
68b74739 | 788 | #define CONFIG_FLASH_CFI_MTD |
68b74739 PK |
789 | #endif |
790 | ||
062ef1a6 PJ |
791 | /* |
792 | * Environment Configuration | |
793 | */ | |
794 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
795 | #define CONFIG_BOOTFILE "uImage" | |
796 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
797 | ||
798 | /* default location for tftp and bootm */ | |
799 | #define CONFIG_LOADADDR 1000000 | |
800 | ||
062ef1a6 | 801 | #define __USB_PHY_TYPE utmi |
363fb32a | 802 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
062ef1a6 | 803 | |
6fcddd09 | 804 | #ifdef CONFIG_TARGET_T1040RDB |
f4c3917a | 805 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
55ed8ae3 | 806 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
363fb32a | 807 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
0167369c | 808 | #elif defined(CONFIG_TARGET_T1042RDB) |
363fb32a | 809 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
a016735c | 810 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae | 811 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
319ed24a | 812 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae | 813 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
f4c3917a | 814 | #endif |
815 | ||
cf8ddacf JJ |
816 | #ifdef CONFIG_FSL_DIU_FB |
817 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" | |
818 | #else | |
819 | #define DIU_ENVIRONMENT | |
820 | #endif | |
821 | ||
062ef1a6 | 822 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
9b444be3 PJ |
823 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
824 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
825 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
062ef1a6 | 826 | "netdev=eth0\0" \ |
cf8ddacf | 827 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
062ef1a6 PJ |
828 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
829 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
830 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
831 | "protect off $ubootaddr +$filesize && " \ | |
832 | "erase $ubootaddr +$filesize && " \ | |
833 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
834 | "protect on $ubootaddr +$filesize && " \ | |
835 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
836 | "consoledev=ttyS0\0" \ | |
837 | "ramdiskaddr=2000000\0" \ | |
f4c3917a | 838 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
b24a4f62 | 839 | "fdtaddr=1e00000\0" \ |
f4c3917a | 840 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
3246584d | 841 | "bdev=sda3\0" |
062ef1a6 PJ |
842 | |
843 | #define CONFIG_LINUX \ | |
844 | "setenv bootargs root=/dev/ram rw " \ | |
845 | "console=$consoledev,$baudrate $othbootargs;" \ | |
846 | "setenv ramdiskaddr 0x02000000;" \ | |
847 | "setenv fdtaddr 0x00c00000;" \ | |
848 | "setenv loadaddr 0x1000000;" \ | |
849 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
850 | ||
851 | #define CONFIG_HDBOOT \ | |
852 | "setenv bootargs root=/dev/$bdev rw " \ | |
853 | "console=$consoledev,$baudrate $othbootargs;" \ | |
854 | "tftp $loadaddr $bootfile;" \ | |
855 | "tftp $fdtaddr $fdtfile;" \ | |
856 | "bootm $loadaddr - $fdtaddr" | |
857 | ||
858 | #define CONFIG_NFSBOOTCOMMAND \ | |
859 | "setenv bootargs root=/dev/nfs rw " \ | |
860 | "nfsroot=$serverip:$rootpath " \ | |
861 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
862 | "console=$consoledev,$baudrate $othbootargs;" \ | |
863 | "tftp $loadaddr $bootfile;" \ | |
864 | "tftp $fdtaddr $fdtfile;" \ | |
865 | "bootm $loadaddr - $fdtaddr" | |
866 | ||
867 | #define CONFIG_RAMBOOTCOMMAND \ | |
868 | "setenv bootargs root=/dev/ram rw " \ | |
869 | "console=$consoledev,$baudrate $othbootargs;" \ | |
870 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
871 | "tftp $loadaddr $bootfile;" \ | |
872 | "tftp $fdtaddr $fdtfile;" \ | |
873 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
874 | ||
875 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
876 | ||
062ef1a6 | 877 | #include <asm/fsl_secure_boot.h> |
ef6c55a2 | 878 | |
062ef1a6 | 879 | #endif /* __CONFIG_H */ |