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062ef1a6 | 1 | /* |
f4c3917a | 2 | + * Copyright 2014 Freescale Semiconductor, Inc. |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
062ef1a6 PJ |
6 | |
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | /* | |
f4c3917a | 11 | * T104x RDB board configuration file |
062ef1a6 | 12 | */ |
9f074e67 PK |
13 | #include <asm/config_mpc85xx.h> |
14 | ||
062ef1a6 | 15 | #ifdef CONFIG_RAMBOOT_PBL |
aa36c84e SG |
16 | |
17 | #ifndef CONFIG_SECURE_BOOT | |
18c01445 | 18 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg |
aa36c84e SG |
19 | #else |
20 | #define CONFIG_SYS_FSL_PBL_PBI \ | |
21 | $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg | |
22 | #endif | |
23 | ||
18c01445 PK |
24 | #define CONFIG_SPL_FLUSH_IMAGE |
25 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
18c01445 PK |
26 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 |
27 | #define CONFIG_SPL_PAD_TO 0x40000 | |
28 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
29 | #ifdef CONFIG_SPL_BUILD | |
30 | #define CONFIG_SPL_SKIP_RELOCATE | |
31 | #define CONFIG_SPL_COMMON_INIT_DDR | |
32 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
18c01445 PK |
33 | #endif |
34 | #define RESET_VECTOR_OFFSET 0x27FFC | |
35 | #define BOOT_PAGE_OFFSET 0x27000 | |
36 | ||
37 | #ifdef CONFIG_NAND | |
aa36c84e SG |
38 | #ifdef CONFIG_SECURE_BOOT |
39 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
40 | /* | |
41 | * HDR would be appended at end of image and copied to DDR along | |
42 | * with U-Boot image. | |
43 | */ | |
44 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ | |
45 | CONFIG_U_BOOT_HDR_SIZE) | |
46 | #else | |
18c01445 | 47 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
aa36c84e | 48 | #endif |
ce249d95 TY |
49 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 |
50 | #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 | |
18c01445 PK |
51 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) |
52 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
6fcddd09 | 53 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
54 | #define CONFIG_SYS_FSL_PBL_RCW \ |
55 | $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg | |
56 | #endif | |
55ed8ae3 | 57 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
58 | #define CONFIG_SYS_FSL_PBL_RCW \ |
59 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | |
60 | #endif | |
0167369c | 61 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
62 | #define CONFIG_SYS_FSL_PBL_RCW \ |
63 | $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg | |
64 | #endif | |
a016735c | 65 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
66 | #define CONFIG_SYS_FSL_PBL_RCW \ |
67 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | |
68 | #endif | |
319ed24a | 69 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
70 | #define CONFIG_SYS_FSL_PBL_RCW \ |
71 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | |
72 | #endif | |
18c01445 PK |
73 | #define CONFIG_SPL_NAND_BOOT |
74 | #endif | |
75 | ||
76 | #ifdef CONFIG_SPIFLASH | |
ce249d95 | 77 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 PK |
78 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
79 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
ce249d95 TY |
80 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) |
81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) | |
18c01445 PK |
82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) |
83 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
84 | #ifndef CONFIG_SPL_BUILD | |
85 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
86 | #endif | |
6fcddd09 | 87 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
88 | #define CONFIG_SYS_FSL_PBL_RCW \ |
89 | $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg | |
90 | #endif | |
55ed8ae3 | 91 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
92 | #define CONFIG_SYS_FSL_PBL_RCW \ |
93 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | |
94 | #endif | |
0167369c | 95 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
96 | #define CONFIG_SYS_FSL_PBL_RCW \ |
97 | $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg | |
98 | #endif | |
a016735c | 99 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
100 | #define CONFIG_SYS_FSL_PBL_RCW \ |
101 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | |
102 | #endif | |
319ed24a | 103 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
104 | #define CONFIG_SYS_FSL_PBL_RCW \ |
105 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | |
106 | #endif | |
18c01445 PK |
107 | #define CONFIG_SPL_SPI_BOOT |
108 | #endif | |
109 | ||
110 | #ifdef CONFIG_SDCARD | |
ce249d95 | 111 | #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
18c01445 | 112 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
ce249d95 TY |
113 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) |
114 | #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) | |
18c01445 PK |
115 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
116 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
117 | #ifndef CONFIG_SPL_BUILD | |
118 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
119 | #endif | |
6fcddd09 | 120 | #ifdef CONFIG_TARGET_T1040RDB |
ec90ac73 ZQ |
121 | #define CONFIG_SYS_FSL_PBL_RCW \ |
122 | $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg | |
123 | #endif | |
55ed8ae3 | 124 | #ifdef CONFIG_TARGET_T1042RDB_PI |
ec90ac73 ZQ |
125 | #define CONFIG_SYS_FSL_PBL_RCW \ |
126 | $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | |
127 | #endif | |
0167369c | 128 | #ifdef CONFIG_TARGET_T1042RDB |
ec90ac73 ZQ |
129 | #define CONFIG_SYS_FSL_PBL_RCW \ |
130 | $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg | |
131 | #endif | |
a016735c | 132 | #ifdef CONFIG_TARGET_T1040D4RDB |
ec90ac73 ZQ |
133 | #define CONFIG_SYS_FSL_PBL_RCW \ |
134 | $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | |
135 | #endif | |
319ed24a | 136 | #ifdef CONFIG_TARGET_T1042D4RDB |
ec90ac73 ZQ |
137 | #define CONFIG_SYS_FSL_PBL_RCW \ |
138 | $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | |
139 | #endif | |
18c01445 PK |
140 | #define CONFIG_SPL_MMC_BOOT |
141 | #endif | |
142 | ||
062ef1a6 PJ |
143 | #endif |
144 | ||
145 | /* High Level Configuration Options */ | |
062ef1a6 | 146 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
062ef1a6 PJ |
147 | #define CONFIG_MP /* support multiple processors */ |
148 | ||
5303a3de TY |
149 | /* support deep sleep */ |
150 | #define CONFIG_DEEP_SLEEP | |
5303a3de | 151 | |
062ef1a6 PJ |
152 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
153 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
154 | #endif | |
155 | ||
156 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 157 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
062ef1a6 | 158 | #define CONFIG_PCI_INDIRECT_BRIDGE |
b38eaec5 RD |
159 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
160 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
161 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
162 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
062ef1a6 PJ |
163 | |
164 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
165 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
166 | ||
062ef1a6 PJ |
167 | #define CONFIG_ENV_OVERWRITE |
168 | ||
e856bdcf | 169 | #ifdef CONFIG_MTD_NOR_FLASH |
062ef1a6 PJ |
170 | #define CONFIG_FLASH_CFI_DRIVER |
171 | #define CONFIG_SYS_FLASH_CFI | |
172 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
173 | #endif | |
174 | ||
062ef1a6 PJ |
175 | #if defined(CONFIG_SPIFLASH) |
176 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
062ef1a6 PJ |
177 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
178 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
179 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
180 | #elif defined(CONFIG_SDCARD) | |
181 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
062ef1a6 PJ |
182 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
183 | #define CONFIG_ENV_SIZE 0x2000 | |
18c01445 | 184 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
062ef1a6 | 185 | #elif defined(CONFIG_NAND) |
aa36c84e SG |
186 | #ifdef CONFIG_SECURE_BOOT |
187 | #define CONFIG_RAMBOOT_NAND | |
188 | #define CONFIG_BOOTSCRIPT_COPY_RAM | |
189 | #endif | |
062ef1a6 | 190 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
18c01445 | 191 | #define CONFIG_ENV_SIZE 0x2000 |
e222b1f3 | 192 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
062ef1a6 | 193 | #else |
062ef1a6 PJ |
194 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
195 | #define CONFIG_ENV_SIZE 0x2000 | |
196 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
197 | #endif | |
062ef1a6 PJ |
198 | |
199 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
200 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
201 | ||
202 | /* | |
203 | * These can be toggled for performance analysis, otherwise use default. | |
204 | */ | |
205 | #define CONFIG_SYS_CACHE_STASHING | |
206 | #define CONFIG_BACKSIDE_L2_CACHE | |
207 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
208 | #define CONFIG_BTB /* toggle branch predition */ | |
209 | #define CONFIG_DDR_ECC | |
210 | #ifdef CONFIG_DDR_ECC | |
211 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
212 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
213 | #endif | |
214 | ||
215 | #define CONFIG_ENABLE_36BIT_PHYS | |
216 | ||
217 | #define CONFIG_ADDR_MAP | |
218 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
219 | ||
220 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
221 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
222 | #define CONFIG_SYS_ALT_MEMTEST | |
062ef1a6 PJ |
223 | |
224 | /* | |
225 | * Config the L3 Cache as L3 SRAM | |
226 | */ | |
227 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 | |
aa36c84e SG |
228 | /* |
229 | * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence | |
230 | * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address | |
231 | * (CONFIG_SYS_INIT_L3_VADDR) will be different. | |
232 | */ | |
233 | #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 | |
18c01445 | 234 | #define CONFIG_SYS_L3_SIZE 256 << 10 |
aa36c84e | 235 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) |
18c01445 PK |
236 | #ifdef CONFIG_RAMBOOT_PBL |
237 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
238 | #endif | |
239 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
240 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) | |
241 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
242 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
062ef1a6 PJ |
243 | |
244 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
245 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
246 | ||
247 | /* | |
248 | * DDR Setup | |
249 | */ | |
250 | #define CONFIG_VERY_BIG_RAM | |
251 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
252 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
253 | ||
062ef1a6 | 254 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
96ac18c9 | 255 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
062ef1a6 PJ |
256 | |
257 | #define CONFIG_DDR_SPD | |
062ef1a6 PJ |
258 | |
259 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
260 | #define SPD_EEPROM_ADDRESS 0x51 | |
261 | ||
262 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
263 | ||
264 | /* | |
265 | * IFC Definitions | |
266 | */ | |
267 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
268 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
269 | ||
270 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) | |
271 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ | |
272 | CSPR_PORT_SIZE_16 | \ | |
273 | CSPR_MSEL_NOR | \ | |
274 | CSPR_V) | |
275 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
377ffcfa SS |
276 | |
277 | /* | |
278 | * TDM Definition | |
279 | */ | |
280 | #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 | |
281 | ||
062ef1a6 PJ |
282 | /* NOR Flash Timing Params */ |
283 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
284 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
285 | FTIM0_NOR_TEADC(0x5) | \ | |
286 | FTIM0_NOR_TEAHC(0x5)) | |
287 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
288 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
289 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
290 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
291 | FTIM2_NOR_TCH(0x4) | \ | |
292 | FTIM2_NOR_TWPH(0x0E) | \ | |
293 | FTIM2_NOR_TWP(0x1c)) | |
294 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
295 | ||
296 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
297 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
298 | ||
299 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
300 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
301 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
302 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
303 | ||
304 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
305 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
306 | ||
307 | /* CPLD on IFC */ | |
55153d6c PK |
308 | #define CPLD_LBMAP_MASK 0x3F |
309 | #define CPLD_BANK_SEL_MASK 0x07 | |
310 | #define CPLD_BANK_OVERRIDE 0x40 | |
311 | #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ | |
312 | #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ | |
313 | #define CPLD_LBMAP_RESET 0xFF | |
314 | #define CPLD_LBMAP_SHIFT 0x03 | |
4b6067ae | 315 | |
55ed8ae3 | 316 | #if defined(CONFIG_TARGET_T1042RDB_PI) |
cf8ddacf | 317 | #define CPLD_DIU_SEL_DFP 0x80 |
319ed24a | 318 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
319 | #define CPLD_DIU_SEL_DFP 0xc0 |
320 | #endif | |
321 | ||
a016735c | 322 | #if defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae PJ |
323 | #define CPLD_INT_MASK_ALL 0xFF |
324 | #define CPLD_INT_MASK_THERM 0x80 | |
325 | #define CPLD_INT_MASK_DVI_DFP 0x40 | |
326 | #define CPLD_INT_MASK_QSGMII1 0x20 | |
327 | #define CPLD_INT_MASK_QSGMII2 0x10 | |
328 | #define CPLD_INT_MASK_SGMI1 0x08 | |
329 | #define CPLD_INT_MASK_SGMI2 0x04 | |
330 | #define CPLD_INT_MASK_TDMR1 0x02 | |
331 | #define CPLD_INT_MASK_TDMR2 0x01 | |
cf8ddacf | 332 | #endif |
55153d6c | 333 | |
062ef1a6 PJ |
334 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
335 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
9b444be3 | 336 | #define CONFIG_SYS_CSPR2_EXT (0xf) |
062ef1a6 PJ |
337 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
338 | | CSPR_PORT_SIZE_8 \ | |
339 | | CSPR_MSEL_GPCM \ | |
340 | | CSPR_V) | |
341 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
342 | #define CONFIG_SYS_CSOR2 0x0 | |
343 | /* CPLD Timing parameters for IFC CS2 */ | |
344 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
345 | FTIM0_GPCM_TEADC(0x0e) | \ | |
346 | FTIM0_GPCM_TEAHC(0x0e)) | |
347 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
348 | FTIM1_GPCM_TRAD(0x1f)) | |
349 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 350 | FTIM2_GPCM_TCH(0x8) | \ |
062ef1a6 PJ |
351 | FTIM2_GPCM_TWP(0x1f)) |
352 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
353 | ||
354 | /* NAND Flash on IFC */ | |
355 | #define CONFIG_NAND_FSL_IFC | |
356 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
357 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
358 | ||
359 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
360 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
361 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
362 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
363 | | CSPR_V) | |
364 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
365 | ||
366 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
367 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
368 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
369 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
370 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
371 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ | |
372 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
373 | ||
374 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
375 | ||
376 | /* ONFI NAND Flash mode0 Timing Params */ | |
377 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
378 | FTIM0_NAND_TWP(0x18) | \ | |
379 | FTIM0_NAND_TWCHT(0x07) | \ | |
380 | FTIM0_NAND_TWH(0x0a)) | |
381 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
382 | FTIM1_NAND_TWBE(0x39) | \ | |
383 | FTIM1_NAND_TRR(0x0e) | \ | |
384 | FTIM1_NAND_TRP(0x18)) | |
385 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
386 | FTIM2_NAND_TREH(0x0a) | \ | |
387 | FTIM2_NAND_TWHRE(0x1e)) | |
388 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
389 | ||
390 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
391 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
392 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
062ef1a6 PJ |
393 | |
394 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
395 | ||
396 | #if defined(CONFIG_NAND) | |
397 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
398 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
399 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
400 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
401 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
402 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
403 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
404 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
405 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT | |
406 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
407 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
408 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
409 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
410 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
411 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
412 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
413 | #else | |
414 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT | |
415 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR | |
416 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
417 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
418 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
419 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
420 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
421 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
422 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
423 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
424 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
425 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
426 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
427 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
428 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
429 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
430 | #endif | |
431 | ||
18c01445 PK |
432 | #ifdef CONFIG_SPL_BUILD |
433 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
434 | #else | |
435 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
436 | #endif | |
062ef1a6 PJ |
437 | |
438 | #if defined(CONFIG_RAMBOOT_PBL) | |
439 | #define CONFIG_SYS_RAMBOOT | |
440 | #endif | |
441 | ||
9f074e67 PK |
442 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 |
443 | #if defined(CONFIG_NAND) | |
444 | #define CONFIG_A008044_WORKAROUND | |
445 | #endif | |
446 | #endif | |
447 | ||
062ef1a6 PJ |
448 | #define CONFIG_BOARD_EARLY_INIT_R |
449 | #define CONFIG_MISC_INIT_R | |
450 | ||
451 | #define CONFIG_HWCONFIG | |
452 | ||
453 | /* define to use L1 as initial stack */ | |
454 | #define CONFIG_L1_INIT_RAM | |
455 | #define CONFIG_SYS_INIT_RAM_LOCK | |
456 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
457 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 458 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
062ef1a6 PJ |
459 | /* The assembler doesn't like typecast */ |
460 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
461 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
462 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
463 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
464 | ||
465 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
466 | GENERATED_GBL_DATA_SIZE) | |
467 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
468 | ||
9307cbab | 469 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
062ef1a6 PJ |
470 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
471 | ||
472 | /* Serial Port - controlled on board with jumper J8 | |
473 | * open - index 2 | |
474 | * shorted - index 1 | |
475 | */ | |
476 | #define CONFIG_CONS_INDEX 1 | |
062ef1a6 PJ |
477 | #define CONFIG_SYS_NS16550_SERIAL |
478 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
479 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
480 | ||
481 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
482 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
483 | ||
484 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
485 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
486 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
487 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
062ef1a6 | 488 | |
319ed24a | 489 | #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) |
cf8ddacf JJ |
490 | /* Video */ |
491 | #define CONFIG_FSL_DIU_FB | |
492 | ||
493 | #ifdef CONFIG_FSL_DIU_FB | |
494 | #define CONFIG_FSL_DIU_CH7301 | |
495 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) | |
cf8ddacf JJ |
496 | #define CONFIG_VIDEO_LOGO |
497 | #define CONFIG_VIDEO_BMP_LOGO | |
498 | #endif | |
499 | #endif | |
500 | ||
062ef1a6 PJ |
501 | /* I2C */ |
502 | #define CONFIG_SYS_I2C | |
503 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
504 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ | |
b0d97cd2 SL |
505 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
506 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 | |
507 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 | |
062ef1a6 | 508 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
062ef1a6 | 509 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
b0d97cd2 SL |
510 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F |
511 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
062ef1a6 | 512 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
b0d97cd2 SL |
513 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
514 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
515 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
062ef1a6 PJ |
516 | |
517 | /* I2C bus multiplexer */ | |
518 | #define I2C_MUX_PCA_ADDR 0x70 | |
519 | #define I2C_MUX_CH_DEFAULT 0x8 | |
f4c3917a | 520 | |
78e56995 YS |
521 | #if defined(CONFIG_TARGET_T1042RDB_PI) || \ |
522 | defined(CONFIG_TARGET_T1040D4RDB) || \ | |
523 | defined(CONFIG_TARGET_T1042D4RDB) | |
cf8ddacf JJ |
524 | /* LDI/DVI Encoder for display */ |
525 | #define CONFIG_SYS_I2C_LDI_ADDR 0x38 | |
526 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
527 | ||
f4c3917a | 528 | /* |
529 | * RTC configuration | |
530 | */ | |
531 | #define RTC | |
532 | #define CONFIG_RTC_DS1337 1 | |
533 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
062ef1a6 | 534 | |
f4c3917a | 535 | /*DVI encoder*/ |
536 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 | |
537 | #endif | |
062ef1a6 PJ |
538 | |
539 | /* | |
540 | * eSPI - Enhanced SPI | |
541 | */ | |
7172de33 | 542 | #define CONFIG_SPI_FLASH_BAR |
062ef1a6 PJ |
543 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
544 | #define CONFIG_SF_DEFAULT_MODE 0 | |
9b444be3 PJ |
545 | #define CONFIG_ENV_SPI_BUS 0 |
546 | #define CONFIG_ENV_SPI_CS 0 | |
547 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
548 | #define CONFIG_ENV_SPI_MODE 0 | |
062ef1a6 PJ |
549 | |
550 | /* | |
551 | * General PCI | |
552 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
553 | */ | |
554 | ||
555 | #ifdef CONFIG_PCI | |
556 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
557 | #ifdef CONFIG_PCIE1 | |
558 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
559 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
560 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
561 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
562 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
563 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
564 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
565 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
566 | #endif | |
567 | ||
568 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
569 | #ifdef CONFIG_PCIE2 | |
570 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 | |
571 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
572 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull | |
573 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
574 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
575 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
576 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
577 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
578 | #endif | |
579 | ||
580 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
581 | #ifdef CONFIG_PCIE3 | |
582 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
583 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
584 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
585 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
586 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
587 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
588 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
589 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
590 | #endif | |
591 | ||
592 | /* controller 4, Base address 203000 */ | |
593 | #ifdef CONFIG_PCIE4 | |
594 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 | |
595 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
596 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull | |
597 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
598 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 | |
599 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
600 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
601 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
602 | #endif | |
603 | ||
062ef1a6 | 604 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
062ef1a6 PJ |
605 | #endif /* CONFIG_PCI */ |
606 | ||
607 | /* SATA */ | |
608 | #define CONFIG_FSL_SATA_V2 | |
609 | #ifdef CONFIG_FSL_SATA_V2 | |
062ef1a6 PJ |
610 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
611 | #define CONFIG_SATA1 | |
612 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
613 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
614 | ||
615 | #define CONFIG_LBA48 | |
062ef1a6 PJ |
616 | #endif |
617 | ||
618 | /* | |
619 | * USB | |
620 | */ | |
621 | #define CONFIG_HAS_FSL_DR_USB | |
622 | ||
623 | #ifdef CONFIG_HAS_FSL_DR_USB | |
8850c5d5 | 624 | #ifdef CONFIG_USB_EHCI_HCD |
062ef1a6 PJ |
625 | #define CONFIG_USB_EHCI_FSL |
626 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
e6a727ff | 627 | #define CONFIG_EHCI_DESC_BIG_ENDIAN |
062ef1a6 PJ |
628 | #endif |
629 | #endif | |
630 | ||
062ef1a6 PJ |
631 | #ifdef CONFIG_MMC |
632 | #define CONFIG_FSL_ESDHC | |
633 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
062ef1a6 PJ |
634 | #endif |
635 | ||
636 | /* Qman/Bman */ | |
637 | #ifndef CONFIG_NOBQFMAN | |
2a8b3422 | 638 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
639 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
640 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
641 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
642 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
643 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
644 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
645 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
646 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
647 | CONFIG_SYS_BMAN_CENA_SIZE) | |
648 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
649 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
2a8b3422 | 650 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
062ef1a6 PJ |
651 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
652 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
653 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
654 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
655 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
656 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
657 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
658 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
659 | CONFIG_SYS_QMAN_CENA_SIZE) | |
660 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
661 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
062ef1a6 PJ |
662 | |
663 | #define CONFIG_SYS_DPAA_FMAN | |
664 | #define CONFIG_SYS_DPAA_PME | |
665 | ||
59ff5d33 ZQ |
666 | #define CONFIG_QE |
667 | #define CONFIG_U_QE | |
668 | ||
062ef1a6 PJ |
669 | /* Default address of microcode for the Linux Fman driver */ |
670 | #if defined(CONFIG_SPIFLASH) | |
671 | /* | |
672 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
673 | * env, so we got 0x110000. | |
674 | */ | |
675 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 676 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
062ef1a6 PJ |
677 | #elif defined(CONFIG_SDCARD) |
678 | /* | |
679 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
18c01445 PK |
680 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
681 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
062ef1a6 PJ |
682 | */ |
683 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
18c01445 | 684 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
062ef1a6 PJ |
685 | #elif defined(CONFIG_NAND) |
686 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
18c01445 | 687 | #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) |
062ef1a6 PJ |
688 | #else |
689 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 690 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
18c01445 PK |
691 | #endif |
692 | ||
18c01445 PK |
693 | #if defined(CONFIG_SPIFLASH) |
694 | #define CONFIG_SYS_QE_FW_ADDR 0x130000 | |
695 | #elif defined(CONFIG_SDCARD) | |
696 | #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) | |
697 | #elif defined(CONFIG_NAND) | |
698 | #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
699 | #else | |
59ff5d33 | 700 | #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 |
062ef1a6 | 701 | #endif |
18c01445 | 702 | |
062ef1a6 PJ |
703 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
704 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
705 | #endif /* CONFIG_NOBQFMAN */ | |
706 | ||
707 | #ifdef CONFIG_SYS_DPAA_FMAN | |
708 | #define CONFIG_FMAN_ENET | |
709 | #define CONFIG_PHY_VITESSE | |
710 | #define CONFIG_PHY_REALTEK | |
711 | #endif | |
712 | ||
713 | #ifdef CONFIG_FMAN_ENET | |
0167369c | 714 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) |
4b6067ae | 715 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 |
a016735c | 716 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
94af6842 | 717 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 |
319ed24a | 718 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
719 | #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 |
720 | #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 | |
721 | #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 | |
722 | #endif | |
723 | ||
78e56995 | 724 | #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae PJ |
725 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 |
726 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 | |
727 | #else | |
728 | #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 | |
729 | #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 | |
f4c3917a | 730 | #endif |
062ef1a6 | 731 | |
db4a1767 | 732 | /* Enable VSC9953 L2 Switch driver on T1040 SoC */ |
6fcddd09 | 733 | #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) |
db4a1767 | 734 | #define CONFIG_VSC9953 |
6fcddd09 | 735 | #ifdef CONFIG_TARGET_T1040RDB |
db4a1767 CC |
736 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 |
737 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 | |
4b6067ae PJ |
738 | #else |
739 | #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 | |
740 | #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c | |
741 | #endif | |
db4a1767 CC |
742 | #endif |
743 | ||
062ef1a6 | 744 | #define CONFIG_MII /* MII PHY management */ |
714fd406 | 745 | #define CONFIG_ETHPRIME "FM1@DTSEC4" |
062ef1a6 PJ |
746 | #endif |
747 | ||
748 | /* | |
749 | * Environment | |
750 | */ | |
751 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
752 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
753 | ||
062ef1a6 PJ |
754 | /* |
755 | * Miscellaneous configurable options | |
756 | */ | |
062ef1a6 | 757 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
062ef1a6 PJ |
758 | |
759 | /* | |
760 | * For booting Linux, the board info and command line data | |
761 | * have to be in the first 64 MB of memory, since this is | |
762 | * the maximum mapped by the Linux kernel during initialization. | |
763 | */ | |
764 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
765 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
766 | ||
767 | #ifdef CONFIG_CMD_KGDB | |
768 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
062ef1a6 PJ |
769 | #endif |
770 | ||
68b74739 PK |
771 | /* |
772 | * Dynamic MTD Partition support with mtdparts | |
773 | */ | |
e856bdcf | 774 | #ifdef CONFIG_MTD_NOR_FLASH |
68b74739 PK |
775 | #define CONFIG_MTD_DEVICE |
776 | #define CONFIG_MTD_PARTITIONS | |
68b74739 | 777 | #define CONFIG_FLASH_CFI_MTD |
68b74739 PK |
778 | #endif |
779 | ||
062ef1a6 PJ |
780 | /* |
781 | * Environment Configuration | |
782 | */ | |
783 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
784 | #define CONFIG_BOOTFILE "uImage" | |
785 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
786 | ||
787 | /* default location for tftp and bootm */ | |
788 | #define CONFIG_LOADADDR 1000000 | |
789 | ||
062ef1a6 | 790 | #define __USB_PHY_TYPE utmi |
363fb32a | 791 | #define RAMDISKFILE "t104xrdb/ramdisk.uboot" |
062ef1a6 | 792 | |
6fcddd09 | 793 | #ifdef CONFIG_TARGET_T1040RDB |
f4c3917a | 794 | #define FDTFILE "t1040rdb/t1040rdb.dtb" |
55ed8ae3 | 795 | #elif defined(CONFIG_TARGET_T1042RDB_PI) |
363fb32a | 796 | #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" |
0167369c | 797 | #elif defined(CONFIG_TARGET_T1042RDB) |
363fb32a | 798 | #define FDTFILE "t1042rdb/t1042rdb.dtb" |
a016735c | 799 | #elif defined(CONFIG_TARGET_T1040D4RDB) |
4b6067ae | 800 | #define FDTFILE "t1042rdb/t1040d4rdb.dtb" |
319ed24a | 801 | #elif defined(CONFIG_TARGET_T1042D4RDB) |
4b6067ae | 802 | #define FDTFILE "t1042rdb/t1042d4rdb.dtb" |
f4c3917a | 803 | #endif |
804 | ||
cf8ddacf JJ |
805 | #ifdef CONFIG_FSL_DIU_FB |
806 | #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" | |
807 | #else | |
808 | #define DIU_ENVIRONMENT | |
809 | #endif | |
810 | ||
062ef1a6 | 811 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
9b444be3 PJ |
812 | "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ |
813 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
814 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
062ef1a6 | 815 | "netdev=eth0\0" \ |
cf8ddacf | 816 | "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ |
062ef1a6 PJ |
817 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
818 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
819 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
820 | "protect off $ubootaddr +$filesize && " \ | |
821 | "erase $ubootaddr +$filesize && " \ | |
822 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
823 | "protect on $ubootaddr +$filesize && " \ | |
824 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
825 | "consoledev=ttyS0\0" \ | |
826 | "ramdiskaddr=2000000\0" \ | |
f4c3917a | 827 | "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ |
b24a4f62 | 828 | "fdtaddr=1e00000\0" \ |
f4c3917a | 829 | "fdtfile=" __stringify(FDTFILE) "\0" \ |
3246584d | 830 | "bdev=sda3\0" |
062ef1a6 PJ |
831 | |
832 | #define CONFIG_LINUX \ | |
833 | "setenv bootargs root=/dev/ram rw " \ | |
834 | "console=$consoledev,$baudrate $othbootargs;" \ | |
835 | "setenv ramdiskaddr 0x02000000;" \ | |
836 | "setenv fdtaddr 0x00c00000;" \ | |
837 | "setenv loadaddr 0x1000000;" \ | |
838 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
839 | ||
840 | #define CONFIG_HDBOOT \ | |
841 | "setenv bootargs root=/dev/$bdev rw " \ | |
842 | "console=$consoledev,$baudrate $othbootargs;" \ | |
843 | "tftp $loadaddr $bootfile;" \ | |
844 | "tftp $fdtaddr $fdtfile;" \ | |
845 | "bootm $loadaddr - $fdtaddr" | |
846 | ||
847 | #define CONFIG_NFSBOOTCOMMAND \ | |
848 | "setenv bootargs root=/dev/nfs rw " \ | |
849 | "nfsroot=$serverip:$rootpath " \ | |
850 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
851 | "console=$consoledev,$baudrate $othbootargs;" \ | |
852 | "tftp $loadaddr $bootfile;" \ | |
853 | "tftp $fdtaddr $fdtfile;" \ | |
854 | "bootm $loadaddr - $fdtaddr" | |
855 | ||
856 | #define CONFIG_RAMBOOTCOMMAND \ | |
857 | "setenv bootargs root=/dev/ram rw " \ | |
858 | "console=$consoledev,$baudrate $othbootargs;" \ | |
859 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
860 | "tftp $loadaddr $bootfile;" \ | |
861 | "tftp $fdtaddr $fdtfile;" \ | |
862 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
863 | ||
864 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
865 | ||
062ef1a6 | 866 | #include <asm/fsl_secure_boot.h> |
ef6c55a2 | 867 | |
062ef1a6 | 868 | #endif /* __CONFIG_H */ |