]>
Commit | Line | Data |
---|---|---|
8d67c368 SL |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * T2080 RDB/PCIe board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __T2080RDB_H | |
12 | #define __T2080RDB_H | |
13 | ||
8d67c368 | 14 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
8d67c368 SL |
15 | #define CONFIG_FSL_SATA_V2 |
16 | ||
17 | /* High Level Configuration Options */ | |
8d67c368 SL |
18 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
19 | #define CONFIG_MP /* support multiple processors */ | |
20 | #define CONFIG_ENABLE_36BIT_PHYS | |
21 | ||
22 | #ifdef CONFIG_PHYS_64BIT | |
23 | #define CONFIG_ADDR_MAP 1 | |
24 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
25 | #endif | |
26 | ||
27 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 28 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
8d67c368 SL |
29 | #define CONFIG_ENV_OVERWRITE |
30 | ||
31 | #ifdef CONFIG_RAMBOOT_PBL | |
e4536f8e | 32 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg |
4d666683 | 33 | |
4d666683 SL |
34 | #define CONFIG_SPL_FLUSH_IMAGE |
35 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
4d666683 SL |
36 | #define CONFIG_SYS_TEXT_BASE 0x00201000 |
37 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
38 | #define CONFIG_SPL_PAD_TO 0x40000 | |
39 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
40 | #define RESET_VECTOR_OFFSET 0x27FFC | |
41 | #define BOOT_PAGE_OFFSET 0x27000 | |
42 | #ifdef CONFIG_SPL_BUILD | |
43 | #define CONFIG_SPL_SKIP_RELOCATE | |
44 | #define CONFIG_SPL_COMMON_INIT_DDR | |
45 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
4d666683 SL |
46 | #endif |
47 | ||
48 | #ifdef CONFIG_NAND | |
4d666683 SL |
49 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
50 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
ec90ac73 | 54 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg |
4d666683 SL |
55 | #define CONFIG_SPL_NAND_BOOT |
56 | #endif | |
57 | ||
58 | #ifdef CONFIG_SPIFLASH | |
59 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
4d666683 SL |
60 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
61 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
62 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) | |
63 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) | |
64 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) | |
65 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
66 | #ifndef CONFIG_SPL_BUILD | |
67 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
68 | #endif | |
ec90ac73 | 69 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg |
4d666683 SL |
70 | #define CONFIG_SPL_SPI_BOOT |
71 | #endif | |
72 | ||
73 | #ifdef CONFIG_SDCARD | |
74 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
4d666683 SL |
75 | #define CONFIG_SPL_MMC_MINIMAL |
76 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
77 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) | |
78 | #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) | |
79 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
80 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
81 | #ifndef CONFIG_SPL_BUILD | |
82 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
83 | #endif | |
ec90ac73 | 84 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg |
4d666683 | 85 | #define CONFIG_SPL_MMC_BOOT |
8d67c368 SL |
86 | #endif |
87 | ||
4d666683 SL |
88 | #endif /* CONFIG_RAMBOOT_PBL */ |
89 | ||
8d67c368 SL |
90 | #define CONFIG_SRIO_PCIE_BOOT_MASTER |
91 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
92 | /* Set 1M boot space */ | |
93 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
94 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
95 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
96 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
8d67c368 SL |
97 | #endif |
98 | ||
99 | #ifndef CONFIG_SYS_TEXT_BASE | |
100 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
101 | #endif | |
102 | ||
103 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
104 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
105 | #endif | |
106 | ||
107 | /* | |
108 | * These can be toggled for performance analysis, otherwise use default. | |
109 | */ | |
110 | #define CONFIG_SYS_CACHE_STASHING | |
111 | #define CONFIG_BTB /* toggle branch predition */ | |
112 | #define CONFIG_DDR_ECC | |
113 | #ifdef CONFIG_DDR_ECC | |
114 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
115 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
116 | #endif | |
117 | ||
4913229e SL |
118 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
119 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
120 | #define CONFIG_SYS_ALT_MEMTEST | |
121 | ||
e856bdcf | 122 | #ifdef CONFIG_MTD_NOR_FLASH |
8d67c368 SL |
123 | #define CONFIG_FLASH_CFI_DRIVER |
124 | #define CONFIG_SYS_FLASH_CFI | |
125 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
126 | #endif | |
127 | ||
128 | #if defined(CONFIG_SPIFLASH) | |
129 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
130 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
131 | #define CONFIG_ENV_SPI_BUS 0 | |
132 | #define CONFIG_ENV_SPI_CS 0 | |
133 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
134 | #define CONFIG_ENV_SPI_MODE 0 | |
135 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
136 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
137 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
138 | #elif defined(CONFIG_SDCARD) | |
139 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
140 | #define CONFIG_ENV_IS_IN_MMC | |
141 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
142 | #define CONFIG_ENV_SIZE 0x2000 | |
4d666683 | 143 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
8d67c368 SL |
144 | #elif defined(CONFIG_NAND) |
145 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
146 | #define CONFIG_ENV_IS_IN_NAND | |
4d666683 | 147 | #define CONFIG_ENV_SIZE 0x2000 |
8d67c368 SL |
148 | #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) |
149 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) | |
150 | #define CONFIG_ENV_IS_IN_REMOTE | |
151 | #define CONFIG_ENV_ADDR 0xffe20000 | |
152 | #define CONFIG_ENV_SIZE 0x2000 | |
153 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
154 | #define CONFIG_ENV_SIZE 0x2000 | |
155 | #else | |
156 | #define CONFIG_ENV_IS_IN_FLASH | |
157 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
158 | #define CONFIG_ENV_SIZE 0x2000 | |
159 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
160 | #endif | |
161 | ||
162 | #ifndef __ASSEMBLY__ | |
163 | unsigned long get_board_sys_clk(void); | |
164 | unsigned long get_board_ddr_clk(void); | |
165 | #endif | |
166 | ||
167 | #define CONFIG_SYS_CLK_FREQ 66660000 | |
168 | #define CONFIG_DDR_CLK_FREQ 133330000 | |
169 | ||
170 | /* | |
171 | * Config the L3 Cache as L3 SRAM | |
172 | */ | |
4d666683 SL |
173 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
174 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
175 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
176 | #ifdef CONFIG_RAMBOOT_PBL | |
177 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
178 | #endif | |
179 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
180 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
181 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
182 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
8d67c368 SL |
183 | |
184 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
185 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
186 | ||
187 | /* EEPROM */ | |
188 | #define CONFIG_ID_EEPROM | |
189 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
190 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
191 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
ef531c73 | 192 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
8d67c368 SL |
193 | |
194 | /* | |
195 | * DDR Setup | |
196 | */ | |
197 | #define CONFIG_VERY_BIG_RAM | |
198 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
199 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
200 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
201 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
202 | #define CONFIG_DDR_SPD | |
8d67c368 SL |
203 | #undef CONFIG_FSL_DDR_INTERACTIVE |
204 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
205 | #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ | |
206 | #define SPD_EEPROM_ADDRESS1 0x51 | |
207 | #define SPD_EEPROM_ADDRESS2 0x52 | |
208 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
209 | #define CTRL_INTLV_PREFERED cacheline | |
210 | ||
211 | /* | |
212 | * IFC Definitions | |
213 | */ | |
214 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 | |
215 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
216 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
217 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
218 | CSPR_PORT_SIZE_16 | \ | |
219 | CSPR_MSEL_NOR | \ | |
220 | CSPR_V) | |
221 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
222 | ||
223 | /* NOR Flash Timing Params */ | |
224 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
225 | ||
226 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
227 | FTIM0_NOR_TEADC(0x5) | \ | |
228 | FTIM0_NOR_TEAHC(0x5)) | |
229 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
230 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
231 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
232 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
233 | FTIM2_NOR_TCH(0x4) | \ | |
234 | FTIM2_NOR_TWPH(0x0E) | \ | |
235 | FTIM2_NOR_TWP(0x1c)) | |
236 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
237 | ||
238 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
239 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
240 | ||
241 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
242 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
243 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
244 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
245 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
246 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } | |
247 | ||
248 | /* CPLD on IFC */ | |
249 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
250 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
251 | #define CONFIG_SYS_CSPR2_EXT (0xf) | |
252 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ | |
253 | | CSPR_PORT_SIZE_8 \ | |
254 | | CSPR_MSEL_GPCM \ | |
255 | | CSPR_V) | |
256 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) | |
257 | #define CONFIG_SYS_CSOR2 0x0 | |
258 | ||
259 | /* CPLD Timing parameters for IFC CS2 */ | |
260 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
261 | FTIM0_GPCM_TEADC(0x0e) | \ | |
262 | FTIM0_GPCM_TEAHC(0x0e)) | |
263 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
264 | FTIM1_GPCM_TRAD(0x1f)) | |
265 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 266 | FTIM2_GPCM_TCH(0x8) | \ |
8d67c368 SL |
267 | FTIM2_GPCM_TWP(0x1f)) |
268 | #define CONFIG_SYS_CS2_FTIM3 0x0 | |
269 | ||
270 | /* NAND Flash on IFC */ | |
271 | #define CONFIG_NAND_FSL_IFC | |
272 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
273 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
274 | ||
275 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
276 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
277 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
278 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
279 | | CSPR_V) | |
280 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
281 | ||
282 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
283 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
284 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
285 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
286 | | CSOR_NAND_PGS_2K /* Page Size = 2K */\ | |
287 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ | |
288 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
289 | ||
290 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
291 | ||
292 | /* ONFI NAND Flash mode0 Timing Params */ | |
293 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
294 | FTIM0_NAND_TWP(0x18) | \ | |
295 | FTIM0_NAND_TWCHT(0x07) | \ | |
296 | FTIM0_NAND_TWH(0x0a)) | |
297 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
298 | FTIM1_NAND_TWBE(0x39) | \ | |
299 | FTIM1_NAND_TRR(0x0e) | \ | |
300 | FTIM1_NAND_TRP(0x18)) | |
301 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
302 | FTIM2_NAND_TREH(0x0a) | \ | |
303 | FTIM2_NAND_TWHRE(0x1e)) | |
304 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
305 | ||
306 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
307 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
308 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
8d67c368 SL |
309 | #define CONFIG_CMD_NAND |
310 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
311 | ||
312 | #if defined(CONFIG_NAND) | |
313 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
314 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
315 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
316 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
317 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
318 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
319 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
320 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
321 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
322 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
323 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
324 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
325 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
326 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
327 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
328 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
329 | #else | |
330 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
331 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
332 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
333 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
334 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
335 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
336 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
337 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
338 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
339 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
340 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
341 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
342 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
343 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
344 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
345 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
346 | #endif | |
347 | ||
348 | #if defined(CONFIG_RAMBOOT_PBL) | |
349 | #define CONFIG_SYS_RAMBOOT | |
350 | #endif | |
351 | ||
4d666683 SL |
352 | #ifdef CONFIG_SPL_BUILD |
353 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
354 | #else | |
355 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
356 | #endif | |
357 | ||
8d67c368 SL |
358 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
359 | #define CONFIG_MISC_INIT_R | |
360 | #define CONFIG_HWCONFIG | |
361 | ||
362 | /* define to use L1 as initial stack */ | |
363 | #define CONFIG_L1_INIT_RAM | |
364 | #define CONFIG_SYS_INIT_RAM_LOCK | |
365 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
366 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 367 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
8d67c368 SL |
368 | /* The assembler doesn't like typecast */ |
369 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
370 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
371 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
372 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
373 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
374 | GENERATED_GBL_DATA_SIZE) | |
375 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
9307cbab | 376 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
8d67c368 SL |
377 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
378 | ||
379 | /* | |
380 | * Serial Port | |
381 | */ | |
382 | #define CONFIG_CONS_INDEX 1 | |
8d67c368 SL |
383 | #define CONFIG_SYS_NS16550_SERIAL |
384 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
385 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
386 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
387 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
388 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
389 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
390 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
391 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
392 | ||
8d67c368 SL |
393 | /* |
394 | * I2C | |
395 | */ | |
396 | #define CONFIG_SYS_I2C | |
397 | #define CONFIG_SYS_I2C_FSL | |
398 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
399 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
400 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F | |
401 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
402 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
403 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
404 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
405 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
406 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
407 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
408 | #define CONFIG_SYS_FSL_I2C3_SPEED 100000 | |
409 | #define CONFIG_SYS_FSL_I2C4_SPEED 100000 | |
410 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
411 | #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ | |
412 | #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ | |
413 | #define I2C_MUX_CH_DEFAULT 0x8 | |
414 | ||
e5abb92c YZ |
415 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
416 | ||
417 | #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" | |
418 | #ifndef CONFIG_SPL_BUILD | |
419 | #define CONFIG_VID | |
420 | #endif | |
421 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
422 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
423 | /* The lowest and highest voltage allowed for T208xRDB */ | |
424 | #define VDD_MV_MIN 819 | |
425 | #define VDD_MV_MAX 1212 | |
8d67c368 SL |
426 | |
427 | /* | |
428 | * RapidIO | |
429 | */ | |
430 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
431 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
432 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
433 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
434 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
435 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
436 | /* | |
437 | * for slave u-boot IMAGE instored in master memory space, | |
438 | * PHYS must be aligned based on the SIZE | |
439 | */ | |
e4911815 LG |
440 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
441 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
442 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
443 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
8d67c368 SL |
444 | /* |
445 | * for slave UCODE and ENV instored in master memory space, | |
446 | * PHYS must be aligned based on the SIZE | |
447 | */ | |
e4911815 | 448 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
8d67c368 SL |
449 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
450 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
451 | ||
452 | /* slave core release by master*/ | |
453 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
454 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
455 | ||
456 | /* | |
457 | * SRIO_PCIE_BOOT - SLAVE | |
458 | */ | |
459 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
460 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
461 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
462 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
463 | #endif | |
464 | ||
465 | /* | |
466 | * eSPI - Enhanced SPI | |
467 | */ | |
468 | #ifdef CONFIG_SPI_FLASH | |
8d67c368 | 469 | #define CONFIG_SPI_FLASH_BAR |
8d67c368 SL |
470 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
471 | #define CONFIG_SF_DEFAULT_MODE 0 | |
472 | #endif | |
473 | ||
474 | /* | |
475 | * General PCI | |
476 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
477 | */ | |
b38eaec5 RD |
478 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
479 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
480 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
481 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
8d67c368 SL |
482 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
483 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
484 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
485 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
486 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
487 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
488 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
489 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
490 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
491 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
492 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
493 | ||
494 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
495 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
496 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
497 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
498 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
499 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
500 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
501 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
502 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
503 | ||
504 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
505 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
506 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
507 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull | |
508 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
509 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
510 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
511 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
512 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
513 | ||
514 | /* controller 4, Base address 203000 */ | |
515 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 | |
516 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
517 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull | |
518 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ | |
519 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
520 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
521 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
522 | ||
523 | #ifdef CONFIG_PCI | |
524 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
525 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ | |
8d67c368 | 526 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
8d67c368 SL |
527 | #endif |
528 | ||
529 | /* Qman/Bman */ | |
530 | #ifndef CONFIG_NOBQFMAN | |
531 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
532 | #define CONFIG_SYS_BMAN_NUM_PORTALS 18 | |
533 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
534 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
535 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
536 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
537 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
538 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
539 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
540 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
541 | CONFIG_SYS_BMAN_CENA_SIZE) | |
542 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
543 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
8d67c368 SL |
544 | #define CONFIG_SYS_QMAN_NUM_PORTALS 18 |
545 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
546 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
547 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
548 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
549 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
550 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
551 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
552 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
553 | CONFIG_SYS_QMAN_CENA_SIZE) | |
554 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
555 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
8d67c368 SL |
556 | |
557 | #define CONFIG_SYS_DPAA_FMAN | |
558 | #define CONFIG_SYS_DPAA_PME | |
559 | #define CONFIG_SYS_PMAN | |
560 | #define CONFIG_SYS_DPAA_DCE | |
561 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
562 | #define CONFIG_SYS_INTERLAKEN | |
563 | ||
564 | /* Default address of microcode for the Linux Fman driver */ | |
565 | #if defined(CONFIG_SPIFLASH) | |
566 | /* | |
567 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
568 | * env, so we got 0x110000. | |
569 | */ | |
570 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
ef531c73 SL |
571 | #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH |
572 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 | |
8d67c368 SL |
573 | #define CONFIG_CORTINA_FW_ADDR 0x120000 |
574 | ||
575 | #elif defined(CONFIG_SDCARD) | |
576 | /* | |
577 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
4d666683 SL |
578 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
579 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
8d67c368 SL |
580 | */ |
581 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
ef531c73 | 582 | #define CONFIG_SYS_CORTINA_FW_IN_MMC |
4d666683 SL |
583 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
584 | #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) | |
8d67c368 SL |
585 | |
586 | #elif defined(CONFIG_NAND) | |
587 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
ef531c73 | 588 | #define CONFIG_SYS_CORTINA_FW_IN_NAND |
4d666683 SL |
589 | #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
590 | #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
8d67c368 SL |
591 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
592 | /* | |
593 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
594 | * in two corenet boards, slave's ucode could be stored in master's memory | |
595 | * space, the address can be mapped from slave TLB->slave LAW-> | |
596 | * slave SRIO or PCIE outbound window->master inbound window-> | |
597 | * master LAW->the ucode address in master's memory space. | |
598 | */ | |
599 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
ef531c73 SL |
600 | #define CONFIG_SYS_CORTINA_FW_IN_REMOTE |
601 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 | |
8d67c368 SL |
602 | #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 |
603 | #else | |
604 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
ef531c73 SL |
605 | #define CONFIG_SYS_CORTINA_FW_IN_NOR |
606 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 | |
8d67c368 SL |
607 | #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 |
608 | #endif | |
609 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
610 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
611 | #endif /* CONFIG_NOBQFMAN */ | |
612 | ||
613 | #ifdef CONFIG_SYS_DPAA_FMAN | |
614 | #define CONFIG_FMAN_ENET | |
615 | #define CONFIG_PHYLIB_10G | |
747aedaf | 616 | #define CONFIG_PHY_AQUANTIA |
8d67c368 | 617 | #define CONFIG_PHY_CORTINA |
8d67c368 SL |
618 | #define CONFIG_PHY_REALTEK |
619 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
620 | #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ | |
621 | #define RGMII_PHY2_ADDR 0x02 | |
622 | #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ | |
623 | #define CORTINA_PHY_ADDR2 0x0d | |
624 | #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ | |
625 | #define FM1_10GEC4_PHY_ADDR 0x01 | |
626 | #endif | |
627 | ||
8d67c368 SL |
628 | #ifdef CONFIG_FMAN_ENET |
629 | #define CONFIG_MII /* MII PHY management */ | |
630 | #define CONFIG_ETHPRIME "FM1@DTSEC3" | |
631 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
632 | #endif | |
633 | ||
634 | /* | |
635 | * SATA | |
636 | */ | |
637 | #ifdef CONFIG_FSL_SATA_V2 | |
638 | #define CONFIG_LIBATA | |
639 | #define CONFIG_FSL_SATA | |
640 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
641 | #define CONFIG_SATA1 | |
642 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
643 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
644 | #define CONFIG_SATA2 | |
645 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
646 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
647 | #define CONFIG_LBA48 | |
8d67c368 SL |
648 | #endif |
649 | ||
650 | /* | |
651 | * USB | |
652 | */ | |
8850c5d5 | 653 | #ifdef CONFIG_USB_EHCI_HCD |
8d67c368 SL |
654 | #define CONFIG_USB_EHCI_FSL |
655 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
8d67c368 SL |
656 | #define CONFIG_HAS_FSL_DR_USB |
657 | #endif | |
658 | ||
659 | /* | |
660 | * SDHC | |
661 | */ | |
662 | #ifdef CONFIG_MMC | |
8d67c368 SL |
663 | #define CONFIG_FSL_ESDHC |
664 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
665 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
666 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
8d67c368 SL |
667 | #endif |
668 | ||
4feac1c6 SL |
669 | /* |
670 | * Dynamic MTD Partition support with mtdparts | |
671 | */ | |
e856bdcf | 672 | #ifdef CONFIG_MTD_NOR_FLASH |
4feac1c6 SL |
673 | #define CONFIG_MTD_DEVICE |
674 | #define CONFIG_MTD_PARTITIONS | |
4feac1c6 SL |
675 | #define CONFIG_FLASH_CFI_MTD |
676 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ | |
677 | "spi0=spife110000.1" | |
678 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ | |
679 | "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ | |
680 | "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ | |
681 | "1m(uboot),5m(kernel),128k(dtb),-(user)" | |
682 | #endif | |
683 | ||
8d67c368 SL |
684 | /* |
685 | * Environment | |
686 | */ | |
687 | ||
688 | /* | |
689 | * Command line configuration. | |
690 | */ | |
8d67c368 | 691 | #define CONFIG_CMD_REGINFO |
8d67c368 SL |
692 | |
693 | #ifdef CONFIG_PCI | |
694 | #define CONFIG_CMD_PCI | |
8d67c368 SL |
695 | #endif |
696 | ||
697 | /* | |
698 | * Miscellaneous configurable options | |
699 | */ | |
700 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
701 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
702 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
703 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8d67c368 SL |
704 | #ifdef CONFIG_CMD_KGDB |
705 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
706 | #else | |
707 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
708 | #endif | |
709 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
710 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
711 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
8d67c368 SL |
712 | |
713 | /* | |
714 | * For booting Linux, the board info and command line data | |
715 | * have to be in the first 64 MB of memory, since this is | |
716 | * the maximum mapped by the Linux kernel during initialization. | |
717 | */ | |
718 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
719 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
720 | ||
721 | #ifdef CONFIG_CMD_KGDB | |
722 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
723 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
724 | #endif | |
725 | ||
726 | /* | |
727 | * Environment Configuration | |
728 | */ | |
729 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
730 | #define CONFIG_BOOTFILE "uImage" | |
731 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ | |
732 | ||
733 | /* default location for tftp and bootm */ | |
734 | #define CONFIG_LOADADDR 1000000 | |
8d67c368 SL |
735 | #define __USB_PHY_TYPE utmi |
736 | ||
737 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
738 | "hwconfig=fsl_ddr:" \ | |
739 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
740 | "bank_intlv=auto;" \ | |
741 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
742 | "netdev=eth0\0" \ | |
743 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
744 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
745 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
746 | "protect off $ubootaddr +$filesize && " \ | |
747 | "erase $ubootaddr +$filesize && " \ | |
748 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
749 | "protect on $ubootaddr +$filesize && " \ | |
750 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
751 | "consoledev=ttyS0\0" \ | |
752 | "ramdiskaddr=2000000\0" \ | |
753 | "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ | |
b24a4f62 | 754 | "fdtaddr=1e00000\0" \ |
8d67c368 | 755 | "fdtfile=t2080rdb/t2080rdb.dtb\0" \ |
3246584d | 756 | "bdev=sda3\0" |
8d67c368 SL |
757 | |
758 | /* | |
759 | * For emulation this causes u-boot to jump to the start of the | |
760 | * proof point app code automatically | |
761 | */ | |
762 | #define CONFIG_PROOF_POINTS \ | |
763 | "setenv bootargs root=/dev/$bdev rw " \ | |
764 | "console=$consoledev,$baudrate $othbootargs;" \ | |
765 | "cpu 1 release 0x29000000 - - -;" \ | |
766 | "cpu 2 release 0x29000000 - - -;" \ | |
767 | "cpu 3 release 0x29000000 - - -;" \ | |
768 | "cpu 4 release 0x29000000 - - -;" \ | |
769 | "cpu 5 release 0x29000000 - - -;" \ | |
770 | "cpu 6 release 0x29000000 - - -;" \ | |
771 | "cpu 7 release 0x29000000 - - -;" \ | |
772 | "go 0x29000000" | |
773 | ||
774 | #define CONFIG_HVBOOT \ | |
775 | "setenv bootargs config-addr=0x60000000; " \ | |
776 | "bootm 0x01000000 - 0x00f00000" | |
777 | ||
778 | #define CONFIG_ALU \ | |
779 | "setenv bootargs root=/dev/$bdev rw " \ | |
780 | "console=$consoledev,$baudrate $othbootargs;" \ | |
781 | "cpu 1 release 0x01000000 - - -;" \ | |
782 | "cpu 2 release 0x01000000 - - -;" \ | |
783 | "cpu 3 release 0x01000000 - - -;" \ | |
784 | "cpu 4 release 0x01000000 - - -;" \ | |
785 | "cpu 5 release 0x01000000 - - -;" \ | |
786 | "cpu 6 release 0x01000000 - - -;" \ | |
787 | "cpu 7 release 0x01000000 - - -;" \ | |
788 | "go 0x01000000" | |
789 | ||
790 | #define CONFIG_LINUX \ | |
791 | "setenv bootargs root=/dev/ram rw " \ | |
792 | "console=$consoledev,$baudrate $othbootargs;" \ | |
793 | "setenv ramdiskaddr 0x02000000;" \ | |
794 | "setenv fdtaddr 0x00c00000;" \ | |
795 | "setenv loadaddr 0x1000000;" \ | |
796 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
797 | ||
798 | #define CONFIG_HDBOOT \ | |
799 | "setenv bootargs root=/dev/$bdev rw " \ | |
800 | "console=$consoledev,$baudrate $othbootargs;" \ | |
801 | "tftp $loadaddr $bootfile;" \ | |
802 | "tftp $fdtaddr $fdtfile;" \ | |
803 | "bootm $loadaddr - $fdtaddr" | |
804 | ||
805 | #define CONFIG_NFSBOOTCOMMAND \ | |
806 | "setenv bootargs root=/dev/nfs rw " \ | |
807 | "nfsroot=$serverip:$rootpath " \ | |
808 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
809 | "console=$consoledev,$baudrate $othbootargs;" \ | |
810 | "tftp $loadaddr $bootfile;" \ | |
811 | "tftp $fdtaddr $fdtfile;" \ | |
812 | "bootm $loadaddr - $fdtaddr" | |
813 | ||
814 | #define CONFIG_RAMBOOTCOMMAND \ | |
815 | "setenv bootargs root=/dev/ram rw " \ | |
816 | "console=$consoledev,$baudrate $othbootargs;" \ | |
817 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
818 | "tftp $loadaddr $bootfile;" \ | |
819 | "tftp $fdtaddr $fdtfile;" \ | |
820 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
821 | ||
822 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
823 | ||
8d67c368 | 824 | #include <asm/fsl_secure_boot.h> |
ef6c55a2 | 825 | |
8d67c368 | 826 | #endif /* __T2080RDB_H */ |