]>
Commit | Line | Data |
---|---|---|
0b2e13d9 CL |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * T4240 RDB board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_T4240RDB | |
0b2e13d9 CL |
14 | |
15 | #define CONFIG_FSL_SATA_V2 | |
16 | #define CONFIG_PCIE4 | |
17 | ||
18 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
19 | ||
20 | #ifdef CONFIG_RAMBOOT_PBL | |
0b2e13d9 CL |
21 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg |
22 | #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg | |
373762c3 CL |
23 | #ifndef CONFIG_SDCARD |
24 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
25 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
26 | #else | |
373762c3 CL |
27 | #define CONFIG_SPL_FLUSH_IMAGE |
28 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
373762c3 CL |
29 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
30 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
31 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
32 | #define CONFIG_SPL_PAD_TO 0x40000 | |
33 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
34 | #define RESET_VECTOR_OFFSET 0x27FFC | |
35 | #define BOOT_PAGE_OFFSET 0x27000 | |
36 | ||
37 | #ifdef CONFIG_SDCARD | |
38 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
373762c3 CL |
39 | #define CONFIG_SPL_MMC_MINIMAL |
40 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
41 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 | |
42 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 | |
43 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
44 | #ifndef CONFIG_SPL_BUILD | |
45 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
46 | #endif | |
47 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
48 | #define CONFIG_SPL_MMC_BOOT | |
49 | #endif | |
50 | ||
51 | #ifdef CONFIG_SPL_BUILD | |
52 | #define CONFIG_SPL_SKIP_RELOCATE | |
53 | #define CONFIG_SPL_COMMON_INIT_DDR | |
54 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
55 | #define CONFIG_SYS_NO_FLASH | |
56 | #endif | |
57 | ||
0b2e13d9 | 58 | #endif |
373762c3 | 59 | #endif /* CONFIG_RAMBOOT_PBL */ |
0b2e13d9 CL |
60 | |
61 | #define CONFIG_DDR_ECC | |
62 | ||
63 | #define CONFIG_CMD_REGINFO | |
64 | ||
65 | /* High Level Configuration Options */ | |
66 | #define CONFIG_BOOKE | |
67 | #define CONFIG_E500 /* BOOKE e500 family */ | |
68 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
69 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
70 | #define CONFIG_MP /* support multiple processors */ | |
71 | ||
72 | #ifndef CONFIG_SYS_TEXT_BASE | |
73 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
74 | #endif | |
75 | ||
76 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
77 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
78 | #endif | |
79 | ||
80 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
81 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
82 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
737537ef | 83 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
0b2e13d9 | 84 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
b38eaec5 RD |
85 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
86 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
87 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
0b2e13d9 CL |
88 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
89 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
90 | ||
91 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
92 | ||
93 | #define CONFIG_ENV_OVERWRITE | |
94 | ||
95 | /* | |
96 | * These can be toggled for performance analysis, otherwise use default. | |
97 | */ | |
98 | #define CONFIG_SYS_CACHE_STASHING | |
99 | #define CONFIG_BTB /* toggle branch predition */ | |
100 | #ifdef CONFIG_DDR_ECC | |
101 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
102 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
103 | #endif | |
104 | ||
105 | #define CONFIG_ENABLE_36BIT_PHYS | |
106 | ||
107 | #define CONFIG_ADDR_MAP | |
108 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
109 | ||
110 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
111 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
112 | #define CONFIG_SYS_ALT_MEMTEST | |
113 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
114 | ||
115 | /* | |
116 | * Config the L3 Cache as L3 SRAM | |
117 | */ | |
373762c3 CL |
118 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
119 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
120 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
121 | #ifdef CONFIG_RAMBOOT_PBL | |
122 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
123 | #endif | |
124 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
125 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
126 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
127 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
0b2e13d9 CL |
128 | |
129 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
130 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
131 | ||
132 | /* | |
133 | * DDR Setup | |
134 | */ | |
135 | #define CONFIG_VERY_BIG_RAM | |
136 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
137 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
138 | ||
139 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ | |
140 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
141 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
142 | #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE | |
143 | ||
144 | #define CONFIG_DDR_SPD | |
145 | #define CONFIG_SYS_FSL_DDR3 | |
146 | ||
0b2e13d9 CL |
147 | /* |
148 | * IFC Definitions | |
149 | */ | |
150 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
151 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
152 | ||
373762c3 CL |
153 | #ifdef CONFIG_SPL_BUILD |
154 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
155 | #else | |
0b2e13d9 | 156 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
373762c3 | 157 | #endif |
0b2e13d9 CL |
158 | |
159 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
160 | #define CONFIG_MISC_INIT_R | |
161 | ||
162 | #define CONFIG_HWCONFIG | |
163 | ||
164 | /* define to use L1 as initial stack */ | |
165 | #define CONFIG_L1_INIT_RAM | |
166 | #define CONFIG_SYS_INIT_RAM_LOCK | |
167 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
168 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 169 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
0b2e13d9 CL |
170 | /* The assembler doesn't like typecast */ |
171 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
172 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
173 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
174 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
175 | ||
176 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
177 | GENERATED_GBL_DATA_SIZE) | |
178 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
179 | ||
373762c3 | 180 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
0b2e13d9 CL |
181 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
182 | ||
183 | /* Serial Port - controlled on board with jumper J8 | |
184 | * open - index 2 | |
185 | * shorted - index 1 | |
186 | */ | |
187 | #define CONFIG_CONS_INDEX 1 | |
0b2e13d9 CL |
188 | #define CONFIG_SYS_NS16550_SERIAL |
189 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
190 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
191 | ||
192 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
193 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
194 | ||
195 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
196 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
197 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
198 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
199 | ||
0b2e13d9 CL |
200 | /* I2C */ |
201 | #define CONFIG_SYS_I2C | |
202 | #define CONFIG_SYS_I2C_FSL | |
203 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
204 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
205 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
206 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
207 | ||
208 | /* | |
209 | * General PCI | |
210 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
211 | */ | |
212 | ||
213 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
214 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
215 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
216 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
217 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
218 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
219 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
220 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
221 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
222 | ||
223 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
224 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
225 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
226 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
227 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
228 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
229 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
230 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
231 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
232 | ||
233 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
234 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
235 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
236 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
237 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
238 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
239 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
240 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
241 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
242 | ||
243 | /* controller 4, Base address 203000 */ | |
244 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
245 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
246 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
247 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
248 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
249 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
250 | ||
251 | #ifdef CONFIG_PCI | |
252 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
0b2e13d9 | 253 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0b2e13d9 CL |
254 | |
255 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
256 | #define CONFIG_DOS_PARTITION | |
257 | #endif /* CONFIG_PCI */ | |
258 | ||
259 | /* SATA */ | |
260 | #ifdef CONFIG_FSL_SATA_V2 | |
261 | #define CONFIG_LIBATA | |
262 | #define CONFIG_FSL_SATA | |
263 | ||
264 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
265 | #define CONFIG_SATA1 | |
266 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
267 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
268 | #define CONFIG_SATA2 | |
269 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
270 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
271 | ||
272 | #define CONFIG_LBA48 | |
273 | #define CONFIG_CMD_SATA | |
274 | #define CONFIG_DOS_PARTITION | |
0b2e13d9 CL |
275 | #endif |
276 | ||
277 | #ifdef CONFIG_FMAN_ENET | |
278 | #define CONFIG_MII /* MII PHY management */ | |
279 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
280 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
281 | #endif | |
282 | ||
283 | /* | |
284 | * Environment | |
285 | */ | |
286 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
287 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
288 | ||
289 | /* | |
290 | * Command line configuration. | |
291 | */ | |
0b2e13d9 | 292 | #define CONFIG_CMD_ERRATA |
0b2e13d9 | 293 | #define CONFIG_CMD_IRQ |
0b2e13d9 CL |
294 | |
295 | #ifdef CONFIG_PCI | |
296 | #define CONFIG_CMD_PCI | |
0b2e13d9 CL |
297 | #endif |
298 | ||
299 | /* | |
300 | * Miscellaneous configurable options | |
301 | */ | |
302 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
303 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
304 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
305 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
306 | #ifdef CONFIG_CMD_KGDB | |
307 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
308 | #else | |
309 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
310 | #endif | |
311 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
312 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
313 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
314 | ||
315 | /* | |
316 | * For booting Linux, the board info and command line data | |
317 | * have to be in the first 64 MB of memory, since this is | |
318 | * the maximum mapped by the Linux kernel during initialization. | |
319 | */ | |
320 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
321 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
322 | ||
323 | #ifdef CONFIG_CMD_KGDB | |
324 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
325 | #endif | |
326 | ||
327 | /* | |
328 | * Environment Configuration | |
329 | */ | |
330 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
331 | #define CONFIG_BOOTFILE "uImage" | |
332 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
333 | ||
334 | /* default location for tftp and bootm */ | |
335 | #define CONFIG_LOADADDR 1000000 | |
336 | ||
0b2e13d9 CL |
337 | #define CONFIG_BAUDRATE 115200 |
338 | ||
339 | #define CONFIG_HVBOOT \ | |
340 | "setenv bootargs config-addr=0x60000000; " \ | |
341 | "bootm 0x01000000 - 0x00f00000" | |
342 | ||
343 | #ifdef CONFIG_SYS_NO_FLASH | |
344 | #ifndef CONFIG_RAMBOOT_PBL | |
345 | #define CONFIG_ENV_IS_NOWHERE | |
346 | #endif | |
347 | #else | |
348 | #define CONFIG_FLASH_CFI_DRIVER | |
349 | #define CONFIG_SYS_FLASH_CFI | |
350 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
351 | #endif | |
352 | ||
353 | #if defined(CONFIG_SPIFLASH) | |
354 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
355 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
356 | #define CONFIG_ENV_SPI_BUS 0 | |
357 | #define CONFIG_ENV_SPI_CS 0 | |
358 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
359 | #define CONFIG_ENV_SPI_MODE 0 | |
360 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
361 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
362 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
363 | #elif defined(CONFIG_SDCARD) | |
364 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
365 | #define CONFIG_ENV_IS_IN_MMC | |
366 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
367 | #define CONFIG_ENV_SIZE 0x2000 | |
373762c3 | 368 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
0b2e13d9 CL |
369 | #elif defined(CONFIG_NAND) |
370 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
371 | #define CONFIG_ENV_IS_IN_NAND | |
372 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
373 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
374 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
375 | #define CONFIG_ENV_SIZE 0x2000 | |
376 | #else | |
377 | #define CONFIG_ENV_IS_IN_FLASH | |
378 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
379 | #define CONFIG_ENV_SIZE 0x2000 | |
380 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
381 | #endif | |
382 | ||
383 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
384 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
385 | ||
386 | #ifndef __ASSEMBLY__ | |
387 | unsigned long get_board_sys_clk(void); | |
388 | unsigned long get_board_ddr_clk(void); | |
389 | #endif | |
390 | ||
391 | /* | |
392 | * DDR Setup | |
393 | */ | |
394 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
395 | #define SPD_EEPROM_ADDRESS1 0x52 | |
396 | #define SPD_EEPROM_ADDRESS2 0x54 | |
397 | #define SPD_EEPROM_ADDRESS3 0x56 | |
398 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ | |
399 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
400 | ||
401 | /* | |
402 | * IFC Definitions | |
403 | */ | |
404 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
405 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
406 | + 0x8000000) | \ | |
407 | CSPR_PORT_SIZE_16 | \ | |
408 | CSPR_MSEL_NOR | \ | |
409 | CSPR_V) | |
410 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
411 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
412 | CSPR_PORT_SIZE_16 | \ | |
413 | CSPR_MSEL_NOR | \ | |
414 | CSPR_V) | |
415 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
416 | /* NOR Flash Timing Params */ | |
417 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
418 | ||
419 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
420 | FTIM0_NOR_TEADC(0x5) | \ | |
421 | FTIM0_NOR_TEAHC(0x5)) | |
422 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
423 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
424 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
425 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
426 | FTIM2_NOR_TCH(0x4) | \ | |
427 | FTIM2_NOR_TWPH(0x0E) | \ | |
428 | FTIM2_NOR_TWP(0x1c)) | |
429 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
430 | ||
431 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
432 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
433 | ||
434 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
435 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
436 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
437 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
438 | ||
439 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
440 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
441 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
442 | ||
443 | /* NAND Flash on IFC */ | |
444 | #define CONFIG_NAND_FSL_IFC | |
445 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
446 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
447 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
448 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
449 | ||
450 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
451 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
452 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
453 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
454 | | CSPR_V) | |
455 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
456 | ||
457 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
458 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
459 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
460 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
461 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
462 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
463 | | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ | |
464 | ||
465 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
466 | ||
467 | /* ONFI NAND Flash mode0 Timing Params */ | |
468 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
469 | FTIM0_NAND_TWP(0x18) | \ | |
470 | FTIM0_NAND_TWCHT(0x07) | \ | |
471 | FTIM0_NAND_TWH(0x0a)) | |
472 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
473 | FTIM1_NAND_TWBE(0x39) | \ | |
474 | FTIM1_NAND_TRR(0x0e) | \ | |
475 | FTIM1_NAND_TRP(0x18)) | |
476 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
477 | FTIM2_NAND_TREH(0x0a) | \ | |
478 | FTIM2_NAND_TWHRE(0x1e)) | |
479 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
480 | ||
481 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
482 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
483 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
0b2e13d9 CL |
484 | #define CONFIG_CMD_NAND |
485 | ||
486 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
487 | ||
488 | #if defined(CONFIG_NAND) | |
489 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
490 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
491 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
492 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
493 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
494 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
495 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
496 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
497 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
498 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR | |
499 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
500 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
501 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
502 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
503 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
504 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
505 | #else | |
506 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
507 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
508 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
509 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
510 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
511 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
512 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
513 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
514 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
515 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
516 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
517 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
518 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
519 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
520 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
521 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
522 | #endif | |
523 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
524 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
525 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
526 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
527 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
528 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
529 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
530 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
531 | ||
ab06b236 CL |
532 | /* CPLD on IFC */ |
533 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
534 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
535 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
536 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
537 | | CSPR_PORT_SIZE_8 \ | |
538 | | CSPR_MSEL_GPCM \ | |
539 | | CSPR_V) | |
540 | ||
541 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
542 | #define CONFIG_SYS_CSOR3 0x0 | |
543 | ||
544 | /* CPLD Timing parameters for IFC CS3 */ | |
545 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
546 | FTIM0_GPCM_TEADC(0x0e) | \ | |
547 | FTIM0_GPCM_TEAHC(0x0e)) | |
548 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
549 | FTIM1_GPCM_TRAD(0x1f)) | |
550 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
1b5c2b51 | 551 | FTIM2_GPCM_TCH(0x8) | \ |
ab06b236 CL |
552 | FTIM2_GPCM_TWP(0x1f)) |
553 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
554 | ||
0b2e13d9 CL |
555 | #if defined(CONFIG_RAMBOOT_PBL) |
556 | #define CONFIG_SYS_RAMBOOT | |
557 | #endif | |
558 | ||
0b2e13d9 CL |
559 | /* I2C */ |
560 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ | |
561 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ | |
562 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
563 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ | |
564 | ||
565 | #define I2C_MUX_CH_DEFAULT 0x8 | |
566 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
567 | #define I2C_MUX_CH_VSC3316_FS 0xc | |
568 | #define I2C_MUX_CH_VSC3316_BS 0xd | |
569 | ||
570 | /* Voltage monitor on channel 2*/ | |
571 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
572 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
573 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
574 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
575 | ||
2f66a828 YZ |
576 | #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" |
577 | #ifndef CONFIG_SPL_BUILD | |
578 | #define CONFIG_VID | |
579 | #endif | |
580 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
581 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
582 | /* The lowest and highest voltage allowed for T4240RDB */ | |
583 | #define VDD_MV_MIN 819 | |
584 | #define VDD_MV_MAX 1212 | |
585 | ||
0b2e13d9 CL |
586 | /* |
587 | * eSPI - Enhanced SPI | |
588 | */ | |
0b2e13d9 CL |
589 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
590 | #define CONFIG_SF_DEFAULT_MODE 0 | |
591 | ||
0b2e13d9 CL |
592 | /* Qman/Bman */ |
593 | #ifndef CONFIG_NOBQFMAN | |
594 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
595 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 | |
596 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
597 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
598 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
599 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
600 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
601 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
602 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
603 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
604 | CONFIG_SYS_BMAN_CENA_SIZE) | |
605 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
606 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
0b2e13d9 CL |
607 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
608 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
609 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
610 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
611 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
612 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
613 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
614 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
615 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
616 | CONFIG_SYS_QMAN_CENA_SIZE) | |
617 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
618 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
0b2e13d9 CL |
619 | |
620 | #define CONFIG_SYS_DPAA_FMAN | |
621 | #define CONFIG_SYS_DPAA_PME | |
622 | #define CONFIG_SYS_PMAN | |
623 | #define CONFIG_SYS_DPAA_DCE | |
624 | #define CONFIG_SYS_DPAA_RMAN | |
625 | #define CONFIG_SYS_INTERLAKEN | |
626 | ||
627 | /* Default address of microcode for the Linux Fman driver */ | |
628 | #if defined(CONFIG_SPIFLASH) | |
629 | /* | |
630 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
631 | * env, so we got 0x110000. | |
632 | */ | |
633 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
634 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 | |
635 | #elif defined(CONFIG_SDCARD) | |
636 | /* | |
637 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
373762c3 CL |
638 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
639 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
0b2e13d9 CL |
640 | */ |
641 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
373762c3 | 642 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
0b2e13d9 CL |
643 | #elif defined(CONFIG_NAND) |
644 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
645 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
646 | #else | |
647 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
648 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 | |
649 | #endif | |
650 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
651 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
652 | #endif /* CONFIG_NOBQFMAN */ | |
653 | ||
654 | #ifdef CONFIG_SYS_DPAA_FMAN | |
655 | #define CONFIG_FMAN_ENET | |
656 | #define CONFIG_PHYLIB_10G | |
657 | #define CONFIG_PHY_VITESSE | |
658 | #define CONFIG_PHY_CORTINA | |
a8efe79c | 659 | #define CONFIG_SYS_CORTINA_FW_IN_NOR |
0b2e13d9 CL |
660 | #define CONFIG_CORTINA_FW_ADDR 0xefe00000 |
661 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
662 | #define CONFIG_PHY_TERANETICS | |
663 | #define SGMII_PHY_ADDR1 0x0 | |
664 | #define SGMII_PHY_ADDR2 0x1 | |
665 | #define SGMII_PHY_ADDR3 0x2 | |
666 | #define SGMII_PHY_ADDR4 0x3 | |
667 | #define SGMII_PHY_ADDR5 0x4 | |
668 | #define SGMII_PHY_ADDR6 0x5 | |
669 | #define SGMII_PHY_ADDR7 0x6 | |
670 | #define SGMII_PHY_ADDR8 0x7 | |
671 | #define FM1_10GEC1_PHY_ADDR 0x10 | |
672 | #define FM1_10GEC2_PHY_ADDR 0x11 | |
673 | #define FM2_10GEC1_PHY_ADDR 0x12 | |
674 | #define FM2_10GEC2_PHY_ADDR 0x13 | |
675 | #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR | |
676 | #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR | |
677 | #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR | |
678 | #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR | |
679 | #endif | |
680 | ||
0b2e13d9 CL |
681 | /* SATA */ |
682 | #ifdef CONFIG_FSL_SATA_V2 | |
683 | #define CONFIG_LIBATA | |
684 | #define CONFIG_FSL_SATA | |
685 | ||
686 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
687 | #define CONFIG_SATA1 | |
688 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
689 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
690 | #define CONFIG_SATA2 | |
691 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
692 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
693 | ||
694 | #define CONFIG_LBA48 | |
695 | #define CONFIG_CMD_SATA | |
696 | #define CONFIG_DOS_PARTITION | |
0b2e13d9 CL |
697 | #endif |
698 | ||
699 | #ifdef CONFIG_FMAN_ENET | |
700 | #define CONFIG_MII /* MII PHY management */ | |
701 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
702 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
703 | #endif | |
704 | ||
705 | /* | |
706 | * USB | |
707 | */ | |
0b2e13d9 CL |
708 | #define CONFIG_USB_EHCI |
709 | #define CONFIG_USB_EHCI_FSL | |
710 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
0b2e13d9 CL |
711 | #define CONFIG_HAS_FSL_DR_USB |
712 | ||
713 | #define CONFIG_MMC | |
714 | ||
715 | #ifdef CONFIG_MMC | |
716 | #define CONFIG_FSL_ESDHC | |
717 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
718 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
0b2e13d9 | 719 | #define CONFIG_GENERIC_MMC |
0b2e13d9 | 720 | #define CONFIG_DOS_PARTITION |
929dfdc2 | 721 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
0b2e13d9 CL |
722 | #endif |
723 | ||
737537ef RG |
724 | /* Hash command with SHA acceleration supported in hardware */ |
725 | #ifdef CONFIG_FSL_CAAM | |
726 | #define CONFIG_CMD_HASH | |
727 | #define CONFIG_SHA_HW_ACCEL | |
728 | #endif | |
729 | ||
0b2e13d9 CL |
730 | |
731 | #define __USB_PHY_TYPE utmi | |
732 | ||
733 | /* | |
734 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be | |
735 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way | |
736 | * interleaving. It can be cacheline, page, bank, superbank. | |
737 | * See doc/README.fsl-ddr for details. | |
738 | */ | |
1a344456 | 739 | #ifdef CONFIG_PPC_T4240 |
0b2e13d9 | 740 | #define CTRL_INTLV_PREFERED 3way_4KB |
1a344456 CL |
741 | #else |
742 | #define CTRL_INTLV_PREFERED cacheline | |
743 | #endif | |
0b2e13d9 CL |
744 | |
745 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
746 | "hwconfig=fsl_ddr:" \ | |
747 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
748 | "bank_intlv=auto;" \ | |
749 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
750 | "netdev=eth0\0" \ | |
751 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
752 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
753 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
754 | "protect off $ubootaddr +$filesize && " \ | |
755 | "erase $ubootaddr +$filesize && " \ | |
756 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
757 | "protect on $ubootaddr +$filesize && " \ | |
758 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
759 | "consoledev=ttyS0\0" \ | |
760 | "ramdiskaddr=2000000\0" \ | |
761 | "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ | |
b24a4f62 | 762 | "fdtaddr=1e00000\0" \ |
0b2e13d9 CL |
763 | "fdtfile=t4240rdb/t4240rdb.dtb\0" \ |
764 | "bdev=sda3\0" | |
765 | ||
766 | #define CONFIG_HVBOOT \ | |
767 | "setenv bootargs config-addr=0x60000000; " \ | |
768 | "bootm 0x01000000 - 0x00f00000" | |
769 | ||
770 | #define CONFIG_LINUX \ | |
771 | "setenv bootargs root=/dev/ram rw " \ | |
772 | "console=$consoledev,$baudrate $othbootargs;" \ | |
773 | "setenv ramdiskaddr 0x02000000;" \ | |
774 | "setenv fdtaddr 0x00c00000;" \ | |
775 | "setenv loadaddr 0x1000000;" \ | |
776 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
777 | ||
778 | #define CONFIG_HDBOOT \ | |
779 | "setenv bootargs root=/dev/$bdev rw " \ | |
780 | "console=$consoledev,$baudrate $othbootargs;" \ | |
781 | "tftp $loadaddr $bootfile;" \ | |
782 | "tftp $fdtaddr $fdtfile;" \ | |
783 | "bootm $loadaddr - $fdtaddr" | |
784 | ||
785 | #define CONFIG_NFSBOOTCOMMAND \ | |
786 | "setenv bootargs root=/dev/nfs rw " \ | |
787 | "nfsroot=$serverip:$rootpath " \ | |
788 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
789 | "console=$consoledev,$baudrate $othbootargs;" \ | |
790 | "tftp $loadaddr $bootfile;" \ | |
791 | "tftp $fdtaddr $fdtfile;" \ | |
792 | "bootm $loadaddr - $fdtaddr" | |
793 | ||
794 | #define CONFIG_RAMBOOTCOMMAND \ | |
795 | "setenv bootargs root=/dev/ram rw " \ | |
796 | "console=$consoledev,$baudrate $othbootargs;" \ | |
797 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
798 | "tftp $loadaddr $bootfile;" \ | |
799 | "tftp $fdtaddr $fdtfile;" \ | |
800 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
801 | ||
802 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
803 | ||
804 | #include <asm/fsl_secure_boot.h> | |
805 | ||
0b2e13d9 | 806 | #endif /* __CONFIG_H */ |