[people/ms/u-boot.git] / include / configs / TASREG.h

/*
 * Configuation settings for the esd TASREG board.
 *
 * (C) Copyright 2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _TASREG_H
#define _TASREG_H

#ifndef __ASSEMBLY__
#include <asm/m5249.h>
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF52x2			/* define processor family */
#define CONFIG_M5249			/* define processor type */

#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		19200

#undef  CONFIG_WATCHDOG

#undef CONFIG_MONITOR_IS_IN_RAM	              /* no pre-loader required!!! ;-) */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C

#undef CONFIG_CMD_NET


#define CONFIG_BOOTDELAY	3

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */

#define CONFIG_SYS_LOAD_ADDR	        0x200000	/* default load address */

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

/*
 * Clock configuration: enable only one of the following options
 */

#if 0 /* this setting will run the cpu at 11MHz */
#define CONFIG_SYS_PLL_BYPASS          1                /* bypass PLL for test purpose */
#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
#define CONFIG_SYS_CLK		        11289600         /* PLL bypass                  */
#endif

#if 0 /* this setting will run the cpu at 70MHz */
#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
#define CONFIG_SYS_CLK		        72185018         /* The next lower speed        */
#endif

#if 1 /* this setting will run the cpu at 140MHz */
#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
#define	CONFIG_SYS_CLK		        132025600        /* MCF5249 can run at 140MHz   */
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define	CONFIG_SYS_MBAR2	        0x80000000

/*-----------------------------------------------------------------------
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	100000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F

#if 0 /* push-pull */
#define	SDA	        0x00800000
#define	SCL	        0x00000008
#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
#define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
#define	I2C_READ	((IN1&SDA)?1:0)
#define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
#define	I2C_SCL(x)	{if(x)OUT0|=SCL;else OUT0&=~SCL;}
#define	I2C_DELAY	{udelay(5);}
#define	I2C_ACTIVE	{DIR1|=SDA;}
#define	I2C_TRISTATE    {DIR1&=~SDA;}
#else /* open-collector */
#define	SDA	        0x00800000
#define	SCL	        0x00000008
#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
#define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
#define	I2C_READ	((IN1&SDA)?1:0)
#define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
#define	I2C_SCL(x)	{if(x)DIR0&=~SCL;else DIR0|=SCL;}
#define	I2C_DELAY	{udelay(5);}
#define	I2C_ACTIVE	{DIR1|=SDA;}
#define	I2C_TRISTATE    {DIR1&=~SDA;}
#endif

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address	*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
/*
 * The Catalyst CAT24WC32 has 32 byte page write mode using
 * last 5 bits of the address
 */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#if 0 /* test-only */
#define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */

/* CS0 - AMD Flash, address 0xffc00000 */
#define	CONFIG_SYS_CS0_BASE		0xffc00000
#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */

/* CS1 - FPGA, address 0xe0000000 */
#define	CONFIG_SYS_CS1_BASE		0xe0000000
#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define	CONFIG_SYS_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
#define	CONFIG_SYS_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
#define	CONFIG_SYS_GPIO_EN             0x00000008      /* Set gpio output enable       */
#define	CONFIG_SYS_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
#define	CONFIG_SYS_GPIO_OUT            0x00000008      /* Set outputs to default state */
#define	CONFIG_SYS_GPIO1_OUT           0x00c70000      /* Set outputs to default state */

#define CONFIG_SYS_GPIO1_LED           0x00400000      /* user led                     */

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CONFIG_SYS_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */

#endif	/* _TASREG_H */
Commit	Line	Data
a20b27a3 SR	1	/*
	2	* Configuation settings for the esd TASREG board.
	3	*
	4	* (C) Copyright 2004
	5	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
a20b27a3 SR	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _TASREG_H
	15	#define _TASREG_H
	16
	17	#ifndef __ASSEMBLY__
	18	#include <asm/m5249.h>
	19	#endif
	20
	21	/*
	22	* High Level Configuration Options
	23	* (easy to change)
	24	*/
	25	#define CONFIG_MCF52x2 /* define processor family */
	26	#define CONFIG_M5249 /* define processor type */
	27
	28	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	29
aa93d859 TL	30	#define CONFIG_MCFTMR
	31
	32	#define CONFIG_MCFUART
6d0f6bcf	33	#define CONFIG_SYS_UART_PORT (0)
a20b27a3	34	#define CONFIG_BAUDRATE 19200
a20b27a3 SR	35
	36	#undef CONFIG_WATCHDOG
	37
	38	#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
	39
a5562901	40
a1aa0bb5 JL	41	/*
	42	* BOOTP options
	43	*/
	44	#define CONFIG_BOOTP_BOOTFILESIZE
	45	#define CONFIG_BOOTP_BOOTPATH
	46	#define CONFIG_BOOTP_GATEWAY
	47	#define CONFIG_BOOTP_HOSTNAME
	48
	49
a5562901 JL	50	/*
	51	* Command line configuration.
	52	*/
	53	#include <config_cmd_default.h>
	54
	55	#define CONFIG_CMD_BSP
	56	#define CONFIG_CMD_EEPROM
	57	#define CONFIG_CMD_I2C
	58
	59	#undef CONFIG_CMD_NET
	60
	61
a20b27a3 SR	62	#define CONFIG_BOOTDELAY 3
a20b27a3 SR	63
6d0f6bcf	64	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a20b27a3	65
a5562901	66	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	67	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a20b27a3	68	#else
6d0f6bcf	69	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a20b27a3	70	#endif
6d0f6bcf JCPV	71	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	72	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	73	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a20b27a3	74
6d0f6bcf JCPV	75	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
6d0f6bcf JCPV	76	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
a20b27a3 SR	77	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	78	#define CONFIG_LOOPW 1 /* enable loopw command */
	79	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	80
6d0f6bcf	81	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
a20b27a3	82
6d0f6bcf JCPV	83	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	84	#define CONFIG_SYS_MEMTEST_END 0x380000
a20b27a3	85
a20b27a3 SR	86	/*
	87	* Clock configuration: enable only one of the following options
	88	*/
	89
	90	#if 0 /* this setting will run the cpu at 11MHz */
6d0f6bcf JCPV	91	#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */
	92	#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
	93	#define CONFIG_SYS_CLK 11289600 /* PLL bypass */
a20b27a3 SR	94	#endif
	95
	96	#if 0 /* this setting will run the cpu at 70MHz */
6d0f6bcf JCPV	97	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	98	#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
	99	#define CONFIG_SYS_CLK 72185018 /* The next lower speed */
a20b27a3 SR	100	#endif
	101
	102	#if 1 /* this setting will run the cpu at 140MHz */
6d0f6bcf JCPV	103	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	104	#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
	105	#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
a20b27a3 SR	106	#endif
	107
	108	/*
	109	* Low Level Configuration Settings
	110	* (address mappings, register initial values, etc.)
	111	* You should know what you are doing if you make changes here.
	112	*/
	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	115	#define CONFIG_SYS_MBAR2 0x80000000
a20b27a3 SR	116
	117	/*-----------------------------------------------------------------------
	118	* I2C
	119	*/
ea818dbb HS	120	#define CONFIG_SYS_I2C
	121	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	122	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
	123	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
a20b27a3	124
a20b27a3 SR	125	#if 0 /* push-pull */
	126	#define SDA 0x00800000
	127	#define SCL 0x00000008
6d0f6bcf JCPV	128	#define DIR0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
	129	#define DIR1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
	130	#define OUT0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
	131	#define OUT1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
	132	#define IN0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
	133	#define IN1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
a20b27a3 SR	134	#define I2C_INIT {OUT1\|=SDA;OUT0\|=SCL;}
	135	#define I2C_READ ((IN1&SDA)?1:0)
	136	#define I2C_SDA(x) {if(x)OUT1\|=SDA;else OUT1&=~SDA;}
	137	#define I2C_SCL(x) {if(x)OUT0\|=SCL;else OUT0&=~SCL;}
	138	#define I2C_DELAY {udelay(5);}
	139	#define I2C_ACTIVE {DIR1\|=SDA;}
	140	#define I2C_TRISTATE {DIR1&=~SDA;}
	141	#else /* open-collector */
	142	#define SDA 0x00800000
	143	#define SCL 0x00000008
6d0f6bcf JCPV	144	#define DIR0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
	145	#define DIR1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
	146	#define OUT0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
	147	#define OUT1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
	148	#define IN0 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
	149	#define IN1 ((volatile ulong)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
a20b27a3 SR	150	#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
	151	#define I2C_READ ((IN1&SDA)?1:0)
	152	#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1\|=SDA;}
	153	#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0\|=SCL;}
	154	#define I2C_DELAY {udelay(5);}
	155	#define I2C_ACTIVE {DIR1\|=SDA;}
	156	#define I2C_TRISTATE {DIR1&=~SDA;}
	157	#endif
ea818dbb HS	158
	159	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
	160	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	161	/* mask of address bits that overflow into the "EEPROM chip address" */
	162	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
	163	/*
	164	* The Catalyst CAT24WC32 has 32 byte page write mode using
	165	* last 5 bits of the address
	166	*/
	167	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	168	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
a20b27a3 SR	169
	170	/*-----------------------------------------------------------------------
	171	* Definitions for initial stack pointer and data area (in DPRAM)
	172	*/
6d0f6bcf	173	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	174	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	175	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	176	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a20b27a3	177
5a1aceb0	178	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	179	#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
	180	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
	181	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
a20b27a3 SR	182
	183	/*-----------------------------------------------------------------------
	184	* Start addresses for the final memory configuration
	185	* (Set up by the startup code)
6d0f6bcf	186	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a20b27a3	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	189	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	190	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
a20b27a3 SR	191
	192	#if 0 /* test-only */
	193	#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
	194	#endif
	195
6d0f6bcf	196	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a20b27a3	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_MONITOR_LEN 0x20000
	199	#define CONFIG_SYS_MALLOC_LEN (1 * 10241024) / Reserve 1 MB for malloc() */
	200	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a20b27a3 SR	201
	202	/*
	203	* For booting Linux, the board info and command line data
	204	* have to be in the first 8 MB of memory, since this is
	205	* the maximum mapped by the Linux kernel during initialization ??
	206	*/
6d0f6bcf	207	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a20b27a3 SR	208
	209	/*-----------------------------------------------------------------------
	210	* FLASH organization
	211	*/
6d0f6bcf JCPV	212	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	213	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
a20b27a3	214
6d0f6bcf JCPV	215	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	216	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
a20b27a3	217
6d0f6bcf JCPV	218	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	219	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	220	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
a20b27a3 SR	221	/*
	222	* The following defines are added for buggy IOP480 byte interface.
	223	* All other boards should use the standard values (CPCI405 etc.)
	224	*/
6d0f6bcf JCPV	225	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	226	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	227	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
a20b27a3	228
6d0f6bcf	229	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
a20b27a3 SR	230
	231	/*-----------------------------------------------------------------------
	232	* Cache Configuration
	233	*/
6d0f6bcf	234	#define CONFIG_SYS_CACHELINE_SIZE 16
a20b27a3	235
dd9f054e	236	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	237	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	238	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	239	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	240	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	241	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	242	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	243	CF_ACR_EN \| CF_ACR_SM_ALL)
	244	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	245	CF_CACR_DBWE)
	246
a20b27a3 SR	247	/*-----------------------------------------------------------------------
	248	* Memory bank definitions
	249	*/
	250
	251	/* CS0 - AMD Flash, address 0xffc00000 */
012522fe TL	252	#define CONFIG_SYS_CS0_BASE 0xffc00000
012522fe TL	253	#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
a20b27a3	254	/ Note: There is a CSMR0/DRAM vector problem, need to disable C/I */
012522fe	255	#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
a20b27a3 SR	256
a20b27a3 SR	257	/* CS1 - FPGA, address 0xe0000000 */
012522fe TL	258	#define CONFIG_SYS_CS1_BASE 0xe0000000
	259	#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
	260	#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
a20b27a3 SR	261
	262	/*-----------------------------------------------------------------------
	263	* Port configuration
	264	*/
6d0f6bcf JCPV	265	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	266	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
	267	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	268	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	269	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	270	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
a20b27a3	271
6d0f6bcf	272	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a20b27a3 SR	273
	274	/*-----------------------------------------------------------------------
	275	* FPGA stuff
	276	*/
6d0f6bcf JCPV	277	#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
6d0f6bcf JCPV	278	#define CONFIG_SYS_FPGA_MAX_SIZE 5121024 / 512kByte is enough for XC2S200*/
a20b27a3 SR	279
a20b27a3 SR	280	/* FPGA program pin configuration */
6d0f6bcf JCPV	281	#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
	282	#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
	283	#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
	284	#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
	285	#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
a20b27a3 SR	286
a20b27a3 SR	287	#endif /* _TASREG_H */