[people/ms/u-boot.git] / include / configs / TQM5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#ifdef CONFIG_STK52XX
#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
#define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_STK52XX */

#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#ifdef CONFIG_STK52XX
#define CONFIG_PCI		1
#elif
#define CONFIG_PCI		0
#endif
#define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW	1 */

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#ifdef CONFIG_STK52XX
#define ADD_PCI_CMD		CFG_CMD_PCI
#elif
#define ADD_PCI_CMD		0
#endif

#else	/* MPC5100 */

#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */

#endif

/* Partitions */
#undef CONFIG_MAC_PARTITION
#if defined (CONFIG_MINIFAP)
#define CONFIG_DOS_PARTITION
#endif

/* USB */
#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD		0
#endif

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_I2C)

#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif

/* IDE */
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#define ADD_IDE_CMD		CFG_CMD_IDE | CFG_CMD_FAT
#else
#define ADD_IDE_CMD		0
#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				ADD_PCI_CMD	| \
				ADD_USB_CMD	| \
				CFG_CMD_POST_DIAG | \
				CFG_CMD_DATE	| \
				CFG_CMD_REGINFO | \
				CFG_CMD_MII	| \
				CFG_CMD_PING	| \
				ADD_IDE_CMD)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#if defined (CONFIG_TQM5200_AA)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_aa_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0"			\
	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0"		\
	"serverip=172.20.5.13\0"					\
	""
#else
#if defined (CONFIG_TQM5200_AB)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_ab_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0"			\
	"update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0"		\
	"serverip=172.20.5.13\0"					\
	""
#else
#if defined (CONFIG_TQM5200_AC)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_ac_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0"			\
	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0"		\
	"serverip=172.20.5.13\0"					\
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0"				\
	"bootfile=uImage_tqm5200_mkr\0"					\
	"load=tftp 200000 $(loadfile)\0"				\
	"load133=tftp 200000 $(loadfile133)\0"				\
	"loadfile=u-boot_tqm5200_mkr.bin\0"				\
	"loadfile133=u-boot_tqm5200_133_mkr.bin\0"			\
	"update=protect off fc000000 fc03ffff; erase fc000000 fc03ffff; cp.b 200000 0xfc000000 $(filesize); protect on fc000000 fc03ffff\0"		\
	"serverip=172.20.5.13\0"					\
	""
#endif
#endif
#endif

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBSPEED_133		/* define for 133MHz speed */

#if defined(CFG_IPBSPEED_133)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 * been tested with a IPB Bus Clock of 66 MHz.
 */
#define CFG_PCISPEED_66			/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
#else
#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
#endif

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 * same configuration could be used.
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * HW-Monitor configuration on Mini-FAP
 */
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_HWMON_ADDR		0x2C
#endif

/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
				CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST	{	CFG_I2C_SLAVE }
#endif

#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
				CFG_I2C_HWMON_ADDR,	\
				CFG_I2C_SLAVE }
#endif

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE		0x02000000 /* 32 MByte */
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/


/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 *	Bit 0 (mask: 0x80000000): 1
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC6:
 *   on STK52xx:
 *      use as UART. Pins PSC6_0 to PSC6_3 are used.
	Bits 9:11 (mask: 0x00700000):
 *	   101 -> PSC6 : Extended POST test is not available
 *   on MINI-FAP and TQM5200_IB:
 *      use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 *	   011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 * tests.
 */
#if defined (CONFIG_MINIFAP)
#define CFG_GPS_PORT_CONFIG	0x91300004
#elif defined (CONFIG_STK52XX)
#define CFG_GPS_PORT_CONFIG	0x81500004
#else
#define CFG_GPS_PORT_CONFIG	0x81300004
#endif

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
#else
#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START		0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
#else  /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
#endif
#define CFG_CS2_CFG		0x0004D930
#endif

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
    defined (CONFIG_CS_AUTOCONF)
#define CFG_CS1_START		0xE0000000
#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
#define CFG_CS1_CFG		0x8F48FF70
#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
#endif

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CFG_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
56523f12 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
56523f12 WD	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	37	#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
7e6bf358	38	#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
56523f12 WD	39
	40	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	41
	42	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	43	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	44
	45	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	46	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	47	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	48	#endif
	49
	50	/*
	51	* Serial console configuration
	52	*/
	53	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	54	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	55	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	56
7e6bf358 WD	57	#ifdef CONFIG_STK52XX
	58	#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	59	#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	60	#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
	61	#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
	62	#define CONFIG_BOARD_EARLY_INIT_R
	63	#endif /* CONFIG_STK52XX */
56523f12 WD	64
	65	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	66	/*
	67	* PCI Mapping:
	68	* 0x40000000 - 0x4fffffff - PCI Memory
	69	* 0x50000000 - 0x50ffffff - PCI IO Space
	70	*/
7e6bf358 WD	71	#ifdef CONFIG_STK52XX
	72	#define CONFIG_PCI 1
	73	#elif
56523f12	74	#define CONFIG_PCI 0
7e6bf358	75	#endif
56523f12	76	#define CONFIG_PCI_PNP 1
31a64923	77	/* #define CONFIG_PCI_SCAN_SHOW 1 */
56523f12 WD	78
	79	#define CONFIG_PCI_MEM_BUS 0x40000000
	80	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	81	#define CONFIG_PCI_MEM_SIZE 0x10000000
	82
	83	#define CONFIG_PCI_IO_BUS 0x50000000
	84	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	85	#define CONFIG_PCI_IO_SIZE 0x01000000
	86
	87	#define CONFIG_NET_MULTI 1
	88	#define CONFIG_EEPRO100 1
	89	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	90	#define CONFIG_NS8382X 1
	91
7e6bf358 WD	92	#ifdef CONFIG_STK52XX
	93	#define ADD_PCI_CMD CFG_CMD_PCI
	94	#elif
	95	#define ADD_PCI_CMD 0
	96	#endif
56523f12 WD	97
	98	#else /* MPC5100 */
	99
	100	#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
	101
	102	#endif
	103
	104	/* Partitions */
	105	#undef CONFIG_MAC_PARTITION
	106	#if defined (CONFIG_MINIFAP)
	107	#define CONFIG_DOS_PARTITION
	108	#endif
	109
	110	/* USB */
7e6bf358	111	#ifdef CONFIG_STK52XX
56523f12	112	#define CONFIG_USB_OHCI
81050926	113	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
7e6bf358	114	#define CONFIG_DOS_PARTITION
56523f12 WD	115	#define CONFIG_USB_STORAGE
56523f12 WD	116	#else
81050926	117	#define ADD_USB_CMD 0
56523f12 WD	118	#endif
	119
	120	/* POST support */
	121	#define CONFIG_POST (CFG_POST_MEMORY \| \
	122	CFG_POST_CPU \| \
	123	CFG_POST_I2C)
	124
	125	#ifdef CONFIG_POST
	126	#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
	127	/* preserve space for the post_word at end of on-chip SRAM */
	128	#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
	129	#else
	130	#define CFG_CMD_POST_DIAG 0
	131	#endif
	132
	133	/* IDE */
7e6bf358	134	#if defined (CONFIG_MINIFAP) \|\| defined (CONFIG_STK52XX)
56523f12 WD	135	#define ADD_IDE_CMD CFG_CMD_IDE \| CFG_CMD_FAT
	136	#else
	137	#define ADD_IDE_CMD 0
	138	#endif
	139
	140	/*
	141	* Supported commands
	142	*/
	143	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	144	CFG_CMD_EEPROM \| \
	145	CFG_CMD_I2C \| \
	146	ADD_PCI_CMD \| \
	147	ADD_USB_CMD \| \
	148	CFG_CMD_POST_DIAG \| \
	149	CFG_CMD_DATE \| \
81050926	150	CFG_CMD_REGINFO \| \
56523f12 WD	151	CFG_CMD_MII \| \
	152	CFG_CMD_PING \| \
	153	ADD_IDE_CMD)
	154
	155	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	156	#include <cmd_confdefs.h>
	157
	158	#if (TEXT_BASE == 0xFC000000) /* Boot low */
81050926	159	# define CFG_LOWBOOT 1
56523f12 WD	160	#endif
	161
	162	/*
	163	* Autobooting
	164	*/
	165	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	166
81050926	167	#define CONFIG_PREBOOT "echo;" \
56523f12 WD	168	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	169	"echo"
	170
	171	#undef CONFIG_BOOTARGS
	172
	173	#if defined (CONFIG_TQM5200_AA)
81050926	174	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	175	"netdev=eth0\0" \
	176	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	177	"nfsroot=$(serverip):$(rootpath)\0" \
	178	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	179	"addip=setenv bootargs $(bootargs) " \
	180	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	181	":$(hostname):$(netdev):off panic=1\0" \
	182	"flash_nfs=run nfsargs addip;" \
	183	"bootm $(kernel_addr)\0" \
	184	"flash_self=run ramargs addip;" \
	185	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	186	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	187	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	188	"bootfile=uImage_tqm5200_mkr\0" \
	189	"load=tftp 200000 $(loadfile)\0" \
	190	"load133=tftp 200000 $(loadfile133)\0" \
	191	"loadfile=u-boot_tqm5200_aa_mkr.bin\0" \
81050926	192	"loadfile133=u-boot_tqm5200_aa_133_mkr.bin\0" \
56523f12 WD	193	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
	194	"serverip=172.20.5.13\0" \
	195	""
	196	#else
	197	#if defined (CONFIG_TQM5200_AB)
81050926	198	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	199	"netdev=eth0\0" \
	200	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	201	"nfsroot=$(serverip):$(rootpath)\0" \
	202	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	203	"addip=setenv bootargs $(bootargs) " \
	204	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	205	":$(hostname):$(netdev):off panic=1\0" \
	206	"flash_nfs=run nfsargs addip;" \
	207	"bootm $(kernel_addr)\0" \
	208	"flash_self=run ramargs addip;" \
	209	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	210	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	211	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	212	"bootfile=uImage_tqm5200_mkr\0" \
	213	"load=tftp 200000 $(loadfile)\0" \
	214	"load133=tftp 200000 $(loadfile133)\0" \
	215	"loadfile=u-boot_tqm5200_ab_mkr.bin\0" \
81050926	216	"loadfile133=u-boot_tqm5200_ab_133_mkr.bin\0" \
56523f12 WD	217	"update=protect off 1:0-1; erase 1:0-1; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-1\0" \
	218	"serverip=172.20.5.13\0" \
	219	""
	220	#else
	221	#if defined (CONFIG_TQM5200_AC)
81050926	222	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12 WD	223	"netdev=eth0\0" \
	224	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	225	"nfsroot=$(serverip):$(rootpath)\0" \
	226	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	227	"addip=setenv bootargs $(bootargs) " \
	228	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	229	":$(hostname):$(netdev):off panic=1\0" \
	230	"flash_nfs=run nfsargs addip;" \
	231	"bootm $(kernel_addr)\0" \
	232	"flash_self=run ramargs addip;" \
	233	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	234	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	235	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	236	"bootfile=uImage_tqm5200_mkr\0" \
	237	"load=tftp 200000 $(loadfile)\0" \
	238	"load133=tftp 200000 $(loadfile133)\0" \
	239	"loadfile=u-boot_tqm5200_ac_mkr.bin\0" \
81050926	240	"loadfile133=u-boot_tqm5200_ac_133_mkr.bin\0" \
56523f12 WD	241	"update=protect off 1:0-4; erase 1:0-4; cp.b 200000 0xfc000000 $(filesize); protect on 1:0-4\0" \
	242	"serverip=172.20.5.13\0" \
	243	""
7e6bf358 WD	244	#else
	245	#define CONFIG_EXTRA_ENV_SETTINGS \
	246	"netdev=eth0\0" \
	247	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	248	"nfsroot=$(serverip):$(rootpath)\0" \
	249	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	250	"addip=setenv bootargs $(bootargs) " \
	251	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	252	":$(hostname):$(netdev):off panic=1\0" \
	253	"flash_nfs=run nfsargs addip;" \
	254	"bootm $(kernel_addr)\0" \
	255	"flash_self=run ramargs addip;" \
	256	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	257	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	258	"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
	259	"bootfile=uImage_tqm5200_mkr\0" \
	260	"load=tftp 200000 $(loadfile)\0" \
	261	"load133=tftp 200000 $(loadfile133)\0" \
	262	"loadfile=u-boot_tqm5200_mkr.bin\0" \
	263	"loadfile133=u-boot_tqm5200_133_mkr.bin\0" \
	264	"update=protect off fc000000 fc03ffff; erase fc000000 fc03ffff; cp.b 200000 0xfc000000 $(filesize); protect on fc000000 fc03ffff\0" \
	265	"serverip=172.20.5.13\0" \
	266	""
56523f12 WD	267	#endif
	268	#endif
	269	#endif
	270
	271	#define CONFIG_BOOTCOMMAND "run net_nfs"
	272
	273	/*
	274	* IPB Bus clocking configuration.
	275	*/
81050926	276	#define CFG_IPBSPEED_133 /* define for 133MHz speed */
56523f12 WD	277
	278	#if defined(CFG_IPBSPEED_133)
	279	/*
	280	* PCI Bus clocking configuration
	281	*
	282	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
	283	* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
	284	* been tested with a IPB Bus Clock of 66 MHz.
	285	*/
	286	#define CFG_PCISPEED_66 /* define for 66MHz speed */
	287	#endif
	288
	289	/*
	290	* I2C configuration
	291	*/
	292	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	293	#if defined (CONFIG_MINIFAP)
	294	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	295	#else
	296	#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
	297	#endif
	298
	299	/*
	300	* I2C clock frequency
	301	*
	302	* Please notice, that the resulting clock frequency could differ from the
	303	* configured value. This is because the I2C clock is derived from system
	304	* clock over a frequency divider with only a few divider values. U-boot
	305	* calculates the best approximation for CFG_I2C_SPEED. However the calculated
	306	* approximation allways lies below the configured value, never above.
	307	*/
	308	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	309	#define CFG_I2C_SLAVE 0x7F
	310
	311	/*
	312	* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
	313	* also). For other EEPROMs configuration should be verified. On Mini-FAP the
	314	* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
	315	* same configuration could be used.
	316	*/
	317	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	318	#define CFG_I2C_EEPROM_ADDR_LEN 2
	319	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	320	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	321
	322	/*
	323	* HW-Monitor configuration on Mini-FAP
	324	*/
	325	#if defined (CONFIG_MINIFAP)
	326	#define CFG_I2C_HWMON_ADDR 0x2C
	327	#endif
	328
	329	/* List of I2C addresses to be verified by POST */
	330	#if defined (CONFIG_TQM5200_AA) \|\| defined (CONFIG_TQM5200_AB)
	331	#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
	332	CFG_I2C_SLAVE }
	333	#elif defined (CONFIG_TQM5200_AC)
	334	#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
	335	#endif
	336
	337	#if defined (CONFIG_MINIFAP)
	338	#undef I2C_ADDR_LIST
	339	#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
	340	CFG_I2C_HWMON_ADDR, \
341	CFG_I2C_SLAVE }
342	#endif
343
344	/*
345	* Flash configuration
346	*/
347	#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
348
7e6bf358 WD	349	/* use CFI flash driver if no module variant is spezified */
	350	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	351	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	352	#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
	353	#define CFG_FLASH_EMPTY_INFO
56523f12 WD	354	#define CFG_FLASH_SIZE 0x02000000 /* 32 MByte */
56523f12 WD	355	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
56523f12 WD	356
	357	#if !defined(CFG_LOWBOOT)
	358	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
	359	#else /* CFG_LOWBOOT */
56523f12	360	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
56523f12 WD	361	#endif /* CFG_LOWBOOT */
	362	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	363	(= chip selects) */
81050926 WD	364	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
81050926 WD	365	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
56523f12 WD	366
	367
	368	/*
	369	* Environment settings
	370	*/
	371	#define CFG_ENV_IS_IN_FLASH 1
	372	#define CFG_ENV_SIZE 0x10000
	373	#define CFG_ENV_SECT_SIZE 0x20000
	374	#define CONFIG_ENV_OVERWRITE 1
	375
	376	/*
	377	* Memory map
	378	*/
	379	#define CFG_MBAR 0xF0000000
	380	#define CFG_SDRAM_BASE 0x00000000
	381	#define CFG_DEFAULT_MBAR 0x80000000
	382
	383	/* Use ON-Chip SRAM until RAM will be available */
	384	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	385	#ifdef CONFIG_POST
	386	/* preserve space for the post_word at end of on-chip SRAM */
	387	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	388	#else
	389	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	390	#endif
	391
	392
	393	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	394	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	395	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	396
	397	#define CFG_MONITOR_BASE TEXT_BASE
	398	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	399	# define CFG_RAMBOOT 1
	400	#endif
	401
	402	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	403	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	404	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	405
	406	/*
	407	* Ethernet configuration
	408	*/
	409	#define CONFIG_MPC5xxx_FEC 1
	410	/*
	411	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	412	*/
	413	/* #define CONFIG_FEC_10MBIT 1 */
	414	#define CONFIG_PHY_ADDR 0x00
	415
	416	/*
	417	* GPIO configuration
	418	*
	419	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
	420	* Bit 0 (mask: 0x80000000): 1
	421	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	422	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
81050926 WD	423	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
81050926 WD	424	* EEPROM
56523f12	425	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
7e6bf358 WD	426	* use PSC6:
	427	* on STK52xx:
	428	* use as UART. Pins PSC6_0 to PSC6_3 are used.
efe2a4d5	429	Bits 9:11 (mask: 0x00700000):
7e6bf358 WD	430	* 101 -> PSC6 : Extended POST test is not available
	431	* on MINI-FAP and TQM5200_IB:
	432	* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
	433	* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
56523f12 WD	434	* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
	435	* tests.
	436	*/
	437	#if defined (CONFIG_MINIFAP)
7e6bf358 WD	438	#define CFG_GPS_PORT_CONFIG 0x91300004
	439	#elif defined (CONFIG_STK52XX)
	440	#define CFG_GPS_PORT_CONFIG 0x81500004
56523f12	441	#else
7e6bf358	442	#define CFG_GPS_PORT_CONFIG 0x81300004
56523f12 WD	443	#endif
	444
	445	/*
	446	* RTC configuration
	447	*/
	448	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	449
	450	/*
	451	* Miscellaneous configurable options
	452	*/
	453	#define CFG_LONGHELP /* undef to save memory */
	454	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	455	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	456	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	457	#else
	458	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	459	#endif
	460	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	461	#define CFG_MAXARGS 16 /* max number of command args */
	462	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	463
	464	/* Enable an alternate, more extensive memory test */
	465	#define CFG_ALT_MEMTEST
	466
	467	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	468	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	469
	470	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	471
	472	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	473
	474	/*
	475	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
	476	* which is normally part of the default commands (CFV_CMD_DFL)
	477	*/
	478	#define CONFIG_LOOPW
	479
	480	/*
	481	* Various low-level settings
	482	*/
	483	#if defined(CONFIG_MPC5200)
	484	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	485	#define CFG_HID0_FINAL HID0_ICE
	486	#else
	487	#define CFG_HID0_INIT 0
	488	#define CFG_HID0_FINAL 0
	489	#endif
	490
	491	#define CFG_BOOTCS_START CFG_FLASH_BASE
	492	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	493	#ifdef CFG_PCISPEED_66
	494	#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
	495	#else
	496	#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
	497	#endif
	498	#define CFG_CS0_START CFG_FLASH_BASE
	499	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	500
7e6bf358 WD	501	/* automatic configuration of chip selects */
	502	#ifdef CONFIG_CS_AUTOCONF
	503	#define CONFIG_LAST_STAGE_INIT
	504	#endif
	505
56523f12 WD	506	/*
	507	* SRAM - Do not map below 2 GB in address space, because this area is used
	508	* for SDRAM autosizing.
	509	*/
7e6bf358	510	#if defined CONFIG_TQM5200_AB \|\| defined (CONFIG_CS_AUTOCONF)
56523f12	511	#define CFG_CS2_START 0xE5000000
7e6bf358	512	#ifdef CONFIG_TQM5200_AB
56523f12	513	#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
7e6bf358 WD	514	#else /* CONFIG_CS_AUTOCONF */
	515	#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
	516	#endif
56523f12 WD	517	#define CFG_CS2_CFG 0x0004D930
	518	#endif
	519
	520	/*
	521	* Grafic controller - Do not map below 2 GB in address space, because this
	522	* area is used for SDRAM autosizing.
	523	*/
7e6bf358 WD	524	#if defined (CONFIG_TQM5200_AB) \|\| defined (CONFIG_TQM5200_AC) \|\| \
7e6bf358 WD	525	defined (CONFIG_CS_AUTOCONF)
56523f12 WD	526	#define CFG_CS1_START 0xE0000000
56523f12 WD	527	#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
89394047	528	#define CFG_CS1_CFG 0x8F48FF70
56523f12 WD	529	#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
	530	#endif
	531
	532	#define CFG_CS_BURST 0x00000000
	533	#define CFG_CS_DEADCYCLE 0x33333333
	534
	535	#define CFG_RESET_ADDRESS 0xff000000
	536
	537	/*-----------------------------------------------------------------------
	538	* USB stuff
	539	*-----------------------------------------------------------------------
	540	*/
	541	#define CONFIG_USB_CLOCK 0x0001BBBB
	542	#define CONFIG_USB_CONFIG 0x00001000
	543
	544	/*-----------------------------------------------------------------------
	545	* IDE/ATA stuff Supports IDE harddisk
	546	*-----------------------------------------------------------------------
	547	*/
	548
81050926	549	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12	550
81050926 WD	551	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
81050926 WD	552	#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12	553
81050926	554	#define CONFIG_IDE_RESET /* reset for ide supported */
56523f12 WD	555	#define CONFIG_IDE_PREINIT
	556
	557	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	558	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	559
	560	#define CFG_ATA_IDE0_OFFSET 0x0000
	561
	562	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	563
	564	/* Offset for data I/O */
	565	#define CFG_ATA_DATA_OFFSET (0x0060)
	566
	567	/* Offset for normal register accesses */
	568	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	569
	570	/* Offset for alternate registers */
	571	#define CFG_ATA_ALT_OFFSET (0x005C)
	572
81050926 WD	573	/* Interval between registers */
81050926 WD	574	#define CFG_ATA_STRIDE 4
56523f12 WD	575
56523f12 WD	576	#endif /* __CONFIG_H */