[people/ms/u-boot.git] / include / configs / TQM834x.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * TQM8349 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC834x		1	/* MPC834x specific */
#define CONFIG_MPC8349		1	/* MPC8349 specific */

/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR		0xff400000

/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */

/*
 * Local Bus LCRR
 *    LCRR:  DLL bypass, Clock divider is 8
 *
 *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
 *
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8

/* board pre init: do not call, nothing to do */

/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * DDR Setup
 */
				/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * FLASH bank number detection
 */

/*
 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
 * Flash banks has to be determined at runtime and stored in a gloabl variable
 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
 * flash_info, and should be made sufficiently large to accomodate the number
 * of banks that might actually be detected.  Since most (all?) Flash related
 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
 * the board, it is defined as tqm834x_num_flash_banks.
 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2

#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */

/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
				| BR_MS_GPCM \
				| BR_PS_32 \
				| BR_V)

/* FLASH timing (0x0000_0c54) */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV4 \
					| OR_GPCM_SCY_5 \
					| OR_GPCM_TRLX)

#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */

#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
					| CONFIG_SYS_OR_TIMING_FLASH)

#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE

/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM		0x00000000
#define CONFIG_SYS_OR1_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000

#define CONFIG_SYS_BR2_PRELIM		0x00000000
#define CONFIG_SYS_OR2_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000

#define CONFIG_SYS_BR3_PRELIM		0x00000000
#define CONFIG_SYS_OR3_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000

/*
 * Monitor config
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#else
# undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

				/* Reserve 384 kB = 3 sect. for Mon */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
				/* Reserve 512 kB for malloc */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */

/* I2C RTC */
#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_MII

#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

/* PCI1 host bridge */
#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */

#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
#endif

#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	0
#define CONFIG_SYS_SICRL	SICRL_LDP_A

/* i-cache and d-cache disabled */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2	HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR 0 - 512M */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE @ 512M (no backing mem) */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)

/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE \
				| BATU_BL_16M \
				| BATU_VS \
				| BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#endif

/* IMMRBAR */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR \
				| BATU_BL_1M \
				| BATU_VS \
				| BATU_VP)

/* FLASH */
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		400000

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=tqm834x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"flash_nfs_old=run nfsargs addip addcons;"			\
		"bootm ${kernel_addr}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self_old=run ramargs addip addcons;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs_old=tftp 400000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons; "				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=tqm834x/uImage\0"					\
	"fdtfile=tqm834x/tqm834x.dtb\0"					\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"ramdisk_addr_r=800000\0"					\
	"kernel_addr=800C0000\0"					\
	"fdt_addr=800A0000\0"						\
	"ramdisk_addr=80300000\0"					\
	"u-boot=tqm834x/u-boot.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off 80000000 +${filesize};"			\
		"era 80000000 +${filesize};"				\
		"cp.b 200000 80000000 ${filesize}\0"			\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * JFFS2 partitions
 */
/* mtdparts command line support */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD

/* default mtd partition table */
#endif	/* __CONFIG_H */
Commit	Line	Data
e6f2e902 MB	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
e6f2e902 MB	6	*/
	7
	8	/*
	9	* TQM8349 board configuration file
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
e6f2e902 MB	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 Family */
2c7920af	19	#define CONFIG_MPC834x 1 /* MPC834x specific */
9ca880a2	20	#define CONFIG_MPC8349 1 /* MPC8349 specific */
e6f2e902	21
16263087	22	/* IMMR Base Address Register, use Freescale default: 0xff400000 */
6d0f6bcf	23	#define CONFIG_SYS_IMMR 0xff400000
e6f2e902 MB	24
	25	/* System clock. Primary input clock when in PCI host mode */
	26	#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
	27
	28	/*
	29	* Local Bus LCRR
	30	* LCRR: DLL bypass, Clock divider is 8
	31	*
	32	* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
	33	*
	34	* External Local Bus rate is
	35	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	36	*/
c7190f02 KP	37	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	38	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
e6f2e902 MB	39
e6f2e902 MB	40	/* board pre init: do not call, nothing to do */
e6f2e902 MB	41
	42	/* detect the number of flash banks */
	43	#define CONFIG_BOARD_EARLY_INIT_R
	44
	45	/*
	46	* DDR Setup
	47	*/
df939e16 JH	48	/* DDR is system memory*/
	49	#define CONFIG_SYS_DDR_BASE 0x00000000
	50	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	51	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
df939e16 JH	52	#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
	53	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	54	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
e6f2e902	55
df939e16	56	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
6d0f6bcf JCPV	57	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
6d0f6bcf JCPV	58	#define CONFIG_SYS_MEMTEST_END 0x00100000
e6f2e902 MB	59
	60	/*
	61	* FLASH on the Local Bus
	62	*/
df939e16 JH	63	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
df939e16 JH	64	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
6d0f6bcf JCPV	65	#undef CONFIG_SYS_FLASH_CHECKSUM
	66	#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
	67	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
df939e16	68	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
a3455c00	69	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
e6f2e902 MB	70
	71	/*
	72	* FLASH bank number detection
	73	*/
	74
	75	/*
df939e16 JH	76	* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
	77	* Flash banks has to be determined at runtime and stored in a gloabl variable
	78	* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
	79	* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
	80	* flash_info, and should be made sufficiently large to accomodate the number
	81	* of banks that might actually be detected. Since most (all?) Flash related
	82	* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
	83	* the board, it is defined as tqm834x_num_flash_banks.
e6f2e902	84	*/
6d0f6bcf	85	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
e6f2e902	86
df939e16	87	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
e6f2e902 MB	88
e6f2e902 MB	89	/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
df939e16 JH	90	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
	91	\| BR_MS_GPCM \
	92	\| BR_PS_32 \
	93	\| BR_V)
e6f2e902 MB	94
e6f2e902 MB	95	/* FLASH timing (0x0000_0c54) */
df939e16 JH	96	#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
	97	\| OR_GPCM_ACS_DIV4 \
	98	\| OR_GPCM_SCY_5 \
	99	\| OR_GPCM_TRLX)
e6f2e902	100
7d6a0982	101	#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
e6f2e902	102
df939e16 JH	103	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
df939e16 JH	104	\| CONFIG_SYS_OR_TIMING_FLASH)
e6f2e902	105
7d6a0982	106	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_1GB)
6902df56	107
df939e16 JH	108	/* Window base at flash base */
df939e16 JH	109	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
e6f2e902 MB	110
e6f2e902 MB	111	/* disable remaining mappings */
6d0f6bcf JCPV	112	#define CONFIG_SYS_BR1_PRELIM 0x00000000
	113	#define CONFIG_SYS_OR1_PRELIM 0x00000000
	114	#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
	115	#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
	116
	117	#define CONFIG_SYS_BR2_PRELIM 0x00000000
	118	#define CONFIG_SYS_OR2_PRELIM 0x00000000
	119	#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
	120	#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
	121
	122	#define CONFIG_SYS_BR3_PRELIM 0x00000000
	123	#define CONFIG_SYS_OR3_PRELIM 0x00000000
	124	#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
	125	#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
e6f2e902 MB	126
	127	/*
	128	* Monitor config
	129	*/
14d0a02a	130	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
e6f2e902	131
6d0f6bcf	132	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
4681e673	133	# define CONFIG_SYS_RAMBOOT
e6f2e902	134	#else
4681e673	135	# undef CONFIG_SYS_RAMBOOT
e6f2e902 MB	136	#endif
e6f2e902 MB	137
6d0f6bcf	138	#define CONFIG_SYS_INIT_RAM_LOCK 1
df939e16 JH	139	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
df939e16 JH	140	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
e6f2e902	141
df939e16 JH	142	#define CONFIG_SYS_GBL_DATA_OFFSET \
df939e16 JH	143	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	144	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e6f2e902	145
df939e16 JH	146	/* Reserve 384 kB = 3 sect. for Mon */
	147	#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
	148	/* Reserve 512 kB for malloc */
	149	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
e6f2e902 MB	150
	151	/*
	152	* Serial Port
	153	*/
	154	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	155	#define CONFIG_SYS_NS16550_SERIAL
	156	#define CONFIG_SYS_NS16550_REG_SIZE 1
	157	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
e6f2e902	158
6d0f6bcf	159	#define CONFIG_SYS_BAUDRATE_TABLE \
df939e16	160	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
e6f2e902	161
6d0f6bcf JCPV	162	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	163	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
e6f2e902 MB	164
	165	/*
	166	* I2C
	167	*/
00f792e0 HS	168	#define CONFIG_SYS_I2C
	169	#define CONFIG_SYS_I2C_FSL
	170	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	171	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	172	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
e6f2e902 MB	173
e6f2e902 MB	174	/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
df939e16 JH	175	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	176	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
	177	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
	178	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
e6f2e902 MB	179
e6f2e902 MB	180	/* I2C RTC */
df939e16 JH	181	#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
df939e16 JH	182	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
e6f2e902	183
e6f2e902 MB	184	/*
	185	* TSEC
	186	*/
53677ef1	187	#define CONFIG_TSEC_ENET /* tsec ethernet support */
e6f2e902 MB	188	#define CONFIG_MII
e6f2e902 MB	189
6d0f6bcf	190	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
df939e16	191	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	192	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
df939e16	193	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
e6f2e902 MB	194
	195	#if defined(CONFIG_TSEC_ENET)
	196
255a3577 KP	197	#define CONFIG_TSEC1 1
	198	#define CONFIG_TSEC1_NAME "TSEC0"
	199	#define CONFIG_TSEC2 1
	200	#define CONFIG_TSEC2_NAME "TSEC1"
df939e16 JH	201	#define TSEC1_PHY_ADDR 2
	202	#define TSEC2_PHY_ADDR 1
	203	#define TSEC1_PHYIDX 0
	204	#define TSEC2_PHYIDX 0
3a79013e AF	205	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	206	#define TSEC2_FLAGS TSEC_GIGABIT
e6f2e902 MB	207
e6f2e902 MB	208	/* Options are: TSEC[0-1] */
df939e16	209	#define CONFIG_ETHPRIME "TSEC0"
e6f2e902 MB	210
	211	#endif /* CONFIG_TSEC_ENET */
	212
e6f2e902 MB	213	#if defined(CONFIG_PCI)
e6f2e902 MB	214
df939e16	215	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6902df56 RJ	216
6902df56 RJ	217	/* PCI1 host bridge */
df939e16 JH	218	#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
	219	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	220	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	221	#define CONFIG_SYS_PCI1_MMIO_BASE \
	222	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
	223	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	224	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	225	#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
	226	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	227	#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
e6f2e902	228
e6f2e902	229	#undef CONFIG_EEPRO100
63ff004c	230	#define CONFIG_EEPRO100
e6f2e902 MB	231	#undef CONFIG_TULIP
	232
	233	#if !defined(CONFIG_PCI_PNP)
6d0f6bcf JCPV	234	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
6d0f6bcf JCPV	235	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
6902df56	236	#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
e6f2e902 MB	237	#endif
e6f2e902 MB	238
6d0f6bcf	239	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
e6f2e902 MB	240
	241	#endif /* CONFIG_PCI */
	242
	243	/*
	244	* Environment
	245	*/
df939e16 JH	246	#define CONFIG_ENV_ADDR \
	247	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	248	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
	249	#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
929b79a0 WD	250	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	251	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	252
df939e16 JH	253	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
df939e16 JH	254	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
e6f2e902	255
a1aa0bb5 JL	256	/*
	257	* BOOTP options
	258	*/
	259	#define CONFIG_BOOTP_BOOTFILESIZE
a1aa0bb5	260
e6f2e902 MB	261	/*
	262	* Miscellaneous configurable options
	263	*/
df939e16	264	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
e6f2e902	265
df939e16	266	#undef CONFIG_WATCHDOG /* watchdog disabled */
e6f2e902 MB	267
	268	/*
	269	* For booting Linux, the board info and command line data
9f530d59	270	* have to be in the first 256 MB of memory, since this is
e6f2e902 MB	271	* the maximum mapped by the Linux kernel during initialization.
e6f2e902 MB	272	*/
df939e16 JH	273	/* Initial Memory map for Linux */
df939e16 JH	274	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
e6f2e902	275
6d0f6bcf	276	#define CONFIG_SYS_HRCW_LOW (\
e6f2e902 MB	277	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	278	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	279	HRCWL_CSB_TO_CLKIN_4X1 \|\
	280	HRCWL_VCO_1X2 \|\
	281	HRCWL_CORE_TO_CSB_2X1)
	282
	283	#if defined(PCI_64BIT)
6d0f6bcf	284	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	285	HRCWH_PCI_HOST \|\
	286	HRCWH_64_BIT_PCI \|\
	287	HRCWH_PCI1_ARBITER_ENABLE \|\
	288	HRCWH_PCI2_ARBITER_DISABLE \|\
	289	HRCWH_CORE_ENABLE \|\
	290	HRCWH_FROM_0X00000100 \|\
	291	HRCWH_BOOTSEQ_DISABLE \|\
	292	HRCWH_SW_WATCHDOG_DISABLE \|\
	293	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	294	HRCWH_TSEC1M_IN_GMII \|\
df939e16	295	HRCWH_TSEC2M_IN_GMII)
e6f2e902	296	#else
6d0f6bcf	297	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	298	HRCWH_PCI_HOST \|\
	299	HRCWH_32_BIT_PCI \|\
	300	HRCWH_PCI1_ARBITER_ENABLE \|\
6902df56	301	HRCWH_PCI2_ARBITER_DISABLE \|\
e6f2e902 MB	302	HRCWH_CORE_ENABLE \|\
	303	HRCWH_FROM_0X00000100 \|\
	304	HRCWH_BOOTSEQ_DISABLE \|\
	305	HRCWH_SW_WATCHDOG_DISABLE \|\
	306	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	307	HRCWH_TSEC1M_IN_GMII \|\
df939e16	308	HRCWH_TSEC2M_IN_GMII)
e6f2e902 MB	309	#endif
e6f2e902 MB	310
9260a561	311	/* System IO Config */
3c9b1ee1	312	#define CONFIG_SYS_SICRH 0
6d0f6bcf	313	#define CONFIG_SYS_SICRL SICRL_LDP_A
9260a561	314
e6f2e902	315	/* i-cache and d-cache disabled */
6d0f6bcf	316	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	317	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
1a2e203b KP	318	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	319	#define CONFIG_SYS_HID2 HID2_HBE
e6f2e902	320
31d82672 BB	321	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	322
2688e2f9	323	/* DDR 0 - 512M */
df939e16	324	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	325	\| BATL_PP_RW \
df939e16 JH	326	\| BATL_MEMCOHERENCE)
	327	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	328	\| BATU_BL_256M \
	329	\| BATU_VS \
	330	\| BATU_VP)
	331	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
72cd4087	332	\| BATL_PP_RW \
df939e16 JH	333	\| BATL_MEMCOHERENCE)
	334	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
	335	\| BATU_BL_256M \
	336	\| BATU_VS \
	337	\| BATU_VP)
2688e2f9 KG	338
2688e2f9 KG	339	/* stack in DCACHE @ 512M (no backing mem) */
df939e16	340	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
72cd4087	341	\| BATL_PP_RW \
df939e16 JH	342	\| BATL_MEMCOHERENCE)
	343	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
	344	\| BATU_BL_128K \
	345	\| BATU_VS \
	346	\| BATU_VP)
2688e2f9 KG	347
2688e2f9 KG	348	/* PCI */
6fe16a87	349	#ifdef CONFIG_PCI
842033e6	350	#define CONFIG_PCI_INDIRECT_BRIDGE
df939e16	351	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
72cd4087	352	\| BATL_PP_RW \
df939e16 JH	353	\| BATL_MEMCOHERENCE)
	354	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
	355	\| BATU_BL_256M \
	356	\| BATU_VS \
	357	\| BATU_VP)
	358	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	359	\| BATL_PP_RW \
df939e16 JH	360	\| BATL_MEMCOHERENCE \
	361	\| BATL_GUARDEDSTORAGE)
	362	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
	363	\| BATU_BL_256M \
	364	\| BATU_VS \
	365	\| BATU_VP)
	366	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
72cd4087	367	\| BATL_PP_RW \
df939e16 JH	368	\| BATL_CACHEINHIBIT \
	369	\| BATL_GUARDEDSTORAGE)
	370	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
	371	\| BATU_BL_16M \
	372	\| BATU_VS \
	373	\| BATU_VP)
6fe16a87	374	#else
6d0f6bcf JCPV	375	#define CONFIG_SYS_IBAT3L (0)
	376	#define CONFIG_SYS_IBAT3U (0)
	377	#define CONFIG_SYS_IBAT4L (0)
	378	#define CONFIG_SYS_IBAT4U (0)
	379	#define CONFIG_SYS_IBAT5L (0)
	380	#define CONFIG_SYS_IBAT5U (0)
6fe16a87	381	#endif
2688e2f9 KG	382
2688e2f9 KG	383	/* IMMRBAR */
df939e16	384	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
72cd4087	385	\| BATL_PP_RW \
df939e16 JH	386	\| BATL_CACHEINHIBIT \
	387	\| BATL_GUARDEDSTORAGE)
	388	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
	389	\| BATU_BL_1M \
	390	\| BATU_VS \
	391	\| BATU_VP)
2688e2f9 KG	392
2688e2f9 KG	393	/* FLASH */
df939e16	394	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
72cd4087	395	\| BATL_PP_RW \
df939e16 JH	396	\| BATL_CACHEINHIBIT \
	397	\| BATL_GUARDEDSTORAGE)
	398	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
	399	\| BATU_BL_256M \
	400	\| BATU_VS \
	401	\| BATU_VP)
6d0f6bcf JCPV	402
	403	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	404	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	405	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	406	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	407	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	408	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	409	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	410	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	411	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	412	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	413	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	414	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	415	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	416	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	417	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	418	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
2688e2f9	419
2694690e	420	#if defined(CONFIG_CMD_KGDB)
e6f2e902	421	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
e6f2e902 MB	422	#endif
	423
	424	/*
	425	* Environment Configuration
	426	*/
	427
df939e16 JH	428	/* default location for tftp and bootm */
df939e16 JH	429	#define CONFIG_LOADADDR 400000
e6f2e902	430
e6f2e902	431	#define CONFIG_PREBOOT "echo;" \
32bf3d14	432	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
e6f2e902 MB	433	"echo"
e6f2e902 MB	434
e6f2e902 MB	435	#define CONFIG_EXTRA_ENV_SETTINGS \
e6f2e902 MB	436	"netdev=eth0\0" \
b931b3a9	437	"hostname=tqm834x\0" \
e6f2e902	438	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	439	"nfsroot=${serverip}:${rootpath}\0" \
e6f2e902	440	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	441	"addip=setenv bootargs ${bootargs} " \
	442	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	443	":${hostname}:${netdev}:off panic=1\0" \
df939e16	444	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
4681e673	445	"flash_nfs_old=run nfsargs addip addcons;" \
fe126d8b	446	"bootm ${kernel_addr}\0" \
4681e673 WD	447	"flash_nfs=run nfsargs addip addcons;" \
	448	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	449	"flash_self_old=run ramargs addip addcons;" \
fe126d8b	450	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
4681e673 WD	451	"flash_self=run ramargs addip addcons;" \
	452	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	453	"net_nfs_old=tftp 400000 ${bootfile};" \
	454	"run nfsargs addip addcons;bootm\0" \
	455	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	456	"tftp ${fdt_addr_r} ${fdt_file}; " \
	457	"run nfsargs addip addcons; " \
	458	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
e6f2e902	459	"rootpath=/opt/eldk/ppc_6xx\0" \
4681e673 WD	460	"bootfile=tqm834x/uImage\0" \
	461	"fdtfile=tqm834x/tqm834x.dtb\0" \
	462	"kernel_addr_r=400000\0" \
	463	"fdt_addr_r=600000\0" \
	464	"ramdisk_addr_r=800000\0" \
	465	"kernel_addr=800C0000\0" \
	466	"fdt_addr=800A0000\0" \
	467	"ramdisk_addr=80300000\0" \
	468	"u-boot=tqm834x/u-boot.bin\0" \
	469	"load=tftp 200000 ${u-boot}\0" \
	470	"update=protect off 80000000 +${filesize};" \
	471	"era 80000000 +${filesize};" \
	472	"cp.b 200000 80000000 ${filesize}\0" \
d8ab58b2	473	"upd=run load update\0" \
e6f2e902 MB	474	""
	475
	476	#define CONFIG_BOOTCOMMAND "run flash_self"
	477
	478	/*
	479	* JFFS2 partitions
	480	*/
	481	/* mtdparts command line support */
942556a9 SR	482	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	483	#define CONFIG_FLASH_CFI_MTD
e6f2e902 MB	484
e6f2e902 MB	485	/* default mtd partition table */
e6f2e902	486	#endif /* __CONFIG_H */