[people/ms/u-boot.git] / include / configs / TQM834x.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * TQM8349 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DISPLAY_BOARDINFO

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC834x		1	/* MPC834x specific */
#define CONFIG_MPC8349		1	/* MPC8349 specific */
#define CONFIG_TQM834X		1	/* TQM834X board specific */

#define	CONFIG_SYS_TEXT_BASE	0x80000000

/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR		0xff400000

/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */

/*
 * Local Bus LCRR
 *    LCRR:  DLL bypass, Clock divider is 8
 *
 *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
 *
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8

/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F

/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * DDR Setup
 */
				/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * FLASH bank number detection
 */

/*
 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
 * Flash banks has to be determined at runtime and stored in a gloabl variable
 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
 * flash_info, and should be made sufficiently large to accomodate the number
 * of banks that might actually be detected.  Since most (all?) Flash related
 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
 * the board, it is defined as tqm834x_num_flash_banks.
 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2

#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */

/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
				| BR_MS_GPCM \
				| BR_PS_32 \
				| BR_V)

/* FLASH timing (0x0000_0c54) */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV4 \
					| OR_GPCM_SCY_5 \
					| OR_GPCM_TRLX)

#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */

#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
					| CONFIG_SYS_OR_TIMING_FLASH)

#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE

/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM		0x00000000
#define CONFIG_SYS_OR1_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000

#define CONFIG_SYS_BR2_PRELIM		0x00000000
#define CONFIG_SYS_OR2_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000

#define CONFIG_SYS_BR3_PRELIM		0x00000000
#define CONFIG_SYS_OR3_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000

/*
 * Monitor config
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#else
# undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

				/* Reserve 384 kB = 3 sect. for Mon */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
				/* Reserve 512 kB for malloc */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */
#define CONFIG_SYS_I2C_MULTI_EEPROMS		/* more than one eeprom */

/* I2C RTC */
#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75			1	/* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP		70
#define CONFIG_SYS_DTT_LOW_TEMP		-30
#define CONFIG_SYS_DTT_HYSTERESIS	3

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_MII

#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

/* PCI1 host bridge */
#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */

#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
#endif

#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */

#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser */

#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

				/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	0
#define CONFIG_SYS_SICRL	SICRL_LDP_A

/* i-cache and d-cache disabled */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2	HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR 0 - 512M */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE @ 512M (no backing mem) */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)

/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE \
				| BATU_BL_16M \
				| BATU_VS \
				| BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#endif

/* IMMRBAR */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR \
				| BATU_BL_1M \
				| BATU_VS \
				| BATU_VP)

/* FLASH */
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		400000

#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE		115200

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=tqm834x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"flash_nfs_old=run nfsargs addip addcons;"			\
		"bootm ${kernel_addr}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self_old=run ramargs addip addcons;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs_old=tftp 400000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons; "				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=tqm834x/uImage\0"					\
	"fdtfile=tqm834x/tqm834x.dtb\0"					\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"ramdisk_addr_r=800000\0"					\
	"kernel_addr=800C0000\0"					\
	"fdt_addr=800A0000\0"						\
	"ramdisk_addr=80300000\0"					\
	"u-boot=tqm834x/u-boot.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off 80000000 +${filesize};"			\
		"era 80000000 +${filesize};"				\
		"cp.b 200000 80000000 ${filesize}\0"			\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * JFFS2 partitions
 */
/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM834x-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
						"1m(kernel),2m(initrd)," \
						"-(user);" \

#endif	/* __CONFIG_H */
Commit	Line	Data
e6f2e902 MB	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
e6f2e902 MB	6	*/
	7
	8	/*
	9	* TQM8349 board configuration file
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
fdfaa29e KP	15	#define CONFIG_DISPLAY_BOARDINFO
fdfaa29e KP	16
e6f2e902 MB	17	/*
	18	* High Level Configuration Options
	19	*/
	20	#define CONFIG_E300 1 /* E300 Family */
2c7920af	21	#define CONFIG_MPC834x 1 /* MPC834x specific */
9ca880a2	22	#define CONFIG_MPC8349 1 /* MPC8349 specific */
e6f2e902 MB	23	#define CONFIG_TQM834X 1 /* TQM834X board specific */
e6f2e902 MB	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0x80000000
2ae18241 WD	26
16263087	27	/* IMMR Base Address Register, use Freescale default: 0xff400000 */
6d0f6bcf	28	#define CONFIG_SYS_IMMR 0xff400000
e6f2e902 MB	29
	30	/* System clock. Primary input clock when in PCI host mode */
	31	#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
	32
	33	/*
	34	* Local Bus LCRR
	35	* LCRR: DLL bypass, Clock divider is 8
	36	*
	37	* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
	38	*
	39	* External Local Bus rate is
	40	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	41	*/
c7190f02 KP	42	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	43	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
e6f2e902 MB	44
	45	/* board pre init: do not call, nothing to do */
	46	#undef CONFIG_BOARD_EARLY_INIT_F
	47
	48	/* detect the number of flash banks */
	49	#define CONFIG_BOARD_EARLY_INIT_R
	50
	51	/*
	52	* DDR Setup
	53	*/
df939e16 JH	54	/* DDR is system memory*/
	55	#define CONFIG_SYS_DDR_BASE 0x00000000
	56	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	57	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
df939e16 JH	58	#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
	59	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	60	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
e6f2e902	61
df939e16	62	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
6d0f6bcf JCPV	63	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
6d0f6bcf JCPV	64	#define CONFIG_SYS_MEMTEST_END 0x00100000
e6f2e902 MB	65
	66	/*
	67	* FLASH on the Local Bus
	68	*/
df939e16 JH	69	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
df939e16 JH	70	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
6d0f6bcf JCPV	71	#undef CONFIG_SYS_FLASH_CHECKSUM
	72	#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
	73	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
df939e16	74	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
a3455c00	75	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
e6f2e902 MB	76
	77	/*
	78	* FLASH bank number detection
	79	*/
	80
	81	/*
df939e16 JH	82	* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
	83	* Flash banks has to be determined at runtime and stored in a gloabl variable
	84	* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
	85	* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
	86	* flash_info, and should be made sufficiently large to accomodate the number
	87	* of banks that might actually be detected. Since most (all?) Flash related
	88	* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
	89	* the board, it is defined as tqm834x_num_flash_banks.
e6f2e902	90	*/
6d0f6bcf	91	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
e6f2e902	92
df939e16	93	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
e6f2e902 MB	94
e6f2e902 MB	95	/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
df939e16 JH	96	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
	97	\| BR_MS_GPCM \
	98	\| BR_PS_32 \
	99	\| BR_V)
e6f2e902 MB	100
e6f2e902 MB	101	/* FLASH timing (0x0000_0c54) */
df939e16 JH	102	#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
	103	\| OR_GPCM_ACS_DIV4 \
	104	\| OR_GPCM_SCY_5 \
	105	\| OR_GPCM_TRLX)
e6f2e902	106
7d6a0982	107	#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
e6f2e902	108
df939e16 JH	109	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
df939e16 JH	110	\| CONFIG_SYS_OR_TIMING_FLASH)
e6f2e902	111
7d6a0982	112	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_1GB)
6902df56	113
df939e16 JH	114	/* Window base at flash base */
df939e16 JH	115	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
e6f2e902 MB	116
e6f2e902 MB	117	/* disable remaining mappings */
6d0f6bcf JCPV	118	#define CONFIG_SYS_BR1_PRELIM 0x00000000
	119	#define CONFIG_SYS_OR1_PRELIM 0x00000000
	120	#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
	121	#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
	122
	123	#define CONFIG_SYS_BR2_PRELIM 0x00000000
	124	#define CONFIG_SYS_OR2_PRELIM 0x00000000
	125	#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
	126	#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
	127
	128	#define CONFIG_SYS_BR3_PRELIM 0x00000000
	129	#define CONFIG_SYS_OR3_PRELIM 0x00000000
	130	#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
	131	#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
e6f2e902 MB	132
	133	/*
	134	* Monitor config
	135	*/
14d0a02a	136	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
e6f2e902	137
6d0f6bcf	138	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
4681e673	139	# define CONFIG_SYS_RAMBOOT
e6f2e902	140	#else
4681e673	141	# undef CONFIG_SYS_RAMBOOT
e6f2e902 MB	142	#endif
e6f2e902 MB	143
6d0f6bcf	144	#define CONFIG_SYS_INIT_RAM_LOCK 1
df939e16 JH	145	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
df939e16 JH	146	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
e6f2e902	147
df939e16 JH	148	#define CONFIG_SYS_GBL_DATA_OFFSET \
df939e16 JH	149	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	150	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e6f2e902	151
df939e16 JH	152	/* Reserve 384 kB = 3 sect. for Mon */
	153	#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
	154	/* Reserve 512 kB for malloc */
	155	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
e6f2e902 MB	156
	157	/*
	158	* Serial Port
	159	*/
	160	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	161	#define CONFIG_SYS_NS16550_SERIAL
	162	#define CONFIG_SYS_NS16550_REG_SIZE 1
	163	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
e6f2e902	164
6d0f6bcf	165	#define CONFIG_SYS_BAUDRATE_TABLE \
df939e16	166	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
e6f2e902	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	169	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
e6f2e902 MB	170
	171	/*
	172	* I2C
	173	*/
00f792e0 HS	174	#define CONFIG_SYS_I2C
	175	#define CONFIG_SYS_I2C_FSL
	176	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	177	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	178	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
e6f2e902 MB	179
e6f2e902 MB	180	/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
df939e16 JH	181	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	182	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
	183	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
	184	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
	185	#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
e6f2e902 MB	186
e6f2e902 MB	187	/* I2C RTC */
df939e16 JH	188	#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
df939e16 JH	189	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
e6f2e902 MB	190
e6f2e902 MB	191	/* I2C SYSMON (LM75) */
df939e16 JH	192	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
df939e16 JH	193	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	194	#define CONFIG_SYS_DTT_MAX_TEMP 70
6d0f6bcf JCPV	195	#define CONFIG_SYS_DTT_LOW_TEMP -30
df939e16	196	#define CONFIG_SYS_DTT_HYSTERESIS 3
e6f2e902 MB	197
	198	/*
	199	* TSEC
	200	*/
53677ef1	201	#define CONFIG_TSEC_ENET /* tsec ethernet support */
e6f2e902 MB	202	#define CONFIG_MII
e6f2e902 MB	203
6d0f6bcf	204	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
df939e16	205	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	206	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
df939e16	207	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
e6f2e902 MB	208
	209	#if defined(CONFIG_TSEC_ENET)
	210
255a3577 KP	211	#define CONFIG_TSEC1 1
	212	#define CONFIG_TSEC1_NAME "TSEC0"
	213	#define CONFIG_TSEC2 1
	214	#define CONFIG_TSEC2_NAME "TSEC1"
df939e16 JH	215	#define TSEC1_PHY_ADDR 2
	216	#define TSEC2_PHY_ADDR 1
	217	#define TSEC1_PHYIDX 0
	218	#define TSEC2_PHYIDX 0
3a79013e AF	219	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	220	#define TSEC2_FLAGS TSEC_GIGABIT
e6f2e902 MB	221
e6f2e902 MB	222	/* Options are: TSEC[0-1] */
df939e16	223	#define CONFIG_ETHPRIME "TSEC0"
e6f2e902 MB	224
	225	#endif /* CONFIG_TSEC_ENET */
	226
	227	/*
	228	* General PCI
	229	* Addresses are mapped 1-1.
	230	*/
6902df56 RJ	231	#define CONFIG_PCI
6902df56 RJ	232
e6f2e902 MB	233	#if defined(CONFIG_PCI)
e6f2e902 MB	234
df939e16 JH	235	#define CONFIG_PCI_PNP /* do pci plug-and-play */
df939e16 JH	236	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6902df56 RJ	237
6902df56 RJ	238	/* PCI1 host bridge */
df939e16 JH	239	#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
	240	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	241	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	242	#define CONFIG_SYS_PCI1_MMIO_BASE \
	243	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
	244	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	245	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	246	#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
	247	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	248	#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
e6f2e902	249
e6f2e902	250	#undef CONFIG_EEPRO100
63ff004c	251	#define CONFIG_EEPRO100
e6f2e902 MB	252	#undef CONFIG_TULIP
	253
	254	#if !defined(CONFIG_PCI_PNP)
6d0f6bcf JCPV	255	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
6d0f6bcf JCPV	256	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
6902df56	257	#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
e6f2e902 MB	258	#endif
e6f2e902 MB	259
6d0f6bcf	260	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
e6f2e902 MB	261
	262	#endif /* CONFIG_PCI */
	263
	264	/*
	265	* Environment
	266	*/
df939e16 JH	267	#define CONFIG_ENV_IS_IN_FLASH 1
	268	#define CONFIG_ENV_ADDR \
	269	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	270	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
	271	#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
929b79a0 WD	272	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	273	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	274
df939e16 JH	275	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
df939e16 JH	276	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
e6f2e902	277
a1aa0bb5 JL	278	/*
	279	* BOOTP options
	280	*/
	281	#define CONFIG_BOOTP_BOOTFILESIZE
	282	#define CONFIG_BOOTP_BOOTPATH
	283	#define CONFIG_BOOTP_GATEWAY
	284	#define CONFIG_BOOTP_HOSTNAME
	285
	286
2694690e JL	287	/*
	288	* Command line configuration.
	289	*/
4681e673	290	#define CONFIG_CMD_ASKENV
2694690e	291	#define CONFIG_CMD_DATE
4681e673	292	#define CONFIG_CMD_DHCP
2694690e JL	293	#define CONFIG_CMD_DTT
	294	#define CONFIG_CMD_EEPROM
	295	#define CONFIG_CMD_I2C
	296	#define CONFIG_CMD_JFFS2
	297	#define CONFIG_CMD_MII
	298	#define CONFIG_CMD_PING
4681e673 WD	299	#define CONFIG_CMD_REGINFO
4681e673 WD	300	#define CONFIG_CMD_SNTP
e6f2e902 MB	301
e6f2e902 MB	302	#if defined(CONFIG_PCI)
2694690e	303	#define CONFIG_CMD_PCI
e6f2e902 MB	304	#endif
e6f2e902 MB	305
e6f2e902 MB	306	/*
	307	* Miscellaneous configurable options
	308	*/
df939e16 JH	309	#define CONFIG_SYS_LONGHELP /* undef to save memory */
df939e16 JH	310	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
e6f2e902	311
df939e16 JH	312	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
df939e16 JH	313	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
a059e90e	314
df939e16	315	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
2751a95a	316
2694690e	317	#if defined(CONFIG_CMD_KGDB)
df939e16	318	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e6f2e902	319	#else
df939e16	320	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e6f2e902 MB	321	#endif
e6f2e902 MB	322
df939e16 JH	323	/* Print Buffer Size */
	324	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	325	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	326	/* Boot Argument Buffer Size */
	327	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
e6f2e902	328
df939e16	329	#undef CONFIG_WATCHDOG /* watchdog disabled */
e6f2e902	330
4681e673 WD	331	/* pass open firmware flat tree */
	332	#define CONFIG_OF_LIBFDT 1
	333	#define CONFIG_OF_BOARD_SETUP 1
	334	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	335
e6f2e902 MB	336	/*
e6f2e902 MB	337	* For booting Linux, the board info and command line data
9f530d59	338	* have to be in the first 256 MB of memory, since this is
e6f2e902 MB	339	* the maximum mapped by the Linux kernel during initialization.
e6f2e902 MB	340	*/
df939e16 JH	341	/* Initial Memory map for Linux */
df939e16 JH	342	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
e6f2e902	343
6d0f6bcf	344	#define CONFIG_SYS_HRCW_LOW (\
e6f2e902 MB	345	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	346	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	347	HRCWL_CSB_TO_CLKIN_4X1 \|\
	348	HRCWL_VCO_1X2 \|\
	349	HRCWL_CORE_TO_CSB_2X1)
	350
	351	#if defined(PCI_64BIT)
6d0f6bcf	352	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	353	HRCWH_PCI_HOST \|\
	354	HRCWH_64_BIT_PCI \|\
	355	HRCWH_PCI1_ARBITER_ENABLE \|\
	356	HRCWH_PCI2_ARBITER_DISABLE \|\
	357	HRCWH_CORE_ENABLE \|\
	358	HRCWH_FROM_0X00000100 \|\
	359	HRCWH_BOOTSEQ_DISABLE \|\
	360	HRCWH_SW_WATCHDOG_DISABLE \|\
	361	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	362	HRCWH_TSEC1M_IN_GMII \|\
df939e16	363	HRCWH_TSEC2M_IN_GMII)
e6f2e902	364	#else
6d0f6bcf	365	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	366	HRCWH_PCI_HOST \|\
	367	HRCWH_32_BIT_PCI \|\
	368	HRCWH_PCI1_ARBITER_ENABLE \|\
6902df56	369	HRCWH_PCI2_ARBITER_DISABLE \|\
e6f2e902 MB	370	HRCWH_CORE_ENABLE \|\
	371	HRCWH_FROM_0X00000100 \|\
	372	HRCWH_BOOTSEQ_DISABLE \|\
	373	HRCWH_SW_WATCHDOG_DISABLE \|\
	374	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	375	HRCWH_TSEC1M_IN_GMII \|\
df939e16	376	HRCWH_TSEC2M_IN_GMII)
e6f2e902 MB	377	#endif
e6f2e902 MB	378
9260a561	379	/* System IO Config */
3c9b1ee1	380	#define CONFIG_SYS_SICRH 0
6d0f6bcf	381	#define CONFIG_SYS_SICRL SICRL_LDP_A
9260a561	382
e6f2e902	383	/* i-cache and d-cache disabled */
6d0f6bcf	384	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	385	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
1a2e203b KP	386	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	387	#define CONFIG_SYS_HID2 HID2_HBE
e6f2e902	388
31d82672 BB	389	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	390
2688e2f9	391	/* DDR 0 - 512M */
df939e16	392	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	393	\| BATL_PP_RW \
df939e16 JH	394	\| BATL_MEMCOHERENCE)
	395	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	396	\| BATU_BL_256M \
	397	\| BATU_VS \
	398	\| BATU_VP)
	399	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
72cd4087	400	\| BATL_PP_RW \
df939e16 JH	401	\| BATL_MEMCOHERENCE)
	402	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
	403	\| BATU_BL_256M \
	404	\| BATU_VS \
	405	\| BATU_VP)
2688e2f9 KG	406
2688e2f9 KG	407	/* stack in DCACHE @ 512M (no backing mem) */
df939e16	408	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
72cd4087	409	\| BATL_PP_RW \
df939e16 JH	410	\| BATL_MEMCOHERENCE)
	411	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
	412	\| BATU_BL_128K \
	413	\| BATU_VS \
	414	\| BATU_VP)
2688e2f9 KG	415
2688e2f9 KG	416	/* PCI */
6fe16a87	417	#ifdef CONFIG_PCI
842033e6	418	#define CONFIG_PCI_INDIRECT_BRIDGE
df939e16	419	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
72cd4087	420	\| BATL_PP_RW \
df939e16 JH	421	\| BATL_MEMCOHERENCE)
	422	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
	423	\| BATU_BL_256M \
	424	\| BATU_VS \
	425	\| BATU_VP)
	426	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	427	\| BATL_PP_RW \
df939e16 JH	428	\| BATL_MEMCOHERENCE \
	429	\| BATL_GUARDEDSTORAGE)
	430	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
	431	\| BATU_BL_256M \
	432	\| BATU_VS \
	433	\| BATU_VP)
	434	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
72cd4087	435	\| BATL_PP_RW \
df939e16 JH	436	\| BATL_CACHEINHIBIT \
	437	\| BATL_GUARDEDSTORAGE)
	438	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
	439	\| BATU_BL_16M \
	440	\| BATU_VS \
	441	\| BATU_VP)
6fe16a87	442	#else
6d0f6bcf JCPV	443	#define CONFIG_SYS_IBAT3L (0)
	444	#define CONFIG_SYS_IBAT3U (0)
	445	#define CONFIG_SYS_IBAT4L (0)
	446	#define CONFIG_SYS_IBAT4U (0)
	447	#define CONFIG_SYS_IBAT5L (0)
	448	#define CONFIG_SYS_IBAT5U (0)
6fe16a87	449	#endif
2688e2f9 KG	450
2688e2f9 KG	451	/* IMMRBAR */
df939e16	452	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
72cd4087	453	\| BATL_PP_RW \
df939e16 JH	454	\| BATL_CACHEINHIBIT \
	455	\| BATL_GUARDEDSTORAGE)
	456	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
	457	\| BATU_BL_1M \
	458	\| BATU_VS \
	459	\| BATU_VP)
2688e2f9 KG	460
2688e2f9 KG	461	/* FLASH */
df939e16	462	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
72cd4087	463	\| BATL_PP_RW \
df939e16 JH	464	\| BATL_CACHEINHIBIT \
	465	\| BATL_GUARDEDSTORAGE)
	466	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
	467	\| BATU_BL_256M \
	468	\| BATU_VS \
	469	\| BATU_VP)
6d0f6bcf JCPV	470
	471	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	472	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	473	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	474	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	475	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	476	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	477	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	478	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	479	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	480	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	481	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	482	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	483	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	484	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	485	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	486	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
2688e2f9	487
2694690e	488	#if defined(CONFIG_CMD_KGDB)
e6f2e902	489	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
e6f2e902 MB	490	#endif
	491
	492	/*
	493	* Environment Configuration
	494	*/
	495
df939e16 JH	496	/* default location for tftp and bootm */
df939e16 JH	497	#define CONFIG_LOADADDR 400000
e6f2e902 MB	498
e6f2e902 MB	499	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
df939e16	500	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
e6f2e902 MB	501
	502	#define CONFIG_BAUDRATE 115200
	503
	504	#define CONFIG_PREBOOT "echo;" \
32bf3d14	505	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
e6f2e902 MB	506	"echo"
	507
	508	#undef CONFIG_BOOTARGS
	509
	510	#define CONFIG_EXTRA_ENV_SETTINGS \
	511	"netdev=eth0\0" \
b931b3a9	512	"hostname=tqm834x\0" \
e6f2e902	513	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	514	"nfsroot=${serverip}:${rootpath}\0" \
e6f2e902	515	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	516	"addip=setenv bootargs ${bootargs} " \
	517	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	518	":${hostname}:${netdev}:off panic=1\0" \
df939e16	519	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
4681e673	520	"flash_nfs_old=run nfsargs addip addcons;" \
fe126d8b	521	"bootm ${kernel_addr}\0" \
4681e673 WD	522	"flash_nfs=run nfsargs addip addcons;" \
	523	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	524	"flash_self_old=run ramargs addip addcons;" \
fe126d8b	525	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
4681e673 WD	526	"flash_self=run ramargs addip addcons;" \
	527	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	528	"net_nfs_old=tftp 400000 ${bootfile};" \
	529	"run nfsargs addip addcons;bootm\0" \
	530	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	531	"tftp ${fdt_addr_r} ${fdt_file}; " \
	532	"run nfsargs addip addcons; " \
	533	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
e6f2e902	534	"rootpath=/opt/eldk/ppc_6xx\0" \
4681e673 WD	535	"bootfile=tqm834x/uImage\0" \
	536	"fdtfile=tqm834x/tqm834x.dtb\0" \
	537	"kernel_addr_r=400000\0" \
	538	"fdt_addr_r=600000\0" \
	539	"ramdisk_addr_r=800000\0" \
	540	"kernel_addr=800C0000\0" \
	541	"fdt_addr=800A0000\0" \
	542	"ramdisk_addr=80300000\0" \
	543	"u-boot=tqm834x/u-boot.bin\0" \
	544	"load=tftp 200000 ${u-boot}\0" \
	545	"update=protect off 80000000 +${filesize};" \
	546	"era 80000000 +${filesize};" \
	547	"cp.b 200000 80000000 ${filesize}\0" \
d8ab58b2	548	"upd=run load update\0" \
e6f2e902 MB	549	""
	550
	551	#define CONFIG_BOOTCOMMAND "run flash_self"
	552
	553	/*
	554	* JFFS2 partitions
	555	*/
	556	/* mtdparts command line support */
68d7d651	557	#define CONFIG_CMD_MTDPARTS
942556a9 SR	558	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	559	#define CONFIG_FLASH_CFI_MTD
e6f2e902 MB	560	#define MTDIDS_DEFAULT "nor0=TQM834x-0"
	561
	562	/* default mtd partition table */
df939e16 JH	563	#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
	564	"1m(kernel),2m(initrd)," \
	565	"-(user);" \
e6f2e902 MB	566
e6f2e902 MB	567	#endif /* __CONFIG_H */