[people/ms/u-boot.git] / include / configs / TQM834x.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * TQM8349 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC834x		1	/* MPC834x specific */
#define CONFIG_MPC8349		1	/* MPC8349 specific */
#define CONFIG_TQM834X		1	/* TQM834X board specific */

#define	CONFIG_SYS_TEXT_BASE	0x80000000

/* IMMR Base Address Register, use Freescale default: 0xff400000 */
#define CONFIG_SYS_IMMR		0xff400000

/* System clock. Primary input clock when in PCI host mode */
#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */

/*
 * Local Bus LCRR
 *    LCRR:  DLL bypass, Clock divider is 8
 *
 *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
 *
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8

/* board pre init: do not call, nothing to do */

/* detect the number of flash banks */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * DDR Setup
 */
				/* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */

#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * FLASH bank number detection
 */

/*
 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
 * Flash banks has to be determined at runtime and stored in a gloabl variable
 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
 * flash_info, and should be made sufficiently large to accomodate the number
 * of banks that might actually be detected.  Since most (all?) Flash related
 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
 * the board, it is defined as tqm834x_num_flash_banks.
 */
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2

#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */

/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
				| BR_MS_GPCM \
				| BR_PS_32 \
				| BR_V)

/* FLASH timing (0x0000_0c54) */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV4 \
					| OR_GPCM_SCY_5 \
					| OR_GPCM_TRLX)

#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */

#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
					| CONFIG_SYS_OR_TIMING_FLASH)

#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE

/* disable remaining mappings */
#define CONFIG_SYS_BR1_PRELIM		0x00000000
#define CONFIG_SYS_OR1_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000

#define CONFIG_SYS_BR2_PRELIM		0x00000000
#define CONFIG_SYS_OR2_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000

#define CONFIG_SYS_BR3_PRELIM		0x00000000
#define CONFIG_SYS_OR3_PRELIM		0x00000000
#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000

/*
 * Monitor config
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#else
# undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

				/* Reserve 384 kB = 3 sect. for Mon */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
				/* Reserve 512 kB for malloc */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */

/* I2C RTC */
#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_MII

#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

/* PCI1 host bridge */
#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */

#undef CONFIG_EEPRO100
#define CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
#endif

#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */

#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */

#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

				/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	0
#define CONFIG_SYS_SICRL	SICRL_LDP_A

/* i-cache and d-cache disabled */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2	HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR 0 - 512M */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE @ 512M (no backing mem) */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)

/* PCI */
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE \
				| BATU_BL_16M \
				| BATU_VS \
				| BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#endif

/* IMMRBAR */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR \
				| BATU_BL_1M \
				| BATU_VS \
				| BATU_VP)

/* FLASH */
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		400000

#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=tqm834x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
	"flash_nfs_old=run nfsargs addip addcons;"			\
		"bootm ${kernel_addr}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self_old=run ramargs addip addcons;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs_old=tftp 400000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons; "				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=tqm834x/uImage\0"					\
	"fdtfile=tqm834x/tqm834x.dtb\0"					\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"ramdisk_addr_r=800000\0"					\
	"kernel_addr=800C0000\0"					\
	"fdt_addr=800A0000\0"						\
	"ramdisk_addr=80300000\0"					\
	"u-boot=tqm834x/u-boot.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off 80000000 +${filesize};"			\
		"era 80000000 +${filesize};"				\
		"cp.b 200000 80000000 ${filesize}\0"			\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * JFFS2 partitions
 */
/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM834x-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
						"1m(kernel),2m(initrd)," \
						"-(user);" \

#endif	/* __CONFIG_H */
Commit	Line	Data
e6f2e902 MB	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
e6f2e902 MB	6	*/
	7
	8	/*
	9	* TQM8349 board configuration file
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
e6f2e902 MB	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 Family */
2c7920af	19	#define CONFIG_MPC834x 1 /* MPC834x specific */
9ca880a2	20	#define CONFIG_MPC8349 1 /* MPC8349 specific */
e6f2e902 MB	21	#define CONFIG_TQM834X 1 /* TQM834X board specific */
e6f2e902 MB	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x80000000
2ae18241 WD	24
16263087	25	/* IMMR Base Address Register, use Freescale default: 0xff400000 */
6d0f6bcf	26	#define CONFIG_SYS_IMMR 0xff400000
e6f2e902 MB	27
	28	/* System clock. Primary input clock when in PCI host mode */
	29	#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
	30
	31	/*
	32	* Local Bus LCRR
	33	* LCRR: DLL bypass, Clock divider is 8
	34	*
	35	* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
	36	*
	37	* External Local Bus rate is
	38	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	39	*/
c7190f02 KP	40	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	41	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
e6f2e902 MB	42
e6f2e902 MB	43	/* board pre init: do not call, nothing to do */
e6f2e902 MB	44
	45	/* detect the number of flash banks */
	46	#define CONFIG_BOARD_EARLY_INIT_R
	47
	48	/*
	49	* DDR Setup
	50	*/
df939e16 JH	51	/* DDR is system memory*/
	52	#define CONFIG_SYS_DDR_BASE 0x00000000
	53	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	54	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
df939e16 JH	55	#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
	56	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	57	#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
e6f2e902	58
df939e16	59	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
6d0f6bcf JCPV	60	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
6d0f6bcf JCPV	61	#define CONFIG_SYS_MEMTEST_END 0x00100000
e6f2e902 MB	62
	63	/*
	64	* FLASH on the Local Bus
	65	*/
df939e16 JH	66	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
df939e16 JH	67	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
6d0f6bcf JCPV	68	#undef CONFIG_SYS_FLASH_CHECKSUM
	69	#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
	70	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
df939e16	71	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
a3455c00	72	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
e6f2e902 MB	73
	74	/*
	75	* FLASH bank number detection
	76	*/
	77
	78	/*
df939e16 JH	79	* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
	80	* Flash banks has to be determined at runtime and stored in a gloabl variable
	81	* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
	82	* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
	83	* flash_info, and should be made sufficiently large to accomodate the number
	84	* of banks that might actually be detected. Since most (all?) Flash related
	85	* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
	86	* the board, it is defined as tqm834x_num_flash_banks.
e6f2e902	87	*/
6d0f6bcf	88	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
e6f2e902	89
df939e16	90	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
e6f2e902 MB	91
e6f2e902 MB	92	/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
df939e16 JH	93	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
	94	\| BR_MS_GPCM \
	95	\| BR_PS_32 \
	96	\| BR_V)
e6f2e902 MB	97
e6f2e902 MB	98	/* FLASH timing (0x0000_0c54) */
df939e16 JH	99	#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
	100	\| OR_GPCM_ACS_DIV4 \
	101	\| OR_GPCM_SCY_5 \
	102	\| OR_GPCM_TRLX)
e6f2e902	103
7d6a0982	104	#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
e6f2e902	105
df939e16 JH	106	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
df939e16 JH	107	\| CONFIG_SYS_OR_TIMING_FLASH)
e6f2e902	108
7d6a0982	109	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_1GB)
6902df56	110
df939e16 JH	111	/* Window base at flash base */
df939e16 JH	112	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
e6f2e902 MB	113
e6f2e902 MB	114	/* disable remaining mappings */
6d0f6bcf JCPV	115	#define CONFIG_SYS_BR1_PRELIM 0x00000000
	116	#define CONFIG_SYS_OR1_PRELIM 0x00000000
	117	#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
	118	#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
	119
	120	#define CONFIG_SYS_BR2_PRELIM 0x00000000
	121	#define CONFIG_SYS_OR2_PRELIM 0x00000000
	122	#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
	123	#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
	124
	125	#define CONFIG_SYS_BR3_PRELIM 0x00000000
	126	#define CONFIG_SYS_OR3_PRELIM 0x00000000
	127	#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
	128	#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
e6f2e902 MB	129
	130	/*
	131	* Monitor config
	132	*/
14d0a02a	133	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
e6f2e902	134
6d0f6bcf	135	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
4681e673	136	# define CONFIG_SYS_RAMBOOT
e6f2e902	137	#else
4681e673	138	# undef CONFIG_SYS_RAMBOOT
e6f2e902 MB	139	#endif
e6f2e902 MB	140
6d0f6bcf	141	#define CONFIG_SYS_INIT_RAM_LOCK 1
df939e16 JH	142	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
df939e16 JH	143	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
e6f2e902	144
df939e16 JH	145	#define CONFIG_SYS_GBL_DATA_OFFSET \
df939e16 JH	146	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	147	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e6f2e902	148
df939e16 JH	149	/* Reserve 384 kB = 3 sect. for Mon */
	150	#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
	151	/* Reserve 512 kB for malloc */
	152	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
e6f2e902 MB	153
	154	/*
	155	* Serial Port
	156	*/
	157	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	158	#define CONFIG_SYS_NS16550_SERIAL
	159	#define CONFIG_SYS_NS16550_REG_SIZE 1
	160	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
e6f2e902	161
6d0f6bcf	162	#define CONFIG_SYS_BAUDRATE_TABLE \
df939e16	163	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
e6f2e902	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	166	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
e6f2e902 MB	167
	168	/*
	169	* I2C
	170	*/
00f792e0 HS	171	#define CONFIG_SYS_I2C
	172	#define CONFIG_SYS_I2C_FSL
	173	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	174	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	175	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
e6f2e902 MB	176
e6f2e902 MB	177	/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
df939e16 JH	178	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	179	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
	180	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
	181	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
e6f2e902 MB	182
e6f2e902 MB	183	/* I2C RTC */
df939e16 JH	184	#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
df939e16 JH	185	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
e6f2e902	186
e6f2e902 MB	187	/*
	188	* TSEC
	189	*/
53677ef1	190	#define CONFIG_TSEC_ENET /* tsec ethernet support */
e6f2e902 MB	191	#define CONFIG_MII
e6f2e902 MB	192
6d0f6bcf	193	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
df939e16	194	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	195	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
df939e16	196	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
e6f2e902 MB	197
	198	#if defined(CONFIG_TSEC_ENET)
	199
255a3577 KP	200	#define CONFIG_TSEC1 1
	201	#define CONFIG_TSEC1_NAME "TSEC0"
	202	#define CONFIG_TSEC2 1
	203	#define CONFIG_TSEC2_NAME "TSEC1"
df939e16 JH	204	#define TSEC1_PHY_ADDR 2
	205	#define TSEC2_PHY_ADDR 1
	206	#define TSEC1_PHYIDX 0
	207	#define TSEC2_PHYIDX 0
3a79013e AF	208	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	209	#define TSEC2_FLAGS TSEC_GIGABIT
e6f2e902 MB	210
e6f2e902 MB	211	/* Options are: TSEC[0-1] */
df939e16	212	#define CONFIG_ETHPRIME "TSEC0"
e6f2e902 MB	213
	214	#endif /* CONFIG_TSEC_ENET */
	215
	216	/*
	217	* General PCI
	218	* Addresses are mapped 1-1.
	219	*/
6902df56	220
e6f2e902 MB	221	#if defined(CONFIG_PCI)
e6f2e902 MB	222
df939e16	223	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6902df56 RJ	224
6902df56 RJ	225	/* PCI1 host bridge */
df939e16 JH	226	#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
	227	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	228	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	229	#define CONFIG_SYS_PCI1_MMIO_BASE \
	230	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
	231	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	232	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	233	#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
	234	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	235	#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
e6f2e902	236
e6f2e902	237	#undef CONFIG_EEPRO100
63ff004c	238	#define CONFIG_EEPRO100
e6f2e902 MB	239	#undef CONFIG_TULIP
	240
	241	#if !defined(CONFIG_PCI_PNP)
6d0f6bcf JCPV	242	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
6d0f6bcf JCPV	243	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
6902df56	244	#define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
e6f2e902 MB	245	#endif
e6f2e902 MB	246
6d0f6bcf	247	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
e6f2e902 MB	248
	249	#endif /* CONFIG_PCI */
	250
	251	/*
	252	* Environment
	253	*/
df939e16 JH	254	#define CONFIG_ENV_IS_IN_FLASH 1
	255	#define CONFIG_ENV_ADDR \
	256	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	257	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
	258	#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
929b79a0 WD	259	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	260	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	261
df939e16 JH	262	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
df939e16 JH	263	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
e6f2e902	264
a1aa0bb5 JL	265	/*
	266	* BOOTP options
	267	*/
	268	#define CONFIG_BOOTP_BOOTFILESIZE
	269	#define CONFIG_BOOTP_BOOTPATH
	270	#define CONFIG_BOOTP_GATEWAY
	271	#define CONFIG_BOOTP_HOSTNAME
	272
2694690e JL	273	/*
	274	* Command line configuration.
	275	*/
e6f2e902	276	#if defined(CONFIG_PCI)
2694690e	277	#define CONFIG_CMD_PCI
e6f2e902 MB	278	#endif
e6f2e902 MB	279
e6f2e902 MB	280	/*
	281	* Miscellaneous configurable options
	282	*/
df939e16 JH	283	#define CONFIG_SYS_LONGHELP /* undef to save memory */
df939e16 JH	284	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
e6f2e902	285
df939e16 JH	286	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
df939e16 JH	287	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
a059e90e	288
2694690e	289	#if defined(CONFIG_CMD_KGDB)
df939e16	290	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e6f2e902	291	#else
df939e16	292	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e6f2e902 MB	293	#endif
e6f2e902 MB	294
df939e16 JH	295	/* Print Buffer Size */
	296	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	297	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	298	/* Boot Argument Buffer Size */
	299	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
e6f2e902	300
df939e16	301	#undef CONFIG_WATCHDOG /* watchdog disabled */
e6f2e902 MB	302
	303	/*
	304	* For booting Linux, the board info and command line data
9f530d59	305	* have to be in the first 256 MB of memory, since this is
e6f2e902 MB	306	* the maximum mapped by the Linux kernel during initialization.
e6f2e902 MB	307	*/
df939e16 JH	308	/* Initial Memory map for Linux */
df939e16 JH	309	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
e6f2e902	310
6d0f6bcf	311	#define CONFIG_SYS_HRCW_LOW (\
e6f2e902 MB	312	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	313	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	314	HRCWL_CSB_TO_CLKIN_4X1 \|\
	315	HRCWL_VCO_1X2 \|\
	316	HRCWL_CORE_TO_CSB_2X1)
	317
	318	#if defined(PCI_64BIT)
6d0f6bcf	319	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	320	HRCWH_PCI_HOST \|\
	321	HRCWH_64_BIT_PCI \|\
	322	HRCWH_PCI1_ARBITER_ENABLE \|\
	323	HRCWH_PCI2_ARBITER_DISABLE \|\
	324	HRCWH_CORE_ENABLE \|\
	325	HRCWH_FROM_0X00000100 \|\
	326	HRCWH_BOOTSEQ_DISABLE \|\
	327	HRCWH_SW_WATCHDOG_DISABLE \|\
	328	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	329	HRCWH_TSEC1M_IN_GMII \|\
df939e16	330	HRCWH_TSEC2M_IN_GMII)
e6f2e902	331	#else
6d0f6bcf	332	#define CONFIG_SYS_HRCW_HIGH (\
e6f2e902 MB	333	HRCWH_PCI_HOST \|\
	334	HRCWH_32_BIT_PCI \|\
	335	HRCWH_PCI1_ARBITER_ENABLE \|\
6902df56	336	HRCWH_PCI2_ARBITER_DISABLE \|\
e6f2e902 MB	337	HRCWH_CORE_ENABLE \|\
	338	HRCWH_FROM_0X00000100 \|\
	339	HRCWH_BOOTSEQ_DISABLE \|\
	340	HRCWH_SW_WATCHDOG_DISABLE \|\
	341	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	342	HRCWH_TSEC1M_IN_GMII \|\
df939e16	343	HRCWH_TSEC2M_IN_GMII)
e6f2e902 MB	344	#endif
e6f2e902 MB	345
9260a561	346	/* System IO Config */
3c9b1ee1	347	#define CONFIG_SYS_SICRH 0
6d0f6bcf	348	#define CONFIG_SYS_SICRL SICRL_LDP_A
9260a561	349
e6f2e902	350	/* i-cache and d-cache disabled */
6d0f6bcf	351	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	352	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
1a2e203b KP	353	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	354	#define CONFIG_SYS_HID2 HID2_HBE
e6f2e902	355
31d82672 BB	356	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	357
2688e2f9	358	/* DDR 0 - 512M */
df939e16	359	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	360	\| BATL_PP_RW \
df939e16 JH	361	\| BATL_MEMCOHERENCE)
	362	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	363	\| BATU_BL_256M \
	364	\| BATU_VS \
	365	\| BATU_VP)
	366	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
72cd4087	367	\| BATL_PP_RW \
df939e16 JH	368	\| BATL_MEMCOHERENCE)
	369	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
	370	\| BATU_BL_256M \
	371	\| BATU_VS \
	372	\| BATU_VP)
2688e2f9 KG	373
2688e2f9 KG	374	/* stack in DCACHE @ 512M (no backing mem) */
df939e16	375	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
72cd4087	376	\| BATL_PP_RW \
df939e16 JH	377	\| BATL_MEMCOHERENCE)
	378	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
	379	\| BATU_BL_128K \
	380	\| BATU_VS \
	381	\| BATU_VP)
2688e2f9 KG	382
2688e2f9 KG	383	/* PCI */
6fe16a87	384	#ifdef CONFIG_PCI
842033e6	385	#define CONFIG_PCI_INDIRECT_BRIDGE
df939e16	386	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
72cd4087	387	\| BATL_PP_RW \
df939e16 JH	388	\| BATL_MEMCOHERENCE)
	389	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
	390	\| BATU_BL_256M \
	391	\| BATU_VS \
	392	\| BATU_VP)
	393	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	394	\| BATL_PP_RW \
df939e16 JH	395	\| BATL_MEMCOHERENCE \
	396	\| BATL_GUARDEDSTORAGE)
	397	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
	398	\| BATU_BL_256M \
	399	\| BATU_VS \
	400	\| BATU_VP)
	401	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
72cd4087	402	\| BATL_PP_RW \
df939e16 JH	403	\| BATL_CACHEINHIBIT \
	404	\| BATL_GUARDEDSTORAGE)
	405	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
	406	\| BATU_BL_16M \
	407	\| BATU_VS \
	408	\| BATU_VP)
6fe16a87	409	#else
6d0f6bcf JCPV	410	#define CONFIG_SYS_IBAT3L (0)
	411	#define CONFIG_SYS_IBAT3U (0)
	412	#define CONFIG_SYS_IBAT4L (0)
	413	#define CONFIG_SYS_IBAT4U (0)
	414	#define CONFIG_SYS_IBAT5L (0)
	415	#define CONFIG_SYS_IBAT5U (0)
6fe16a87	416	#endif
2688e2f9 KG	417
2688e2f9 KG	418	/* IMMRBAR */
df939e16	419	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
72cd4087	420	\| BATL_PP_RW \
df939e16 JH	421	\| BATL_CACHEINHIBIT \
	422	\| BATL_GUARDEDSTORAGE)
	423	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
	424	\| BATU_BL_1M \
	425	\| BATU_VS \
	426	\| BATU_VP)
2688e2f9 KG	427
2688e2f9 KG	428	/* FLASH */
df939e16	429	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
72cd4087	430	\| BATL_PP_RW \
df939e16 JH	431	\| BATL_CACHEINHIBIT \
	432	\| BATL_GUARDEDSTORAGE)
	433	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
	434	\| BATU_BL_256M \
	435	\| BATU_VS \
	436	\| BATU_VP)
6d0f6bcf JCPV	437
	438	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	439	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	440	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	441	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	442	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	443	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	444	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	445	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	446	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	447	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	448	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	449	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	450	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	451	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	452	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	453	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
2688e2f9	454
2694690e	455	#if defined(CONFIG_CMD_KGDB)
e6f2e902	456	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
e6f2e902 MB	457	#endif
	458
	459	/*
	460	* Environment Configuration
	461	*/
	462
df939e16 JH	463	/* default location for tftp and bootm */
df939e16 JH	464	#define CONFIG_LOADADDR 400000
e6f2e902	465
df939e16	466	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
e6f2e902	467
e6f2e902	468	#define CONFIG_PREBOOT "echo;" \
32bf3d14	469	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
e6f2e902 MB	470	"echo"
	471
	472	#undef CONFIG_BOOTARGS
	473
	474	#define CONFIG_EXTRA_ENV_SETTINGS \
	475	"netdev=eth0\0" \
b931b3a9	476	"hostname=tqm834x\0" \
e6f2e902	477	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	478	"nfsroot=${serverip}:${rootpath}\0" \
e6f2e902	479	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	480	"addip=setenv bootargs ${bootargs} " \
	481	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	482	":${hostname}:${netdev}:off panic=1\0" \
df939e16	483	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
4681e673	484	"flash_nfs_old=run nfsargs addip addcons;" \
fe126d8b	485	"bootm ${kernel_addr}\0" \
4681e673 WD	486	"flash_nfs=run nfsargs addip addcons;" \
	487	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	488	"flash_self_old=run ramargs addip addcons;" \
fe126d8b	489	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
4681e673 WD	490	"flash_self=run ramargs addip addcons;" \
	491	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	492	"net_nfs_old=tftp 400000 ${bootfile};" \
	493	"run nfsargs addip addcons;bootm\0" \
	494	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	495	"tftp ${fdt_addr_r} ${fdt_file}; " \
	496	"run nfsargs addip addcons; " \
	497	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
e6f2e902	498	"rootpath=/opt/eldk/ppc_6xx\0" \
4681e673 WD	499	"bootfile=tqm834x/uImage\0" \
	500	"fdtfile=tqm834x/tqm834x.dtb\0" \
	501	"kernel_addr_r=400000\0" \
	502	"fdt_addr_r=600000\0" \
	503	"ramdisk_addr_r=800000\0" \
	504	"kernel_addr=800C0000\0" \
	505	"fdt_addr=800A0000\0" \
	506	"ramdisk_addr=80300000\0" \
	507	"u-boot=tqm834x/u-boot.bin\0" \
	508	"load=tftp 200000 ${u-boot}\0" \
	509	"update=protect off 80000000 +${filesize};" \
	510	"era 80000000 +${filesize};" \
	511	"cp.b 200000 80000000 ${filesize}\0" \
d8ab58b2	512	"upd=run load update\0" \
e6f2e902 MB	513	""
	514
	515	#define CONFIG_BOOTCOMMAND "run flash_self"
	516
	517	/*
	518	* JFFS2 partitions
	519	*/
	520	/* mtdparts command line support */
68d7d651	521	#define CONFIG_CMD_MTDPARTS
942556a9 SR	522	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	523	#define CONFIG_FLASH_CFI_MTD
e6f2e902 MB	524	#define MTDIDS_DEFAULT "nor0=TQM834x-0"
	525
	526	/* default mtd partition table */
df939e16 JH	527	#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
	528	"1m(kernel),2m(initrd)," \
	529	"-(user);" \
e6f2e902 MB	530
e6f2e902 MB	531	#endif /* __CONFIG_H */