]>
Commit | Line | Data |
---|---|---|
f4675560 | 1 | /* |
23c5d253 | 2 | * (C) Copyright 2000-2014 |
f4675560 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f4675560 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
21 | #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
24 | ||
f4675560 | 25 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
26 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
27 | #define CONFIG_SYS_MAXIDLE 10 | |
f4675560 | 28 | |
ae3af05e WD |
29 | #define CONFIG_BOOTCOUNT_LIMIT |
30 | ||
f4675560 WD |
31 | |
32 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
33 | ||
32bf3d14 | 34 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
f4675560 WD |
35 | |
36 | #undef CONFIG_BOOTARGS | |
6aff3115 WD |
37 | |
38 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ae3af05e | 39 | "netdev=eth0\0" \ |
6aff3115 | 40 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 41 | "nfsroot=${serverip}:${rootpath}\0" \ |
6aff3115 | 42 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
43 | "addip=setenv bootargs ${bootargs} " \ |
44 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
45 | ":${hostname}:${netdev}:off panic=1\0" \ | |
6aff3115 | 46 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 47 | "bootm ${kernel_addr}\0" \ |
6aff3115 | 48 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
49 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
50 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
6aff3115 | 51 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
52 | "hostname=TQM850L\0" \ |
53 | "bootfile=TQM850L/uImage\0" \ | |
eb6da805 WD |
54 | "fdt_addr=40040000\0" \ |
55 | "kernel_addr=40060000\0" \ | |
56 | "ramdisk_addr=40200000\0" \ | |
29f8f58f WD |
57 | "u-boot=TQM850L/u-image.bin\0" \ |
58 | "load=tftp 200000 ${u-boot}\0" \ | |
59 | "update=prot off 40000000 +${filesize};" \ | |
60 | "era 40000000 +${filesize};" \ | |
61 | "cp.b 200000 40000000 ${filesize};" \ | |
62 | "sete filesize;save\0" \ | |
6aff3115 WD |
63 | "" |
64 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
f4675560 WD |
65 | |
66 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 67 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
f4675560 WD |
68 | |
69 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
70 | ||
f4675560 WD |
71 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
72 | ||
37d4bb70 JL |
73 | /* |
74 | * BOOTP options | |
75 | */ | |
76 | #define CONFIG_BOOTP_SUBNETMASK | |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_HOSTNAME | |
79 | #define CONFIG_BOOTP_BOOTPATH | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | ||
f4675560 WD |
82 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
83 | ||
2694690e JL |
84 | /* |
85 | * Command line configuration. | |
86 | */ | |
f4675560 | 87 | |
29f8f58f WD |
88 | #define CONFIG_NETCONSOLE |
89 | ||
f4675560 WD |
90 | /* |
91 | * Miscellaneous configurable options | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6aff3115 | 94 | |
2751a95a | 95 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6aff3115 | 96 | |
2694690e | 97 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 98 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
f4675560 | 99 | #else |
6d0f6bcf | 100 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
f4675560 | 101 | #endif |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
103 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
104 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
f4675560 | 105 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
107 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
f4675560 | 108 | |
6d0f6bcf | 109 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
f4675560 | 110 | |
f4675560 WD |
111 | /* |
112 | * Low Level Configuration Settings | |
113 | * (address mappings, register initial values, etc.) | |
114 | * You should know what you are doing if you make changes here. | |
115 | */ | |
116 | /*----------------------------------------------------------------------- | |
117 | * Internal Memory Mapped Register | |
118 | */ | |
6d0f6bcf | 119 | #define CONFIG_SYS_IMMR 0xFFF00000 |
f4675560 WD |
120 | |
121 | /*----------------------------------------------------------------------- | |
122 | * Definitions for initial stack pointer and data area (in DPRAM) | |
123 | */ | |
6d0f6bcf | 124 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 125 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 126 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 127 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
f4675560 WD |
128 | |
129 | /*----------------------------------------------------------------------- | |
130 | * Start addresses for the final memory configuration | |
131 | * (Set up by the startup code) | |
6d0f6bcf | 132 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
f4675560 | 133 | */ |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
135 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
136 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
137 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
138 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
f4675560 WD |
139 | |
140 | /* | |
141 | * For booting Linux, the board info and command line data | |
142 | * have to be in the first 8 MB of memory, since this is | |
143 | * the maximum mapped by the Linux kernel during initialization. | |
144 | */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
f4675560 WD |
146 | |
147 | /*----------------------------------------------------------------------- | |
148 | * FLASH organization | |
149 | */ | |
f4675560 | 150 | |
e318d9e9 | 151 | /* use CFI flash driver */ |
6d0f6bcf | 152 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 153 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
155 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
156 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
157 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
158 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
f4675560 | 159 | |
5a1aceb0 | 160 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
161 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
162 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
f4675560 WD |
163 | |
164 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
165 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
166 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
f4675560 | 167 | |
6d0f6bcf | 168 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 169 | |
7c803be2 WD |
170 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
171 | ||
29f8f58f WD |
172 | /*----------------------------------------------------------------------- |
173 | * Dynamic MTD partition support | |
174 | */ | |
68d7d651 | 175 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
176 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
177 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
178 | #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" |
179 | ||
180 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ | |
181 | "128k(dtb)," \ | |
182 | "1664k(kernel)," \ | |
183 | "2m(rootfs)," \ | |
cd82919e | 184 | "4m(data)" |
29f8f58f | 185 | |
f4675560 WD |
186 | /*----------------------------------------------------------------------- |
187 | * Hardware Information Block | |
188 | */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
190 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
191 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
f4675560 WD |
192 | |
193 | /*----------------------------------------------------------------------- | |
194 | * Cache Configuration | |
195 | */ | |
6d0f6bcf | 196 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 197 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 198 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
f4675560 WD |
199 | #endif |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * SYPCR - System Protection Control 11-9 | |
203 | * SYPCR can only be written once after reset! | |
204 | *----------------------------------------------------------------------- | |
205 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
206 | */ | |
207 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 208 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
f4675560 WD |
209 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
210 | #else | |
6d0f6bcf | 211 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
f4675560 WD |
212 | #endif |
213 | ||
214 | /*----------------------------------------------------------------------- | |
215 | * SIUMCR - SIU Module Configuration 11-6 | |
216 | *----------------------------------------------------------------------- | |
217 | * PCMCIA config., multi-function pin tri-state | |
218 | */ | |
219 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 220 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f4675560 | 221 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 222 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f4675560 WD |
223 | #endif /* CONFIG_CAN_DRIVER */ |
224 | ||
225 | /*----------------------------------------------------------------------- | |
226 | * TBSCR - Time Base Status and Control 11-26 | |
227 | *----------------------------------------------------------------------- | |
228 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
229 | */ | |
6d0f6bcf | 230 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
f4675560 WD |
231 | |
232 | /*----------------------------------------------------------------------- | |
233 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
234 | *----------------------------------------------------------------------- | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
f4675560 WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
240 | *----------------------------------------------------------------------- | |
241 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
242 | */ | |
6d0f6bcf | 243 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
f4675560 WD |
244 | |
245 | /*----------------------------------------------------------------------- | |
246 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
247 | *----------------------------------------------------------------------- | |
248 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
249 | * interrupt status bit | |
f4675560 | 250 | */ |
6d0f6bcf | 251 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
f4675560 WD |
252 | |
253 | /*----------------------------------------------------------------------- | |
254 | * SCCR - System Clock and reset Control Register 15-27 | |
255 | *----------------------------------------------------------------------- | |
256 | * Set clock output, timebase and RTC source and divider, | |
257 | * power management and some other internal clocks | |
258 | */ | |
259 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 260 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
f4675560 WD |
261 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
262 | SCCR_DFALCD00) | |
f4675560 WD |
263 | |
264 | /*----------------------------------------------------------------------- | |
265 | * PCMCIA stuff | |
266 | *----------------------------------------------------------------------- | |
267 | * | |
268 | */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
270 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
271 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
272 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
273 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
274 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
275 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
276 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
f4675560 WD |
277 | |
278 | /*----------------------------------------------------------------------- | |
279 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
280 | *----------------------------------------------------------------------- | |
281 | */ | |
282 | ||
8d1165e1 | 283 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
f4675560 WD |
284 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
285 | ||
286 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
287 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
288 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
289 | ||
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
291 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
f4675560 | 292 | |
6d0f6bcf | 293 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
f4675560 | 294 | |
6d0f6bcf | 295 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
f4675560 WD |
296 | |
297 | /* Offset for data I/O */ | |
6d0f6bcf | 298 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f4675560 WD |
299 | |
300 | /* Offset for normal register accesses */ | |
6d0f6bcf | 301 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f4675560 WD |
302 | |
303 | /* Offset for alternate registers */ | |
6d0f6bcf | 304 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
f4675560 | 305 | |
f4675560 WD |
306 | /*----------------------------------------------------------------------- |
307 | * | |
308 | *----------------------------------------------------------------------- | |
309 | * | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_DER 0 |
f4675560 WD |
312 | |
313 | /* | |
314 | * Init Memory Controller: | |
315 | * | |
316 | * BR0/1 and OR0/1 (FLASH) | |
317 | */ | |
318 | ||
319 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
320 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
321 | ||
322 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
323 | * restrict access enough to keep SRAM working (if any) | |
324 | * but not too much to meddle with FLASH accesses | |
325 | */ | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
327 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
f4675560 WD |
328 | |
329 | /* | |
330 | * FLASH timing: | |
331 | */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
f4675560 | 333 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
f4675560 | 334 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
336 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
337 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
f4675560 | 338 | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
340 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
341 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
f4675560 WD |
342 | |
343 | /* | |
344 | * BR2/3 and OR2/3 (SDRAM) | |
345 | * | |
346 | */ | |
347 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
348 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
349 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
350 | ||
351 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 352 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
f4675560 | 353 | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
355 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f4675560 WD |
356 | |
357 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
359 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f4675560 | 360 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
362 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
363 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
364 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
f4675560 WD |
365 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
366 | #endif /* CONFIG_CAN_DRIVER */ | |
367 | ||
368 | /* | |
369 | * Memory Periodic Timer Prescaler | |
370 | * | |
371 | * The Divider for PTA (refresh timer) configuration is based on an | |
372 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
373 | * the number of chip selects (NCS) and the actually needed refresh | |
374 | * rate is done by setting MPTPR. | |
375 | * | |
376 | * PTA is calculated from | |
377 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
378 | * | |
379 | * gclk CPU clock (not bus clock!) | |
380 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
381 | * | |
382 | * 4096 Rows from SDRAM example configuration | |
383 | * 1000 factor s -> ms | |
384 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
385 | * 4 Number of refresh cycles per period | |
386 | * 64 Refresh cycle in ms per number of rows | |
387 | * -------------------------------------------- | |
388 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
389 | * | |
390 | * 50 MHz => 50.000.000 / Divider = 98 | |
391 | * 66 Mhz => 66.000.000 / Divider = 129 | |
392 | * 80 Mhz => 80.000.000 / Divider = 156 | |
393 | */ | |
e9132ea9 | 394 | |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
396 | #define CONFIG_SYS_MAMR_PTA 98 | |
f4675560 WD |
397 | |
398 | /* | |
399 | * For 16 MBit, refresh rates could be 31.3 us | |
400 | * (= 64 ms / 2K = 125 / quad bursts). | |
401 | * For a simpler initialization, 15.6 us is used instead. | |
402 | * | |
6d0f6bcf JCPV |
403 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
404 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
f4675560 | 405 | */ |
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
407 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
f4675560 WD |
408 | |
409 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
410 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
411 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
f4675560 WD |
412 | |
413 | /* | |
414 | * MAMR settings for SDRAM | |
415 | */ | |
416 | ||
417 | /* 8 column SDRAM */ | |
6d0f6bcf | 418 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f4675560 WD |
419 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
420 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
421 | /* 9 column SDRAM */ | |
6d0f6bcf | 422 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f4675560 WD |
423 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
424 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
425 | ||
7026ead0 HS |
426 | #define CONFIG_HWCONFIG 1 |
427 | ||
f4675560 | 428 | #endif /* __CONFIG_H */ |