[people/ms/u-boot.git] / include / configs / TQM855M.h

/*
 * (C) Copyright 2000-2014
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_SYS_SMC_RXBUFLEN	128
#define CONFIG_SYS_MAXIDLE	10

#define	CONFIG_BOOTCOUNT_LIMIT


#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"hostname=TQM855M\0"						\
	"bootfile=TQM855M/uImage\0"					\
	"fdt_addr=40080000\0"						\
	"kernel_addr=400A0000\0"					\
	"ramdisk_addr=40280000\0"					\
	"u-boot=TQM855M/u-image.bin\0"					\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=prot off 40000000 +${filesize};"			\
		"era 40000000 +${filesize};"				\
		"cp.b 200000 40000000 ${filesize};"			\
		"sete filesize;save\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
#if 0
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

/*
 * Command line configuration.
 */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2

#define CONFIG_NETCONSOLE

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */

/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment		*/
#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"

#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
						"128k(dtb),"		\
						"1920k(kernel),"	\
						"5632(rootfs),"		\
						"4m(data)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
#define CONFIG_SYS_MAMR_PTA	98

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME		"SCC"

#define CONFIG_HWCONFIG		1

#endif	/* __CONFIG_H */
Commit	Line	Data
f12e568c	1	/*
23c5d253	2	* (C) Copyright 2000-2014
f12e568c WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
f12e568c WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
f12e568c WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
	21	#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	24
f12e568c	25	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
3cb7a480 WD	26	#define CONFIG_SYS_SMC_RXBUFLEN 128
3cb7a480 WD	27	#define CONFIG_SYS_MAXIDLE 10
f12e568c	28
ae3af05e	29	#define CONFIG_BOOTCOUNT_LIMIT
f12e568c	30
f12e568c WD	31
	32	#define CONFIG_BOARD_TYPES 1 /* support board types */
	33
	34	#define CONFIG_PREBOOT "echo;" \
32bf3d14	35	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
f12e568c WD	36	"echo"
	37
	38	#undef CONFIG_BOOTARGS
	39
	40	#define CONFIG_EXTRA_ENV_SETTINGS \
	41	"netdev=eth0\0" \
	42	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	43	"nfsroot=${serverip}:${rootpath}\0" \
f12e568c	44	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	45	"addip=setenv bootargs ${bootargs} " \
	46	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	47	":${hostname}:${netdev}:off panic=1\0" \
f12e568c	48	"flash_nfs=run nfsargs addip;" \
fe126d8b	49	"bootm ${kernel_addr}\0" \
f12e568c	50	"flash_self=run ramargs addip;" \
fe126d8b WD	51	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	52	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
f12e568c	53	"rootpath=/opt/eldk/ppc_8xx\0" \
29f8f58f WD	54	"hostname=TQM855M\0" \
29f8f58f WD	55	"bootfile=TQM855M/uImage\0" \
eb6da805 WD	56	"fdt_addr=40080000\0" \
	57	"kernel_addr=400A0000\0" \
	58	"ramdisk_addr=40280000\0" \
29f8f58f WD	59	"u-boot=TQM855M/u-image.bin\0" \
	60	"load=tftp 200000 ${u-boot}\0" \
	61	"update=prot off 40000000 +${filesize};" \
	62	"era 40000000 +${filesize};" \
	63	"cp.b 200000 40000000 ${filesize};" \
	64	"sete filesize;save\0" \
f12e568c WD	65	""
	66	#define CONFIG_BOOTCOMMAND "run flash_self"
	67
	68	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	69	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
f12e568c WD	70
	71	#undef CONFIG_WATCHDOG /* watchdog disabled */
	72
f12e568c WD	73	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
f12e568c WD	74
d4ca31c4	75	/* enable I2C and select the hardware/software driver */
ea818dbb HS	76	#define CONFIG_SYS_I2C
	77	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	78	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	79	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
d4ca31c4 WD	80	/*
	81	* Software (bit-bang) I2C driver configuration
	82	*/
	83	#define PB_SCL 0x00000020 /* PB 26 */
	84	#define PB_SDA 0x00000010 /* PB 27 */
	85
	86	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	87	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	88	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	89	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	90	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	91	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	92	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	93	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	94	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
d4ca31c4	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
6d0f6bcf JCPV	97	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
d4ca31c4	98	#if 0
6d0f6bcf JCPV	99	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
	100	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
	101	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
d4ca31c4 WD	102	#endif
d4ca31c4 WD	103
37d4bb70 JL	104	/*
	105	* BOOTP options
	106	*/
	107	#define CONFIG_BOOTP_SUBNETMASK
	108	#define CONFIG_BOOTP_GATEWAY
	109	#define CONFIG_BOOTP_HOSTNAME
	110	#define CONFIG_BOOTP_BOOTPATH
	111	#define CONFIG_BOOTP_BOOTFILESIZE
	112
f12e568c WD	113	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
f12e568c WD	114
2694690e JL	115	/*
	116	* Command line configuration.
	117	*/
2694690e JL	118	#define CONFIG_CMD_EEPROM
2694690e JL	119	#define CONFIG_CMD_IDE
29f8f58f	120	#define CONFIG_CMD_JFFS2
f12e568c	121
29f8f58f WD	122	#define CONFIG_NETCONSOLE
29f8f58f WD	123
f12e568c WD	124	/*
	125	* Miscellaneous configurable options
	126	*/
6d0f6bcf	127	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f12e568c	128
2751a95a	129	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
f12e568c	130
2694690e	131	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	132	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
f12e568c	133	#else
6d0f6bcf	134	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
f12e568c	135	#endif
6d0f6bcf JCPV	136	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	137	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	138	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
f12e568c	139
6d0f6bcf JCPV	140	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	141	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
f12e568c	142
6d0f6bcf	143	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
f12e568c	144
f12e568c WD	145	/*
	146	* Low Level Configuration Settings
	147	* (address mappings, register initial values, etc.)
	148	* You should know what you are doing if you make changes here.
	149	*/
	150	/*-----------------------------------------------------------------------
	151	* Internal Memory Mapped Register
	152	*/
6d0f6bcf	153	#define CONFIG_SYS_IMMR 0xFFF00000
f12e568c WD	154
	155	/*-----------------------------------------------------------------------
	156	* Definitions for initial stack pointer and data area (in DPRAM)
	157	*/
6d0f6bcf	158	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	159	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	160	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	161	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
f12e568c WD	162
	163	/*-----------------------------------------------------------------------
	164	* Start addresses for the final memory configuration
	165	* (Set up by the startup code)
6d0f6bcf	166	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
f12e568c	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	169	#define CONFIG_SYS_FLASH_BASE 0x40000000
	170	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	171	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	172	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
f12e568c WD	173
	174	/*
	175	* For booting Linux, the board info and command line data
	176	* have to be in the first 8 MB of memory, since this is
	177	* the maximum mapped by the Linux kernel during initialization.
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
f12e568c WD	180
	181	/*-----------------------------------------------------------------------
	182	* FLASH organization
	183	*/
f12e568c	184
e318d9e9	185	/* use CFI flash driver */
6d0f6bcf	186	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	187	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	189	#define CONFIG_SYS_FLASH_EMPTY_INFO
	190	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	191	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	192	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
f12e568c	193
5a1aceb0	194	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	195	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	196	#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
	197	#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
f12e568c WD	198
f12e568c WD	199	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	200	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	201	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
f12e568c	202
6d0f6bcf	203	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
67c31036	204
7c803be2 WD	205	#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
7c803be2 WD	206
29f8f58f WD	207	/*-----------------------------------------------------------------------
	208	* Dynamic MTD partition support
	209	*/
68d7d651	210	#define CONFIG_CMD_MTDPARTS
942556a9 SR	211	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	212	#define CONFIG_FLASH_CFI_MTD
29f8f58f WD	213	#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
	214
	215	#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
	216	"128k(dtb)," \
	217	"1920k(kernel)," \
	218	"5632(rootfs)," \
cd82919e	219	"4m(data)"
29f8f58f	220
f12e568c WD	221	/*-----------------------------------------------------------------------
	222	* Hardware Information Block
	223	*/
6d0f6bcf JCPV	224	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	225	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	226	#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
f12e568c WD	227
	228	/*-----------------------------------------------------------------------
	229	* Cache Configuration
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
2694690e	232	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	233	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
f12e568c WD	234	#endif
	235
	236	/*-----------------------------------------------------------------------
	237	* SYPCR - System Protection Control 11-9
	238	* SYPCR can only be written once after reset!
	239	*-----------------------------------------------------------------------
	240	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	241	*/
	242	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	243	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
f12e568c WD	244	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
f12e568c WD	245	#else
6d0f6bcf	246	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
f12e568c WD	247	#endif
	248
	249	/*-----------------------------------------------------------------------
	250	* SIUMCR - SIU Module Configuration 11-6
	251	*-----------------------------------------------------------------------
	252	* PCMCIA config., multi-function pin tri-state
	253	*/
	254	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	255	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
f12e568c	256	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	257	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
f12e568c WD	258	#endif /* CONFIG_CAN_DRIVER */
	259
	260	/*-----------------------------------------------------------------------
	261	* TBSCR - Time Base Status and Control 11-26
	262	*-----------------------------------------------------------------------
	263	* Clear Reference Interrupt Status, Timebase freezing enabled
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
f12e568c WD	266
	267	/*-----------------------------------------------------------------------
	268	* RTCSC - Real-Time Clock Status and Control Register 11-27
	269	*-----------------------------------------------------------------------
	270	*/
6d0f6bcf	271	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
f12e568c WD	272
	273	/*-----------------------------------------------------------------------
	274	* PISCR - Periodic Interrupt Status and Control 11-31
	275	*-----------------------------------------------------------------------
	276	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	277	*/
6d0f6bcf	278	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
f12e568c WD	279
	280	/*-----------------------------------------------------------------------
	281	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	282	*-----------------------------------------------------------------------
	283	* Reset PLL lock status sticky bit, timer expired status bit and timer
	284	* interrupt status bit
f12e568c	285	*/
6d0f6bcf	286	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
f12e568c WD	287
	288	/*-----------------------------------------------------------------------
	289	* SCCR - System Clock and reset Control Register 15-27
	290	*-----------------------------------------------------------------------
	291	* Set clock output, timebase and RTC source and divider,
	292	* power management and some other internal clocks
	293	*/
	294	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	295	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
f12e568c WD	296	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
f12e568c WD	297	SCCR_DFALCD00)
f12e568c WD	298
	299	/*-----------------------------------------------------------------------
	300	* PCMCIA stuff
	301	*-----------------------------------------------------------------------
	302	*
	303	*/
6d0f6bcf JCPV	304	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	305	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	306	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	307	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	308	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	309	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	310	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	311	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
f12e568c WD	312
	313	/*-----------------------------------------------------------------------
	314	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	315	*-----------------------------------------------------------------------
	316	*/
	317
8d1165e1	318	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
f12e568c WD	319	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	320
	321	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	322	#undef CONFIG_IDE_LED /* LED for ide not supported */
	323	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	324
6d0f6bcf JCPV	325	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	326	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
f12e568c	327
6d0f6bcf	328	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
f12e568c	329
6d0f6bcf	330	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
f12e568c WD	331
f12e568c WD	332	/* Offset for data I/O */
6d0f6bcf	333	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f12e568c WD	334
f12e568c WD	335	/* Offset for normal register accesses */
6d0f6bcf	336	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
f12e568c WD	337
f12e568c WD	338	/* Offset for alternate registers */
6d0f6bcf	339	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
f12e568c WD	340
	341	/*-----------------------------------------------------------------------
	342	*
	343	*-----------------------------------------------------------------------
	344	*
	345	*/
6d0f6bcf	346	#define CONFIG_SYS_DER 0
f12e568c WD	347
	348	/*
	349	* Init Memory Controller:
	350	*
	351	* BR0/1 and OR0/1 (FLASH)
	352	*/
	353
	354	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	355	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	356
	357	/* used to re-map FLASH both when starting from SRAM or FLASH:
	358	* restrict access enough to keep SRAM working (if any)
	359	* but not too much to meddle with FLASH accesses
	360	*/
6d0f6bcf JCPV	361	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	362	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
f12e568c WD	363
	364	/*
	365	* FLASH timing:
	366	*/
6d0f6bcf	367	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
f12e568c	368	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
f12e568c	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	371	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	372	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
f12e568c	373
6d0f6bcf JCPV	374	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	375	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	376	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
f12e568c WD	377
	378	/*
	379	* BR2/3 and OR2/3 (SDRAM)
	380	*
	381	*/
	382	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	383	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	384	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	385
	386	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	387	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
f12e568c	388
6d0f6bcf JCPV	389	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	390	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
f12e568c WD	391
f12e568c WD	392	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	393	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	394	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
f12e568c	395	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	396	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	397	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	398	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	399	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
f12e568c WD	400	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	401	#endif /* CONFIG_CAN_DRIVER */
	402
	403	/*
	404	* Memory Periodic Timer Prescaler
	405	*
	406	* The Divider for PTA (refresh timer) configuration is based on an
	407	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	408	* the number of chip selects (NCS) and the actually needed refresh
	409	* rate is done by setting MPTPR.
	410	*
	411	* PTA is calculated from
	412	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	413	*
	414	* gclk CPU clock (not bus clock!)
	415	* Trefresh Refresh cycle * 4 (four word bursts used)
	416	*
	417	* 4096 Rows from SDRAM example configuration
	418	* 1000 factor s -> ms
	419	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	420	* 4 Number of refresh cycles per period
	421	* 64 Refresh cycle in ms per number of rows
	422	* --------------------------------------------
	423	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	424	*
	425	* 50 MHz => 50.000.000 / Divider = 98
	426	* 66 Mhz => 66.000.000 / Divider = 129
	427	* 80 Mhz => 80.000.000 / Divider = 156
	428	*/
e9132ea9	429
6d0f6bcf JCPV	430	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
6d0f6bcf JCPV	431	#define CONFIG_SYS_MAMR_PTA 98
f12e568c WD	432
	433	/*
	434	* For 16 MBit, refresh rates could be 31.3 us
	435	* (= 64 ms / 2K = 125 / quad bursts).
	436	* For a simpler initialization, 15.6 us is used instead.
	437	*
6d0f6bcf JCPV	438	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	439	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
f12e568c	440	*/
6d0f6bcf JCPV	441	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	442	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
f12e568c WD	443
f12e568c WD	444	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	445	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	446	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
f12e568c WD	447
	448	/*
	449	* MAMR settings for SDRAM
	450	*/
	451
	452	/* 8 column SDRAM */
6d0f6bcf	453	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f12e568c WD	454	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	455	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	456	/* 9 column SDRAM */
6d0f6bcf	457	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
f12e568c WD	458	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	459	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	460
f12e568c WD	461	#define CONFIG_SCC1_ENET
f12e568c WD	462	#define CONFIG_FEC_ENET
48690d80	463	#define CONFIG_ETHPRIME "SCC"
f12e568c	464
7026ead0 HS	465	#define CONFIG_HWCONFIG 1
7026ead0 HS	466
f12e568c	467	#endif /* __CONFIG_H */