[people/ms/u-boot.git] / include / configs / TQM862L.h

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1
#define CONFIG_MPC860T		1
#define CONFIG_MPC862		1

#define CONFIG_TQM862L		1	/* ...on a TQM8xxL module	*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define	CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_8xx\0"					\
	"bootfile=/tftpboot/TQM862L/uImage\0"				\
	"kernel_addr=40040000\0"					\
	"ramdisk_addr=40100000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_IDE	| \
				CFG_CMD_DATE	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#if 0
#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1

#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz or 100 MHz CPU,
 * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
 */
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
#define CFG_PLPRCR							\
		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#else			/* up to 66 MHz we use a 1:1 clock */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#endif	/* CONFIG_80MHz | CONFIG_100MHz */

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
#define CFG_SCCR	(/* SCCR_TBS  | */ \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#else			/* up to 66 MHz we use a 1:1 clock */
#define CFG_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#endif	/* CONFIG_80MHz | CONFIG_100MHz */

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#if defined(CONFIG_100MHz)
/* 100 MHz CPU - 50 MHz bus:
 * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV4  | OR_SCY_7_CLK | OR_BI)
#elif defined(CONFIG_80MHz)
/* 80 MHz CPU - 40 MHz bus:
 * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
#elif defined(CONFIG_66MHz)
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
#else		/*   50 MHz */
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
#endif	/*CONFIG_??MHz */

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 *  50 MHz =>  50.000.000 / Divider =  98
 *  66 Mhz =>  66.000.000 / Divider = 129
 *  80 Mhz =>  80.000.000 / Divider = 156
 * 100 Mhz => 100.000.000 / Divider = 195
 */
#if   defined(CONFIG_100MHz)
#define CFG_MAMR_PTA		195
#elif defined(CONFIG_80MHz)
#define CFG_MAMR_PTA		156
#elif defined(CONFIG_66MHz)
#define CFG_MAMR_PTA		129
#else		/*   50 MHz */
#define CFG_MAMR_PTA		 98
#endif	/*CONFIG_??MHz */

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_NET_MULTI
#define CONFIG_SCC1_ENET
#define CONFIG_FEC_ENET
#define CONFIG_ETHPRIME		"SCC ETHERNET"

#endif	/* __CONFIG_H */
Commit	Line	Data
d126bfbd	1	/*
f12e568c	2	* (C) Copyright 2000-2003
d126bfbd WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1
	37	#define CONFIG_MPC860T 1
	38	#define CONFIG_MPC862 1
	39
	40	#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
	41
	42	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	43	#undef CONFIG_8xx_CONS_SMC2
	44	#undef CONFIG_8xx_CONS_NONE
	45
	46	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	47
ae3af05e	48	#define CONFIG_BOOTCOUNT_LIMIT
d126bfbd	49
ae3af05e	50	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
d126bfbd WD	51
	52	#define CONFIG_BOARD_TYPES 1 /* support board types */
	53
	54	#define CONFIG_PREBOOT "echo;" \
	55	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	56	"echo"
	57
	58	#undef CONFIG_BOOTARGS
	59
	60	#define CONFIG_EXTRA_ENV_SETTINGS \
ae3af05e	61	"netdev=eth0\0" \
d126bfbd WD	62	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	63	"nfsroot=$(serverip):$(rootpath)\0" \
	64	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	65	"addip=setenv bootargs $(bootargs) " \
	66	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	67	":$(hostname):$(netdev):off panic=1\0" \
	68	"flash_nfs=run nfsargs addip;" \
	69	"bootm $(kernel_addr)\0" \
	70	"flash_self=run ramargs addip;" \
	71	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	72	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	73	"rootpath=/opt/eldk/ppc_8xx\0" \
5e4be00f	74	"bootfile=/tftpboot/TQM862L/uImage\0" \
d126bfbd WD	75	"kernel_addr=40040000\0" \
	76	"ramdisk_addr=40100000\0" \
	77	""
	78	#define CONFIG_BOOTCOMMAND "run flash_self"
	79
	80	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	81	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	82
	83	#undef CONFIG_WATCHDOG /* watchdog disabled */
	84
	85	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	86
	87	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	88
	89	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
	90
	91	#define CONFIG_MAC_PARTITION
	92	#define CONFIG_DOS_PARTITION
	93
	94	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	95
	96	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	97	CFG_CMD_ASKENV \| \
	98	CFG_CMD_DHCP \| \
	99	CFG_CMD_IDE \| \
	100	CFG_CMD_DATE )
	101
	102	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	103	#include <cmd_confdefs.h>
	104
	105	/*
	106	* Miscellaneous configurable options
	107	*/
	108	#define CFG_LONGHELP /* undef to save memory */
	109	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	110
	111	#if 0
	112	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
	113	#endif
	114	#ifdef CFG_HUSH_PARSER
	115	#define CFG_PROMPT_HUSH_PS2 "> "
	116	#endif
	117
	118	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	119	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	120	#else
	121	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	122	#endif
	123	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	124	#define CFG_MAXARGS 16 /* max number of command args */
	125	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	126
	127	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	128	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	129
	130	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	131
	132	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	133
	134	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	135
	136	/*
	137	* Low Level Configuration Settings
	138	* (address mappings, register initial values, etc.)
139	* You should know what you are doing if you make changes here.
140	*/
141	/*-----------------------------------------------------------------------
142	* Internal Memory Mapped Register
143	*/
144	#define CFG_IMMR 0xFFF00000
145
146	/*-----------------------------------------------------------------------
147	* Definitions for initial stack pointer and data area (in DPRAM)
148	*/
149	#define CFG_INIT_RAM_ADDR CFG_IMMR
150	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
151	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
152	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
153	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
154
155	/*-----------------------------------------------------------------------
156	* Start addresses for the final memory configuration
157	* (Set up by the startup code)
158	* Please note that CFG_SDRAM_BASE _must_ start at 0
159	*/
160	#define CFG_SDRAM_BASE 0x00000000
161	#define CFG_FLASH_BASE 0x40000000
162	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
163	#define CFG_MONITOR_BASE CFG_FLASH_BASE
164	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
165
166	/*
167	* For booting Linux, the board info and command line data
168	* have to be in the first 8 MB of memory, since this is
169	* the maximum mapped by the Linux kernel during initialization.
170	*/
171	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
172
173	/*-----------------------------------------------------------------------
174	* FLASH organization
175	*/
176	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
177	#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
178
179	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
180	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
181
182	#define CFG_ENV_IS_IN_FLASH 1
71f95118	183
d126bfbd WD	184	#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
	185	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	186
	187	/* Address and size of Redundant Environment Sector */
	188	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
	189	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	190
	191	/*-----------------------------------------------------------------------
	192	* Hardware Information Block
	193	*/
	194	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	195	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	196	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
	197
	198	/*-----------------------------------------------------------------------
	199	* Cache Configuration
	200	*/
	201	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
	202	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	203	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	204	#endif
	205
	206	/*-----------------------------------------------------------------------
	207	* SYPCR - System Protection Control 11-9
	208	* SYPCR can only be written once after reset!
	209	*-----------------------------------------------------------------------
	210	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	211	*/
	212	#if defined(CONFIG_WATCHDOG)
	213	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	214	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	215	#else
	216	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	217	#endif
	218
	219	/*-----------------------------------------------------------------------
	220	* SIUMCR - SIU Module Configuration 11-6
	221	*-----------------------------------------------------------------------
	222	* PCMCIA config., multi-function pin tri-state
	223	*/
	224	#ifndef CONFIG_CAN_DRIVER
	225	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	226	#else /* we must activate GPL5 in the SIUMCR for CAN */
	227	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	228	#endif /* CONFIG_CAN_DRIVER */
	229
	230	/*-----------------------------------------------------------------------
	231	* TBSCR - Time Base Status and Control 11-26
	232	*-----------------------------------------------------------------------
	233	* Clear Reference Interrupt Status, Timebase freezing enabled
	234	*/
	235	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	236
	237	/*-----------------------------------------------------------------------
	238	* RTCSC - Real-Time Clock Status and Control Register 11-27
	239	*-----------------------------------------------------------------------
	240	*/
	241	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	242
	243	/*-----------------------------------------------------------------------
	244	* PISCR - Periodic Interrupt Status and Control 11-31
	245	*-----------------------------------------------------------------------
	246	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	247	*/
248	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
249
250	/*-----------------------------------------------------------------------
251	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
252	*-----------------------------------------------------------------------
253	* Reset PLL lock status sticky bit, timer expired status bit and timer
254	* interrupt status bit
255	*
73a8b27c WD	256	* If this is a 80 MHz or 100 MHz CPU,
73a8b27c WD	257	* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
d126bfbd	258	*/
73a8b27c	259	#if defined(CONFIG_80MHz) \|\| defined(CONFIG_100MHz)
d126bfbd WD	260	#define CFG_PLPRCR \
d126bfbd WD	261	( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
f12e568c	262	#else /* up to 66 MHz we use a 1:1 clock */
d126bfbd	263	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
73a8b27c	264	#endif /* CONFIG_80MHz \| CONFIG_100MHz */
d126bfbd WD	265
	266	/*-----------------------------------------------------------------------
	267	* SCCR - System Clock and reset Control Register 15-27
	268	*-----------------------------------------------------------------------
	269	* Set clock output, timebase and RTC source and divider,
	270	* power management and some other internal clocks
	271	*/
	272	#define SCCR_MASK SCCR_EBDF11
73a8b27c	273	#if defined(CONFIG_80MHz) \|\| defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
d126bfbd WD	274	#define CFG_SCCR (/* SCCR_TBS \| */ \
	275	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	276	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	277	SCCR_DFALCD00)
f12e568c	278	#else /* up to 66 MHz we use a 1:1 clock */
d126bfbd WD	279	#define CFG_SCCR (SCCR_TBS \| \
	280	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	281	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	282	SCCR_DFALCD00)
73a8b27c	283	#endif /* CONFIG_80MHz \| CONFIG_100MHz */
d126bfbd WD	284
	285	/*-----------------------------------------------------------------------
	286	* PCMCIA stuff
	287	*-----------------------------------------------------------------------
	288	*
	289	*/
	290	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	291	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	292	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	293	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	294	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	295	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	296	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	297	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	298
	299	/*-----------------------------------------------------------------------
	300	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	301	*-----------------------------------------------------------------------
	302	*/
	303
	304	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	305
	306	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	307	#undef CONFIG_IDE_LED /* LED for ide not supported */
	308	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	309
	310	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	311	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	312
	313	#define CFG_ATA_IDE0_OFFSET 0x0000
	314
	315	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	316
	317	/* Offset for data I/O */
	318	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	319
	320	/* Offset for normal register accesses */
	321	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	322
	323	/* Offset for alternate registers */
	324	#define CFG_ATA_ALT_OFFSET 0x0100
	325
	326	/*-----------------------------------------------------------------------
	327	*
	328	*-----------------------------------------------------------------------
	329	*
	330	*/
d126bfbd WD	331	#define CFG_DER 0
	332
	333	/*
	334	* Init Memory Controller:
	335	*
	336	* BR0/1 and OR0/1 (FLASH)
	337	*/
	338
	339	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
71f95118	340	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
d126bfbd WD	341
	342	/* used to re-map FLASH both when starting from SRAM or FLASH:
	343	* restrict access enough to keep SRAM working (if any)
	344	* but not too much to meddle with FLASH accesses
	345	*/
	346	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	347	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	348
	349	/*
	350	* FLASH timing:
	351	*/
73a8b27c WD	352	#if defined(CONFIG_100MHz)
73a8b27c WD	353	/* 100 MHz CPU - 50 MHz bus:
71f95118 WD	354	* ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
71f95118 WD	355	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 \| OR_SCY_7_CLK \| OR_BI)
73a8b27c WD	356	#elif defined(CONFIG_80MHz)
	357	/* 80 MHz CPU - 40 MHz bus:
	358	* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
d126bfbd WD	359	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| 0 \| OR_CSNT_SAM \| \
	360	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
	361	#elif defined(CONFIG_66MHz)
	362	/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
	363	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
	364	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
	365	#else /* 50 MHz */
	366	/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
	367	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
	368	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
	369	#endif /CONFIG_??MHz /
	370
	371	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	372	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	373	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
	374
	375	#define CFG_OR1_REMAP CFG_OR0_REMAP
	376	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
	377	#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
	378
	379	/*
	380	* BR2/3 and OR2/3 (SDRAM)
	381	*
	382	*/
	383	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	384	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	385	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	386
	387	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	388	#define CFG_OR_TIMING_SDRAM 0x00000A00
	389
	390	#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	391	#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	392
	393	#ifndef CONFIG_CAN_DRIVER
	394	#define CFG_OR3_PRELIM CFG_OR2_PRELIM
	395	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	396	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
	397	#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	398	#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	399	#define CFG_OR3_CAN (CFG_CAN_OR_AM \| OR_G5LA \| OR_BI)
	400	#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) \| \
	401	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	402	#endif /* CONFIG_CAN_DRIVER */
	403
	404	/*
	405	* Memory Periodic Timer Prescaler
	406	*
	407	* The Divider for PTA (refresh timer) configuration is based on an
	408	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	409	* the number of chip selects (NCS) and the actually needed refresh
	410	* rate is done by setting MPTPR.
	411	*
	412	* PTA is calculated from
	413	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	414	*
	415	* gclk CPU clock (not bus clock!)
	416	* Trefresh Refresh cycle * 4 (four word bursts used)
	417	*
	418	* 4096 Rows from SDRAM example configuration
	419	* 1000 factor s -> ms
	420	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	421	* 4 Number of refresh cycles per period
	422	* 64 Refresh cycle in ms per number of rows
423	* --------------------------------------------
424	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
425	*
73a8b27c WD	426	* 50 MHz => 50.000.000 / Divider = 98
	427	* 66 Mhz => 66.000.000 / Divider = 129
	428	* 80 Mhz => 80.000.000 / Divider = 156
	429	* 100 Mhz => 100.000.000 / Divider = 195
d126bfbd	430	*/
73a8b27c WD	431	#if defined(CONFIG_100MHz)
	432	#define CFG_MAMR_PTA 195
	433	#elif defined(CONFIG_80MHz)
d126bfbd WD	434	#define CFG_MAMR_PTA 156
	435	#elif defined(CONFIG_66MHz)
	436	#define CFG_MAMR_PTA 129
	437	#else /* 50 MHz */
	438	#define CFG_MAMR_PTA 98
	439	#endif /CONFIG_??MHz /
	440
	441	/*
	442	* For 16 MBit, refresh rates could be 31.3 us
	443	* (= 64 ms / 2K = 125 / quad bursts).
	444	* For a simpler initialization, 15.6 us is used instead.
	445	*
	446	* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
	447	* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
	448	*/
	449	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	450	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	451
	452	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	453	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	454	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	455
	456	/*
	457	* MAMR settings for SDRAM
	458	*/
	459
	460	/* 8 column SDRAM */
	461	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	462	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	463	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	464	/* 9 column SDRAM */
	465	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	466	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	467	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	468
	469
	470	/*
	471	* Internal Definitions
	472	*
	473	* Boot Flags
	474	*/
	475	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	476	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	477
	478	#define CONFIG_NET_MULTI
	479	#define CONFIG_SCC1_ENET
	480	#define CONFIG_FEC_ENET
	481	#define CONFIG_ETHPRIME "SCC ETHERNET"
	482
	483	#endif /* __CONFIG_H */