projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 71f95118 | 1 | /* |
| f12e568c | 2 | * (C) Copyright 2000-2003 |
| 71f95118 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC860 1 | |
| 37 | #define CONFIG_MPC860T 1 | |
| 38 | #define CONFIG_MPC862 1 | |
| 39 | ||
| 40 | #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ | |
| 41 | ||
| 42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
| 43 | #undef CONFIG_8xx_CONS_SMC2 | |
| 44 | #undef CONFIG_8xx_CONS_NONE | |
| 45 | ||
| 46 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
| 47 | ||
| ae3af05e | 48 | #define CONFIG_BOOTCOUNT_LIMIT |
| 71f95118 | 49 | |
| ae3af05e | 50 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 71f95118 WD |
51 | |
| 52 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
| 53 | ||
| 54 | #define CONFIG_PREBOOT "echo;" \ | |
| 55 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
| 56 | "echo" | |
| 57 | ||
| 58 | #undef CONFIG_BOOTARGS | |
| 59 | ||
| 60 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 61 | "netdev=eth0\0" \ | |
| 62 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 63 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
| 64 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 65 | "addip=setenv bootargs $(bootargs) " \ | |
| 66 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
| 67 | ":$(hostname):$(netdev):off panic=1\0" \ | |
| 68 | "flash_nfs=run nfsargs addip;" \ | |
| 69 | "bootm $(kernel_addr)\0" \ | |
| 70 | "flash_self=run ramargs addip;" \ | |
| 71 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
| 72 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
| 73 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
| 74 | "bootfile=/tftpboot/TQM862M/uImage\0" \ | |
| 75 | "kernel_addr=40080000\0" \ | |
| 76 | "ramdisk_addr=40180000\0" \ | |
| 77 | "" | |
| 78 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 79 | ||
| 80 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 81 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| 82 | ||
| 83 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 84 | ||
| 85 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
| 86 | ||
| 87 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 88 | ||
| 89 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) | |
| 90 | ||
| 91 | #define CONFIG_MAC_PARTITION | |
| 92 | #define CONFIG_DOS_PARTITION | |
| 93 | ||
| 94 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| 95 | ||
| 96 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
| 97 | CFG_CMD_ASKENV | \ | |
| 98 | CFG_CMD_DHCP | \ | |
| 99 | CFG_CMD_IDE | \ | |
| 100 | CFG_CMD_DATE ) | |
| 101 | ||
| 102 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 103 | #include <cmd_confdefs.h> | |
| 104 | ||
| 105 | /* | |
| 106 | * Miscellaneous configurable options | |
| 107 | */ | |
| 108 | #define CFG_LONGHELP /* undef to save memory */ | |
| 109 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 110 | ||
| 111 | #if 0 | |
| 112 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ | |
| 113 | #endif | |
| 114 | #ifdef CFG_HUSH_PARSER | |
| 115 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 116 | #endif | |
| 117 | ||
| 118 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 119 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 120 | #else | |
| 121 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 122 | #endif | |
| 123 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 124 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 125 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 126 | ||
| 127 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 128 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 129 | ||
| 130 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 131 | ||
| 132 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 133 | ||
| 134 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 135 | ||
| 136 | /* | |
| 137 | * Low Level Configuration Settings | |
| 138 | * (address mappings, register initial values, etc.) | |
| 139 | * You should know what you are doing if you make changes here. | |
| 140 | */ | |
| 141 | /*----------------------------------------------------------------------- | |
| 142 | * Internal Memory Mapped Register | |
| 143 | */ | |
| 144 | #define CFG_IMMR 0xFFF00000 | |
| 145 | ||
| 146 | /*----------------------------------------------------------------------- | |
| 147 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 148 | */ | |
| 149 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 150 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
| 151 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
| 152 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 153 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 154 | ||
| 155 | /*----------------------------------------------------------------------- | |
| 156 | * Start addresses for the final memory configuration | |
| 157 | * (Set up by the startup code) | |
| 158 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 159 | */ | |
| 160 | #define CFG_SDRAM_BASE 0x00000000 | |
| 161 | #define CFG_FLASH_BASE 0x40000000 | |
| 162 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 163 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
| 164 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 165 | ||
| 166 | /* | |
| 167 | * For booting Linux, the board info and command line data | |
| 168 | * have to be in the first 8 MB of memory, since this is | |
| 169 | * the maximum mapped by the Linux kernel during initialization. | |
| 170 | */ | |
| 171 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 172 | ||
| 173 | /*----------------------------------------------------------------------- | |
| 174 | * FLASH organization | |
| 175 | */ | |
| 176 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 177 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
| 178 | ||
| 179 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
| 180 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 181 | ||
| 182 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 183 | ||
| 184 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
| 185 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
| 186 | #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ | |
| 187 | ||
| 188 | /* Address and size of Redundant Environment Sector */ | |
| 189 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) | |
| 190 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
| 191 | ||
| 192 | /*----------------------------------------------------------------------- | |
| 193 | * Hardware Information Block | |
| 194 | */ | |
| 195 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
| 196 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
| 197 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
| 198 | ||
| 199 | /*----------------------------------------------------------------------- | |
| 200 | * Cache Configuration | |
| 201 | */ | |
| 202 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
| 203 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 204 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
| 205 | #endif | |
| 206 | ||
| 207 | /*----------------------------------------------------------------------- | |
| 208 | * SYPCR - System Protection Control 11-9 | |
| 209 | * SYPCR can only be written once after reset! | |
| 210 | *----------------------------------------------------------------------- | |
| 211 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 212 | */ | |
| 213 | #if defined(CONFIG_WATCHDOG) | |
| 214 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
| 215 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
| 216 | #else | |
| 217 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
| 218 | #endif | |
| 219 | ||
| 220 | /*----------------------------------------------------------------------- | |
| 221 | * SIUMCR - SIU Module Configuration 11-6 | |
| 222 | *----------------------------------------------------------------------- | |
| 223 | * PCMCIA config., multi-function pin tri-state | |
| 224 | */ | |
| 225 | #ifndef CONFIG_CAN_DRIVER | |
| 226 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
| 227 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
| 228 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
| 229 | #endif /* CONFIG_CAN_DRIVER */ | |
| 230 | ||
| 231 | /*----------------------------------------------------------------------- | |
| 232 | * TBSCR - Time Base Status and Control 11-26 | |
| 233 | *----------------------------------------------------------------------- | |
| 234 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 235 | */ | |
| 236 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
| 237 | ||
| 238 | /*----------------------------------------------------------------------- | |
| 239 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 240 | *----------------------------------------------------------------------- | |
| 241 | */ | |
| 242 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
| 243 | ||
| 244 | /*----------------------------------------------------------------------- | |
| 245 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 246 | *----------------------------------------------------------------------- | |
| 247 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 248 | */ | |
| 249 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
| 250 | ||
| 251 | /*----------------------------------------------------------------------- | |
| 252 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 253 | *----------------------------------------------------------------------- | |
| 254 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 255 | * interrupt status bit | |
| 256 | * | |
| 257 | * If this is a 80 MHz or 100 MHz CPU, | |
| 258 | * set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100) | |
| 259 | */ | |
| 260 | #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) | |
| 261 | #define CFG_PLPRCR \ | |
| 262 | ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) | |
| f12e568c | 263 | #else /* up to 66 MHz we use a 1:1 clock */ |
| 71f95118 WD |
264 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
| 265 | #endif /* CONFIG_80MHz | CONFIG_100MHz */ | |
| 266 | ||
| 267 | /*----------------------------------------------------------------------- | |
| 268 | * SCCR - System Clock and reset Control Register 15-27 | |
| 269 | *----------------------------------------------------------------------- | |
| 270 | * Set clock output, timebase and RTC source and divider, | |
| 271 | * power management and some other internal clocks | |
| 272 | */ | |
| 273 | #define SCCR_MASK SCCR_EBDF11 | |
| 274 | #if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */ | |
| 275 | #define CFG_SCCR (/* SCCR_TBS | */ \ | |
| 276 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
| 277 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
| 278 | SCCR_DFALCD00) | |
| f12e568c | 279 | #else /* up to 66 MHz we use a 1:1 clock */ |
| 71f95118 WD |
280 | #define CFG_SCCR (SCCR_TBS | \ |
| 281 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
| 282 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
| 283 | SCCR_DFALCD00) | |
| 284 | #endif /* CONFIG_80MHz | CONFIG_100MHz */ | |
| 285 | ||
| 286 | /*----------------------------------------------------------------------- | |
| 287 | * PCMCIA stuff | |
| 288 | *----------------------------------------------------------------------- | |
| 289 | * | |
| 290 | */ | |
| 291 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
| 292 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 293 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
| 294 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 295 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| 296 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 297 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
| 298 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| 299 | ||
| 300 | /*----------------------------------------------------------------------- | |
| 301 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 302 | *----------------------------------------------------------------------- | |
| 303 | */ | |
| 304 | ||
| 305 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| 306 | ||
| 307 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 308 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 309 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| 310 | ||
| 311 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
| 312 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| 313 | ||
| 314 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
| 315 | ||
| 316 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
| 317 | ||
| 318 | /* Offset for data I/O */ | |
| 319 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
| 320 | ||
| 321 | /* Offset for normal register accesses */ | |
| 322 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
| 323 | ||
| 324 | /* Offset for alternate registers */ | |
| 325 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
| 326 | ||
| 327 | /*----------------------------------------------------------------------- | |
| 328 | * | |
| 329 | *----------------------------------------------------------------------- | |
| 330 | * | |
| 331 | */ | |
| 332 | #define CFG_DER 0 | |
| 333 | ||
| 334 | /* | |
| 335 | * Init Memory Controller: | |
| 336 | * | |
| 337 | * BR0/1 and OR0/1 (FLASH) | |
| 338 | */ | |
| 339 | ||
| 340 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 341 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ | |
| 342 | ||
| 343 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 344 | * restrict access enough to keep SRAM working (if any) | |
| 345 | * but not too much to meddle with FLASH accesses | |
| 346 | */ | |
| 347 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
| 348 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| 349 | ||
| 350 | /* | |
| 351 | * FLASH timing: | |
| 352 | */ | |
| 353 | #if defined(CONFIG_100MHz) | |
| 354 | /* 100 MHz CPU - 50 MHz bus: | |
| 355 | * ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */ | |
| 356 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI) | |
| 357 | #elif defined(CONFIG_80MHz) | |
| 358 | /* 80 MHz CPU - 40 MHz bus: | |
| 359 | * ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ | |
| 360 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ | |
| 361 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
| 362 | #elif defined(CONFIG_66MHz) | |
| 363 | /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ | |
| 364 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
| 365 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
| 366 | #else /* 50 MHz */ | |
| 367 | /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ | |
| 368 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
| 369 | OR_SCY_2_CLK | OR_EHTR | OR_BI) | |
| 370 | #endif /*CONFIG_??MHz */ | |
| 371 | ||
| 372 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
| 373 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
| 374 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
| 375 | ||
| 376 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
| 377 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
| 378 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
| 379 | ||
| 380 | /* | |
| 381 | * BR2/3 and OR2/3 (SDRAM) | |
| 382 | * | |
| 383 | */ | |
| 384 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 385 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
| 386 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
| 387 | ||
| 388 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 389 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
| 390 | ||
| 391 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
| 392 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| 393 | ||
| 394 | #ifndef CONFIG_CAN_DRIVER | |
| 395 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
| 396 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
| 397 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
| 398 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
| 399 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
| 400 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
| 401 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
| 402 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
| 403 | #endif /* CONFIG_CAN_DRIVER */ | |
| 404 | ||
| 405 | /* | |
| 406 | * Memory Periodic Timer Prescaler | |
| 407 | * | |
| 408 | * The Divider for PTA (refresh timer) configuration is based on an | |
| 409 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| 410 | * the number of chip selects (NCS) and the actually needed refresh | |
| 411 | * rate is done by setting MPTPR. | |
| 412 | * | |
| 413 | * PTA is calculated from | |
| 414 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| 415 | * | |
| 416 | * gclk CPU clock (not bus clock!) | |
| 417 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 418 | * | |
| 419 | * 4096 Rows from SDRAM example configuration | |
| 420 | * 1000 factor s -> ms | |
| 421 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 422 | * 4 Number of refresh cycles per period | |
| 423 | * 64 Refresh cycle in ms per number of rows | |
| 424 | * -------------------------------------------- | |
| 425 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| 426 | * | |
| 427 | * 50 MHz => 50.000.000 / Divider = 98 | |
| 428 | * 66 Mhz => 66.000.000 / Divider = 129 | |
| 429 | * 80 Mhz => 80.000.000 / Divider = 156 | |
| 430 | * 100 Mhz => 100.000.000 / Divider = 195 | |
| 431 | */ | |
| 432 | #if defined(CONFIG_100MHz) | |
| 433 | #define CFG_MAMR_PTA 195 | |
| 434 | #elif defined(CONFIG_80MHz) | |
| 435 | #define CFG_MAMR_PTA 156 | |
| 436 | #elif defined(CONFIG_66MHz) | |
| 437 | #define CFG_MAMR_PTA 129 | |
| 438 | #else /* 50 MHz */ | |
| 439 | #define CFG_MAMR_PTA 98 | |
| 440 | #endif /*CONFIG_??MHz */ | |
| 441 | ||
| 442 | /* | |
| 443 | * For 16 MBit, refresh rates could be 31.3 us | |
| 444 | * (= 64 ms / 2K = 125 / quad bursts). | |
| 445 | * For a simpler initialization, 15.6 us is used instead. | |
| 446 | * | |
| 447 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
| 448 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
| 449 | */ | |
| 450 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
| 451 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| 452 | ||
| 453 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| 454 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
| 455 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| 456 | ||
| 457 | /* | |
| 458 | * MAMR settings for SDRAM | |
| 459 | */ | |
| 460 | ||
| 461 | /* 8 column SDRAM */ | |
| 462 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
| 463 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
| 464 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 465 | /* 9 column SDRAM */ | |
| 466 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
| 467 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
| 468 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 469 | ||
| 470 | ||
| 471 | /* | |
| 472 | * Internal Definitions | |
| 473 | * | |
| 474 | * Boot Flags | |
| 475 | */ | |
| 476 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 477 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 478 | ||
| 479 | #define CONFIG_NET_MULTI | |
| 480 | #define CONFIG_SCC1_ENET | |
| 481 | #define CONFIG_FEC_ENET | |
| 482 | #define CONFIG_ETHPRIME "SCC ETHERNET" | |
| 483 | ||
| 484 | #endif /* __CONFIG_H */ |