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d4ca31c4 WD |
1 | /* |
2 | * (C) Copyright 2000-2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c178d3da | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d4ca31c4 WD |
16 | * GNU General Public License for more details. |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
37 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
38 | ||
68766094 | 39 | #define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */ |
75d1ea7f | 40 | #define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
c178d3da | 41 | #define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ |
68766094 | 42 | #define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ |
c178d3da WD |
43 | /* (it will be used if there is no */ |
44 | /* 'cpuclk' variable with valid value) */ | |
d4ca31c4 | 45 | |
75d1ea7f WD |
46 | #undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */ |
47 | /* (function measure_gclk() */ | |
48 | /* will be called) */ | |
49 | #ifdef CFG_MEASURE_CPUCLK | |
50 | #define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
51 | #endif | |
52 | ||
c178d3da | 53 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
d4ca31c4 WD |
54 | |
55 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
56 | ||
c178d3da | 57 | #define CONFIG_BOOTCOUNT_LIMIT |
d4ca31c4 WD |
58 | |
59 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
60 | ||
61 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
62 | ||
c178d3da | 63 | #define CONFIG_PREBOOT "echo;" \ |
d4ca31c4 WD |
64 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ |
65 | "echo" | |
66 | ||
67 | #undef CONFIG_BOOTARGS | |
68 | ||
c178d3da | 69 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
d4ca31c4 WD |
70 | "netdev=eth0\0" \ |
71 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
72 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
73 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
74 | "addip=setenv bootargs $(bootargs) " \ | |
75 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
76 | ":$(hostname):$(netdev):off panic=1\0" \ | |
77 | "flash_nfs=run nfsargs addip;" \ | |
78 | "bootm $(kernel_addr)\0" \ | |
79 | "flash_self=run ramargs addip;" \ | |
80 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
81 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
82 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
5e4be00f | 83 | "bootfile=/tftpboot/TQM866M/uImage\0" \ |
d4ca31c4 WD |
84 | "kernel_addr=40080000\0" \ |
85 | "ramdisk_addr=40180000\0" \ | |
86 | "" | |
87 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
88 | ||
89 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
90 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
91 | ||
92 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
93 | ||
c178d3da | 94 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
d4ca31c4 WD |
95 | |
96 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
97 | ||
98 | /* enable I2C and select the hardware/software driver */ | |
99 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
c178d3da | 100 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
d4ca31c4 WD |
101 | |
102 | #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ | |
103 | #define CFG_I2C_SLAVE 0xFE | |
104 | ||
105 | #ifdef CONFIG_SOFT_I2C | |
106 | /* | |
107 | * Software (bit-bang) I2C driver configuration | |
108 | */ | |
109 | #define PB_SCL 0x00000020 /* PB 26 */ | |
110 | #define PB_SDA 0x00000010 /* PB 27 */ | |
111 | ||
112 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
113 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
114 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
115 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
116 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
c178d3da | 117 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
d4ca31c4 | 118 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
c178d3da | 119 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
d4ca31c4 WD |
120 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
121 | #endif /* CONFIG_SOFT_I2C */ | |
122 | ||
123 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ | |
c178d3da | 124 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ |
d4ca31c4 WD |
125 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 |
126 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
127 | ||
128 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) | |
129 | ||
130 | #define CONFIG_MAC_PARTITION | |
131 | #define CONFIG_DOS_PARTITION | |
132 | ||
c178d3da | 133 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
d4ca31c4 WD |
134 | |
135 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
136 | CFG_CMD_ASKENV | \ | |
137 | CFG_CMD_DHCP | \ | |
138 | CFG_CMD_EEPROM | \ | |
139 | CFG_CMD_IDE | \ | |
140 | CFG_CMD_I2C | \ | |
141 | CFG_CMD_DATE ) | |
142 | ||
143 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
144 | #include <cmd_confdefs.h> | |
145 | ||
146 | /* | |
147 | * Miscellaneous configurable options | |
148 | */ | |
c178d3da WD |
149 | #define CFG_LONGHELP /* undef to save memory */ |
150 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
d4ca31c4 WD |
151 | |
152 | #if 0 | |
c178d3da | 153 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
d4ca31c4 WD |
154 | #endif |
155 | #ifdef CFG_HUSH_PARSER | |
c178d3da | 156 | #define CFG_PROMPT_HUSH_PS2 "> " |
d4ca31c4 WD |
157 | #endif |
158 | ||
159 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
c178d3da | 160 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4ca31c4 | 161 | #else |
c178d3da | 162 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
d4ca31c4 | 163 | #endif |
c178d3da WD |
164 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
165 | #define CFG_MAXARGS 16 /* max number of command args */ | |
d4ca31c4 WD |
166 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
167 | ||
168 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
169 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
170 | ||
c178d3da | 171 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
d4ca31c4 | 172 | |
c178d3da | 173 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d4ca31c4 WD |
174 | |
175 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
176 | ||
177 | /* | |
178 | * Low Level Configuration Settings | |
179 | * (address mappings, register initial values, etc.) | |
180 | * You should know what you are doing if you make changes here. | |
181 | */ | |
182 | /*----------------------------------------------------------------------- | |
183 | * Internal Memory Mapped Register | |
184 | */ | |
185 | #define CFG_IMMR 0xFFF00000 | |
186 | ||
187 | /*----------------------------------------------------------------------- | |
188 | * Definitions for initial stack pointer and data area (in DPRAM) | |
189 | */ | |
190 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
c178d3da WD |
191 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
192 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
d4ca31c4 | 193 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
c178d3da | 194 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
d4ca31c4 WD |
195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * Start addresses for the final memory configuration | |
198 | * (Set up by the startup code) | |
199 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
200 | */ | |
c178d3da | 201 | #define CFG_SDRAM_BASE 0x00000000 |
d4ca31c4 | 202 | #define CFG_FLASH_BASE 0x40000000 |
c178d3da | 203 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
d4ca31c4 | 204 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
c178d3da | 205 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
d4ca31c4 WD |
206 | |
207 | /* | |
208 | * For booting Linux, the board info and command line data | |
209 | * have to be in the first 8 MB of memory, since this is | |
210 | * the maximum mapped by the Linux kernel during initialization. | |
211 | */ | |
c178d3da | 212 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d4ca31c4 WD |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * FLASH organization | |
216 | */ | |
217 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
218 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
219 | ||
220 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
221 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
222 | ||
c178d3da WD |
223 | #define CFG_ENV_IS_IN_FLASH 1 |
224 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
225 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
226 | #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ | |
d4ca31c4 WD |
227 | |
228 | /* Address and size of Redundant Environment Sector */ | |
229 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) | |
230 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
231 | ||
232 | /*----------------------------------------------------------------------- | |
233 | * Hardware Information Block | |
234 | */ | |
235 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
c178d3da | 236 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
d4ca31c4 WD |
237 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
238 | ||
239 | /*----------------------------------------------------------------------- | |
240 | * Cache Configuration | |
241 | */ | |
242 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
243 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
244 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
245 | #endif | |
246 | ||
247 | /*----------------------------------------------------------------------- | |
248 | * SYPCR - System Protection Control 11-9 | |
249 | * SYPCR can only be written once after reset! | |
250 | *----------------------------------------------------------------------- | |
251 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
252 | */ | |
253 | #if defined(CONFIG_WATCHDOG) | |
254 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
255 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
256 | #else | |
257 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
258 | #endif | |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * SIUMCR - SIU Module Configuration 11-6 | |
262 | *----------------------------------------------------------------------- | |
263 | * PCMCIA config., multi-function pin tri-state | |
264 | */ | |
c178d3da | 265 | #ifndef CONFIG_CAN_DRIVER |
d4ca31c4 WD |
266 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
267 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
268 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
269 | #endif /* CONFIG_CAN_DRIVER */ | |
270 | ||
271 | /*----------------------------------------------------------------------- | |
272 | * TBSCR - Time Base Status and Control 11-26 | |
273 | *----------------------------------------------------------------------- | |
274 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
275 | */ | |
276 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
277 | ||
278 | /*----------------------------------------------------------------------- | |
279 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
280 | *----------------------------------------------------------------------- | |
281 | */ | |
282 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
283 | ||
284 | /*----------------------------------------------------------------------- | |
285 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
286 | *----------------------------------------------------------------------- | |
287 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
288 | */ | |
289 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
290 | ||
d4ca31c4 WD |
291 | /*----------------------------------------------------------------------- |
292 | * SCCR - System Clock and reset Control Register 15-27 | |
293 | *----------------------------------------------------------------------- | |
294 | * Set clock output, timebase and RTC source and divider, | |
295 | * power management and some other internal clocks | |
296 | */ | |
297 | #define SCCR_MASK SCCR_EBDF11 | |
c178d3da | 298 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d4ca31c4 WD |
299 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
300 | SCCR_DFALCD00) | |
d4ca31c4 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * PCMCIA stuff | |
304 | *----------------------------------------------------------------------- | |
305 | * | |
306 | */ | |
307 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
308 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
309 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
310 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
311 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
312 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
313 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
314 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
315 | ||
316 | /*----------------------------------------------------------------------- | |
317 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
318 | *----------------------------------------------------------------------- | |
319 | */ | |
320 | ||
c178d3da | 321 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
d4ca31c4 | 322 | |
c178d3da WD |
323 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
324 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
d4ca31c4 WD |
325 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
326 | ||
327 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
328 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
329 | ||
330 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
331 | ||
332 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
333 | ||
334 | /* Offset for data I/O */ | |
335 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
336 | ||
337 | /* Offset for normal register accesses */ | |
338 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
339 | ||
340 | /* Offset for alternate registers */ | |
341 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
342 | ||
343 | /*----------------------------------------------------------------------- | |
344 | * | |
345 | *----------------------------------------------------------------------- | |
346 | * | |
347 | */ | |
c178d3da | 348 | #define CFG_DER 0 |
d4ca31c4 WD |
349 | |
350 | /* | |
351 | * Init Memory Controller: | |
352 | * | |
353 | * BR0/1 and OR0/1 (FLASH) | |
354 | */ | |
355 | ||
356 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
357 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
358 | ||
359 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
360 | * restrict access enough to keep SRAM working (if any) | |
361 | * but not too much to meddle with FLASH accesses | |
362 | */ | |
363 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
364 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
365 | ||
366 | /* | |
c178d3da | 367 | * FLASH timing: Default value of OR0 after reset |
d4ca31c4 | 368 | */ |
c178d3da WD |
369 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
370 | OR_SCY_15_CLK | OR_TRLX) | |
d4ca31c4 WD |
371 | |
372 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
373 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
374 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
375 | ||
376 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
377 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
378 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
379 | ||
380 | /* | |
381 | * BR2/3 and OR2/3 (SDRAM) | |
382 | * | |
383 | */ | |
384 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
385 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
c178d3da | 386 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
d4ca31c4 WD |
387 | |
388 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
389 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
390 | ||
391 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
392 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
393 | ||
c178d3da WD |
394 | #ifndef CONFIG_CAN_DRIVER |
395 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
d4ca31c4 WD |
396 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
397 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
c178d3da | 398 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
d4ca31c4 WD |
399 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
400 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
401 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
402 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
403 | #endif /* CONFIG_CAN_DRIVER */ | |
404 | ||
c178d3da WD |
405 | /* |
406 | * | |
407 | * 4096 Rows from SDRAM example configuration | |
408 | * 1000 factor s -> ms | |
409 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
410 | * 4 Number of refresh cycles per period | |
411 | * 64 Refresh cycle in ms per number of rows | |
412 | */ | |
413 | #define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) | |
414 | ||
d4ca31c4 WD |
415 | /* |
416 | * Memory Periodic Timer Prescaler | |
c178d3da WD |
417 | * Periodic timer for refresh, start with refresh rate for 40 MHz clock |
418 | * (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK) | |
d4ca31c4 | 419 | */ |
c178d3da | 420 | #define CFG_MAMR_PTA 39 |
d4ca31c4 WD |
421 | |
422 | /* | |
423 | * For 16 MBit, refresh rates could be 31.3 us | |
424 | * (= 64 ms / 2K = 125 / quad bursts). | |
425 | * For a simpler initialization, 15.6 us is used instead. | |
426 | * | |
427 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
428 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
429 | */ | |
430 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
431 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
432 | ||
433 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
434 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
435 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
436 | ||
437 | /* | |
438 | * MAMR settings for SDRAM | |
439 | */ | |
440 | ||
441 | /* 8 column SDRAM */ | |
442 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
443 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
444 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
445 | /* 9 column SDRAM */ | |
446 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
447 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
448 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
c178d3da WD |
449 | /* 10 column SDRAM */ |
450 | #define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
451 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ | |
452 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
d4ca31c4 WD |
453 | |
454 | /* | |
455 | * Internal Definitions | |
456 | * | |
457 | * Boot Flags | |
458 | */ | |
c178d3da | 459 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
d4ca31c4 WD |
460 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
461 | ||
462 | #define CONFIG_SCC1_ENET | |
463 | #define CONFIG_FEC_ENET | |
464 | #define CONFIG_ETHPRIME "SCC ETHERNET" | |
465 | ||
466 | #endif /* __CONFIG_H */ |