[people/ms/u-boot.git] / include / configs / Total5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Check valid setting of revision define.
 * Total5100 and Total5200 Rev.1 are identical except for the processor.
 */
#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
#error CONFIG_TOTAL5200_REV must be 1 or 2
#endif

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Video console
 */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SED13806
#define CONFIG_VIDEO_SED13806_16BPP

#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
/* #define CONFIG_VIDEO_BMP_LOGO */
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN


#ifdef CONFIG_MPC5200	/* MGT5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#else	/* MGT5100 */

#define CONFIG_MII		1

#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#if defined(CONFIG_MPC5200)
    #define CONFIG_CMD_PCI
#endif

#define CONFIG_CMD_BMP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB


#if (TEXT_BASE == 0xFE000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	\
	"setenv stdout serial;setenv stderr serial;" \
	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#if CONFIG_TOTAL5200_REV==2
#   define CFG_MAX_FLASH_BANKS	3	/* max num of flash banks */
#   define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
#else
#   define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks  */
#   define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#endif
#define CFG_FLASH_EMPTY_INFO
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#if CONFIG_TOTAL5200_REV==1
#   define CFG_FLASH_BASE	0xFE000000
#   define CFG_FLASH_SIZE	0x02000000
#elif CONFIG_TOTAL5200_REV==2
#   define CFG_FLASH_BASE	0xFA000000
#   define CFG_FLASH_SIZE	0x06000000
#endif /* CONFIG_TOTAL5200_REV */

#if defined(CFG_LOWBOOT)
#   define CONFIG_ENV_ADDR		0xFE040000
#else	/* CFG_LOWBOOT */
#   define CONFIG_ENV_ADDR		0xFFF40000
#endif	/* CFG_LOWBOOT */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x40000
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000
#define CFG_MBAR		0xF0000000	/*   64 kB */
#define CFG_FPGA_BASE		0xF0010000	/*   64 kB */
#define CFG_CPLD_BASE		0xF0020000	/*   64 kB */
#define CFG_LCD_BASE		0xF1000000	/* 4096 kB */

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */

#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/* dummy, 7-wire FEC does not have phy address */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
 * Reserved                                                      0
 * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
 * CS7:   Interrupt GPIO on PSC3_5                               0
 * CS8:   Interrupt GPIO on PSC3_4                               0
 * ATA:   reset default, changed in ATA driver                   00
 * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
 * IRDA:  reset default, changed in IrDA driver                  000
 * ETHER: reset default, changed in Ethernet driver              0000
 * PCI_DIS: reset default, changed in PCI driver                 0
 * USB_SE: reset default, changed in USB driver                  0
 * USB:   reset default, changed in USB driver                   00
 * PSC3:  SPI and UART functionality without CD                  1100
 * Reserved                                                      0
 * PSC2:  CAN1/2                                                 001
 * Reserved                                                      0
 * PSC1:  reset default, changed in AC'97 driver                 000
 *
 */
#define CFG_GPS_PORT_CONFIG	0x00000C10

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#if defined (CONFIG_MGT5100)
#   define CONFIG_BOARD_EARLY_INIT_R	/* switch from CS_BOOT to CS0 */
#endif

#if CONFIG_TOTAL5200_REV==1
#   define CFG_BOOTCS_START	CFG_FLASH_BASE
#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CFG_CS0_START	CFG_FLASH_BASE
#   define CFG_CS0_SIZE		0x02000000	/* 32 MB */
#else
#   define CFG_BOOTCS_START	(CFG_CS4_START + CFG_CS4_SIZE)
#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CFG_CS4_START	(CFG_CS5_START + CFG_CS5_SIZE)
#   define CFG_CS4_SIZE		0x02000000	/* 32 MB */
#   define CFG_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#   define CFG_CS5_START	CFG_FLASH_BASE
#   define CFG_CS5_SIZE		0x02000000	/* 32 MB */
#   define CFG_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
#endif

#define CFG_CS1_START		CFG_FPGA_BASE
#define CFG_CS1_SIZE		0x00010000	/* 64 kB */
#define CFG_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */

#define CFG_CS2_START		CFG_LCD_BASE
#define CFG_CS2_SIZE		0x00400000	/* 4096 kB */
#define CFG_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */

#if CONFIG_TOTAL5200_REV==1
#   define CFG_CS3_START	CFG_CPLD_BASE
#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
#   define CFG_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
#else
#   define CFG_CS3_START	CFG_CPLD_BASE
#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
#   define CFG_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
#endif

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
6c7a1408 WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* Check valid setting of revision define.
	32	* Total5100 and Total5200 Rev.1 are identical except for the processor.
	33	*/
	34	#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
	35	#error CONFIG_TOTAL5200_REV must be 1 or 2
	36	#endif
	37
	38	/*
	39	* High Level Configuration Options
	40	* (easy to change)
	41	*/
	42
	43	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	44	#define CONFIG_TOTAL5200 1 /* ... on Total5200 board */
	45
	46	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	47
	48	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	49	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	50
31d82672 BB	51	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	52
6c7a1408 WD	53	/*
	54	* Serial console configuration
	55	*/
	56	#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
	57	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	58	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	59
81050926 WD	60	/*
	61	* Video console
	62	*/
281e00a3	63	#define CONFIG_VIDEO
81050926 WD	64	#define CONFIG_VIDEO_SED13806
	65	#define CONFIG_VIDEO_SED13806_16BPP
	66
	67	#define CONFIG_CFB_CONSOLE
	68	#define CONFIG_VIDEO_LOGO
	69	/* #define CONFIG_VIDEO_BMP_LOGO */
	70	#define CONFIG_CONSOLE_EXTRA_INFO
	71	#define CONFIG_VGA_AS_SINGLE_DEVICE
	72	#define CONFIG_VIDEO_SW_CURSOR
	73	#define CONFIG_SPLASH_SCREEN
	74
6c7a1408 WD	75
	76	#ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */
	77	/*
	78	* PCI Mapping:
	79	* 0x40000000 - 0x4fffffff - PCI Memory
	80	* 0x50000000 - 0x50ffffff - PCI IO Space
	81	*/
	82	#define CONFIG_PCI 1
	83	#define CONFIG_PCI_PNP 1
	84	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	85	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6c7a1408 WD	86
	87	#define CONFIG_PCI_MEM_BUS 0x40000000
	88	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	89	#define CONFIG_PCI_MEM_SIZE 0x10000000
	90
	91	#define CONFIG_PCI_IO_BUS 0x50000000
	92	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	93	#define CONFIG_PCI_IO_SIZE 0x01000000
	94
	95	#define CONFIG_NET_MULTI 1
63ff004c	96	#define CONFIG_MII 1
6c7a1408 WD	97	#define CONFIG_EEPRO100 1
	98	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	99	#define CONFIG_NS8382X 1
	100
6c7a1408 WD	101	#else /* MGT5100 */
6c7a1408 WD	102
63ff004c	103	#define CONFIG_MII 1
6c7a1408 WD	104
	105	#endif
	106
	107	/* Partitions */
	108	#define CONFIG_MAC_PARTITION
	109	#define CONFIG_DOS_PARTITION
	110
	111	/* USB */
6c7a1408	112	#define CONFIG_USB_OHCI
6c7a1408	113	#define CONFIG_USB_STORAGE
d794cfef	114
6c7a1408	115
a1aa0bb5 JL	116	/*
	117	* BOOTP options
	118	*/
	119	#define CONFIG_BOOTP_BOOTFILESIZE
	120	#define CONFIG_BOOTP_BOOTPATH
	121	#define CONFIG_BOOTP_GATEWAY
	122	#define CONFIG_BOOTP_HOSTNAME
	123
	124
6c7a1408	125	/*
d794cfef	126	* Command line configuration.
6c7a1408	127	*/
d794cfef JL	128	#include <config_cmd_default.h>
d794cfef JL	129
e4dbe1b2	130	#if defined(CONFIG_MPC5200)
d794cfef JL	131	#define CONFIG_CMD_PCI
	132	#endif
	133
	134	#define CONFIG_CMD_BMP
	135	#define CONFIG_CMD_EEPROM
	136	#define CONFIG_CMD_FAT
	137	#define CONFIG_CMD_I2C
	138	#define CONFIG_CMD_IDE
	139	#define CONFIG_CMD_PING
	140	#define CONFIG_CMD_USB
	141
6c7a1408 WD	142
	143	#if (TEXT_BASE == 0xFE000000) /* Boot low */
	144	# define CFG_LOWBOOT 1
	145	#endif
	146
	147	/*
	148	* Autobooting
	149	*/
	150	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	151
81050926 WD	152	#define CONFIG_PREBOOT \
	153	"setenv stdout serial;setenv stderr serial;" \
	154	"echo;" \
32bf3d14	155	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6c7a1408 WD	156	"echo"
	157
	158	#undef CONFIG_BOOTARGS
	159
	160	#define CONFIG_EXTRA_ENV_SETTINGS \
	161	"netdev=eth0\0" \
	162	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	163	"nfsroot=${serverip}:${rootpath}\0" \
6c7a1408	164	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	165	"addip=setenv bootargs ${bootargs} " \
	166	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	167	":${hostname}:${netdev}:off panic=1\0" \
6c7a1408	168	"flash_nfs=run nfsargs addip;" \
fe126d8b	169	"bootm ${kernel_addr}\0" \
6c7a1408	170	"flash_self=run ramargs addip;" \
fe126d8b WD	171	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	172	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
6c7a1408 WD	173	"rootpath=/opt/eldk/ppc_82xx\0" \
	174	"bootfile=/tftpboot/MPC5200/uImage\0" \
	175	""
	176
	177	#define CONFIG_BOOTCOMMAND "run flash_self"
	178
	179	#if defined(CONFIG_MPC5200)
	180	/*
	181	* IPB Bus clocking configuration.
	182	*/
53677ef1	183	#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6c7a1408 WD	184	#endif
	185
	186	/*
	187	* I2C configuration
	188	*/
	189	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	190	#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
	191
	192	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	193	#define CFG_I2C_SLAVE 0x7F
	194
	195	/*
	196	* EEPROM configuration
	197	*/
	198	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	199	#define CFG_I2C_EEPROM_ADDR_LEN 1
	200	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	201	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
	202
	203	/*
	204	* Flash configuration
	205	*/
	206	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	207	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6c7a1408 WD	208	#if CONFIG_TOTAL5200_REV==2
	209	# define CFG_MAX_FLASH_BANKS 3 /* max num of flash banks */
	210	# define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
	211	#else
	212	# define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
	213	# define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
	214	#endif
	215	#define CFG_FLASH_EMPTY_INFO
	216	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	217
	218	#if CONFIG_TOTAL5200_REV==1
	219	# define CFG_FLASH_BASE 0xFE000000
	220	# define CFG_FLASH_SIZE 0x02000000
	221	#elif CONFIG_TOTAL5200_REV==2
	222	# define CFG_FLASH_BASE 0xFA000000
	223	# define CFG_FLASH_SIZE 0x06000000
	224	#endif /* CONFIG_TOTAL5200_REV */
	225
81050926	226	#if defined(CFG_LOWBOOT)
0e8d1586	227	# define CONFIG_ENV_ADDR 0xFE040000
6c7a1408	228	#else /* CFG_LOWBOOT */
0e8d1586	229	# define CONFIG_ENV_ADDR 0xFFF40000
6c7a1408 WD	230	#endif /* CFG_LOWBOOT */
	231
	232	/*
	233	* Environment settings
	234	*/
5a1aceb0	235	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	236	#define CONFIG_ENV_SIZE 0x40000
0e8d1586 JCPV	237	#define CONFIG_ENV_SECT_SIZE 0x40000
6c7a1408 WD	238	#define CONFIG_ENV_OVERWRITE 1
	239
	240	/*
	241	* Memory map
	242	*/
	243	#define CFG_SDRAM_BASE 0x00000000
	244	#define CFG_DEFAULT_MBAR 0x80000000
	245	#define CFG_MBAR 0xF0000000 /* 64 kB */
	246	#define CFG_FPGA_BASE 0xF0010000 /* 64 kB */
	247	#define CFG_CPLD_BASE 0xF0020000 /* 64 kB */
81050926	248	#define CFG_LCD_BASE 0xF1000000 /* 4096 kB */
6c7a1408 WD	249
	250	/* Use SRAM until RAM will be available */
	251	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	252	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	253
	254	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	255	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	256	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	257
	258	#define CFG_MONITOR_BASE TEXT_BASE
	259	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	260	# define CFG_RAMBOOT 1
	261	#endif
	262
	263	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	264	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	265	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	266
	267	/*
	268	* Ethernet configuration
	269	*/
	270	#define CONFIG_MPC5xxx_FEC 1
	271	/* dummy, 7-wire FEC does not have phy address */
	272	#define CONFIG_PHY_ADDR 0x00
	273
	274	/*
	275	* GPIO configuration
	276	*
	277	* CS1: SDRAM CS1 disabled, gpio_wkup_6 enabled 0
	278	* Reserved 0
	279	* ALTs: CAN1/2 on PSC2, SPI on PSC3 00
	280	* CS7: Interrupt GPIO on PSC3_5 0
	281	* CS8: Interrupt GPIO on PSC3_4 0
	282	* ATA: reset default, changed in ATA driver 00
	283	* IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO 0
	284	* IRDA: reset default, changed in IrDA driver 000
	285	* ETHER: reset default, changed in Ethernet driver 0000
	286	* PCI_DIS: reset default, changed in PCI driver 0
	287	* USB_SE: reset default, changed in USB driver 0
	288	* USB: reset default, changed in USB driver 00
	289	* PSC3: SPI and UART functionality without CD 1100
	290	* Reserved 0
	291	* PSC2: CAN1/2 001
	292	* Reserved 0
	293	* PSC1: reset default, changed in AC'97 driver 000
	294	*
	295	*/
	296	#define CFG_GPS_PORT_CONFIG 0x00000C10
	297
	298	/*
	299	* Miscellaneous configurable options
	300	*/
	301	#define CFG_LONGHELP /* undef to save memory */
	302	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
d794cfef	303	#if defined(CONFIG_CMD_KGDB)
6c7a1408 WD	304	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	305	#else
	306	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	307	#endif
	308	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	309	#define CFG_MAXARGS 16 /* max number of command args */
	310	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	311
	312	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	313	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	314
	315	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	316
	317	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	318
d794cfef JL	319	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	320	#if defined(CONFIG_CMD_KGDB)
	321	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	322	#endif
	323
	324
6c7a1408 WD	325	/*
	326	* Various low-level settings
	327	*/
	328	#if defined(CONFIG_MPC5200)
	329	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	330	#define CFG_HID0_FINAL HID0_ICE
	331	#else
	332	#define CFG_HID0_INIT 0
	333	#define CFG_HID0_FINAL 0
	334	#endif
	335
	336	#if defined (CONFIG_MGT5100)
	337	# define CONFIG_BOARD_EARLY_INIT_R /* switch from CS_BOOT to CS0 */
	338	#endif
	339
	340	#if CONFIG_TOTAL5200_REV==1
	341	# define CFG_BOOTCS_START CFG_FLASH_BASE
	342	# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
	343	# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	344	# define CFG_CS0_START CFG_FLASH_BASE
	345	# define CFG_CS0_SIZE 0x02000000 /* 32 MB */
	346	#else
	347	# define CFG_BOOTCS_START (CFG_CS4_START + CFG_CS4_SIZE)
	348	# define CFG_BOOTCS_SIZE 0x02000000 /* 32 MB */
	349	# define CFG_BOOTCS_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	350	# define CFG_CS4_START (CFG_CS5_START + CFG_CS5_SIZE)
	351	# define CFG_CS4_SIZE 0x02000000 /* 32 MB */
	352	# define CFG_CS4_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	353	# define CFG_CS5_START CFG_FLASH_BASE
	354	# define CFG_CS5_SIZE 0x02000000 /* 32 MB */
	355	# define CFG_CS5_CFG 0x0004DF00 /* 4WS, MX, AL, CE, AS_25, DS_32 */
	356	#endif
	357
	358	#define CFG_CS1_START CFG_FPGA_BASE
	359	#define CFG_CS1_SIZE 0x00010000 /* 64 kB */
	360	#define CFG_CS1_CFG 0x0019FF00 /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
	361
	362	#define CFG_CS2_START CFG_LCD_BASE
81050926	363	#define CFG_CS2_SIZE 0x00400000 /* 4096 kB */
89394047	364	#define CFG_CS2_CFG 0x0032FD0C /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
6c7a1408 WD	365
	366	#if CONFIG_TOTAL5200_REV==1
	367	# define CFG_CS3_START CFG_CPLD_BASE
	368	# define CFG_CS3_SIZE 0x00010000 /* 64 kB */
	369	# define CFG_CS3_CFG 0x000ADF00 /* 10WS, MX, AL, CE, AS_25, DS_32 */
	370	#else
	371	# define CFG_CS3_START CFG_CPLD_BASE
	372	# define CFG_CS3_SIZE 0x00010000 /* 64 kB */
	373	# define CFG_CS3_CFG 0x000AD800 /* 10WS, MX, AL, CE, AS_24, DS_8 */
	374	#endif
	375
	376	#define CFG_CS_BURST 0x00000000
	377	#define CFG_CS_DEADCYCLE 0x33333333
	378
	379	/*-----------------------------------------------------------------------
	380	* USB stuff
	381	*-----------------------------------------------------------------------
	382	*/
	383	#define CONFIG_USB_CLOCK 0x0001BBBB
	384	#define CONFIG_USB_CONFIG 0x00001000
	385
	386	/*-----------------------------------------------------------------------
	387	* IDE/ATA stuff Supports IDE harddisk
	388	*-----------------------------------------------------------------------
	389	*/
	390
	391	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	392
	393	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	394	#undef CONFIG_IDE_LED /* LED for ide not supported */
	395
	396	#define CONFIG_IDE_RESET /* reset for ide supported */
	397	#define CONFIG_IDE_PREINIT
	398
	399	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	400	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	401
	402	#define CFG_ATA_IDE0_OFFSET 0x0000
	403
	404	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	405
	406	/* Offset for data I/O */
	407	#define CFG_ATA_DATA_OFFSET (0x0060)
	408
	409	/* Offset for normal register accesses */
	410	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	411
	412	/* Offset for alternate registers */
	413	#define CFG_ATA_ALT_OFFSET (0x005C)
	414
	415	/* Interval between registers */
	416	#define CFG_ATA_STRIDE 4
	417
	418	#endif /* __CONFIG_H */