projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8b0044ff OZ |
1 | /* |
| 2 | * Copyright 2013-2015 Arcturus Networks, Inc. | |
| 3 | * http://www.arcturusnetworks.com/products/ucp1020/ | |
| 4 | * based on include/configs/p1_p2_rdb_pc.h | |
| 5 | * original copyright follows: | |
| 6 | * Copyright 2009-2011 Freescale Semiconductor, Inc. | |
| 7 | * | |
| 8 | * SPDX-License-Identifier: GPL-2.0+ | |
| 9 | */ | |
| 10 | ||
| 11 | /* | |
| 12 | * QorIQ uCP1020-xx boards configuration file | |
| 13 | */ | |
| 14 | #ifndef __CONFIG_H | |
| 15 | #define __CONFIG_H | |
| 16 | ||
| 8b0044ff OZ |
17 | #define CONFIG_DISPLAY_BOARDINFO |
| 18 | ||
| 19 | #define CONFIG_FSL_ELBC | |
| 20 | #define CONFIG_PCI | |
| 21 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ | |
| 22 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 23 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 24 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ | |
| 25 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
| 26 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 27 | ||
| 28 | #if defined(CONFIG_TARTGET_UCP1020T1) | |
| 29 | ||
| 30 | #define CONFIG_UCP1020_REV_1_3 | |
| 31 | ||
| 32 | #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" | |
| 33 | #define CONFIG_P1020 | |
| 34 | ||
| 35 | #define CONFIG_TSEC_ENET | |
| 36 | #define CONFIG_TSEC1 | |
| 37 | #define CONFIG_TSEC3 | |
| 38 | #define CONFIG_HAS_ETH0 | |
| 39 | #define CONFIG_HAS_ETH1 | |
| 40 | #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF | |
| 41 | #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE | |
| 42 | #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD | |
| 43 | #define CONFIG_IPADDR 10.80.41.229 | |
| 44 | #define CONFIG_SERVERIP 10.80.41.227 | |
| 45 | #define CONFIG_NETMASK 255.255.252.0 | |
| 46 | #define CONFIG_ETHPRIME "eTSEC3" | |
| 47 | ||
| 48 | #ifndef CONFIG_SPI_FLASH | |
| 8b0044ff OZ |
49 | #endif |
| 50 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
| 51 | ||
| 52 | #define CONFIG_MMC | |
| 53 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 54 | ||
| 55 | #define CONFIG_LAST_STAGE_INIT | |
| 56 | ||
| 57 | #if !defined(CONFIG_DONGLE) | |
| 58 | #define CONFIG_SILENT_CONSOLE | |
| 59 | #endif | |
| 60 | ||
| 61 | #endif | |
| 62 | ||
| 63 | #if defined(CONFIG_TARGET_UCP1020) | |
| 64 | ||
| 65 | #define CONFIG_UCP1020 | |
| 66 | #define CONFIG_UCP1020_REV_1_3 | |
| 67 | ||
| 68 | #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" | |
| 69 | #define CONFIG_P1020 | |
| 70 | ||
| 71 | #define CONFIG_TSEC_ENET | |
| 72 | #define CONFIG_TSEC1 | |
| 73 | #define CONFIG_TSEC2 | |
| 74 | #define CONFIG_TSEC3 | |
| 75 | #define CONFIG_HAS_ETH0 | |
| 76 | #define CONFIG_HAS_ETH1 | |
| 77 | #define CONFIG_HAS_ETH2 | |
| 78 | #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF | |
| 79 | #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE | |
| 80 | #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD | |
| 81 | #define CONFIG_IPADDR 192.168.1.81 | |
| 82 | #define CONFIG_IPADDR1 192.168.1.82 | |
| 83 | #define CONFIG_IPADDR2 192.168.1.83 | |
| 84 | #define CONFIG_SERVERIP 192.168.1.80 | |
| 85 | #define CONFIG_GATEWAYIP 102.168.1.1 | |
| 86 | #define CONFIG_NETMASK 255.255.255.0 | |
| 87 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 88 | ||
| 89 | #ifndef CONFIG_SPI_FLASH | |
| 8b0044ff OZ |
90 | #endif |
| 91 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
| 92 | ||
| 93 | #define CONFIG_MMC | |
| 94 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 95 | ||
| 96 | #define CONFIG_LAST_STAGE_INIT | |
| 97 | ||
| 98 | #endif | |
| 99 | ||
| 100 | #ifdef CONFIG_SDCARD | |
| 101 | #define CONFIG_RAMBOOT_SDCARD | |
| 102 | #define CONFIG_SYS_RAMBOOT | |
| 103 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 104 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 105 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| 106 | #endif | |
| 107 | ||
| 108 | #ifdef CONFIG_SPIFLASH | |
| 109 | #define CONFIG_RAMBOOT_SPIFLASH | |
| 110 | #define CONFIG_SYS_RAMBOOT | |
| 111 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
| 112 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
| 113 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| 114 | #endif | |
| 115 | ||
| 116 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 117 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| 118 | #endif | |
| 119 | #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 | |
| 120 | ||
| 121 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 122 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 123 | #endif | |
| 124 | ||
| 125 | #ifndef CONFIG_SYS_MONITOR_BASE | |
| 126 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 127 | #endif | |
| 128 | ||
| 129 | /* High Level Configuration Options */ | |
| 130 | #define CONFIG_BOOKE | |
| 131 | #define CONFIG_E500 | |
| 132 | /* #define CONFIG_MPC85xx */ | |
| 133 | ||
| 134 | #define CONFIG_MP | |
| 135 | ||
| 136 | #define CONFIG_FSL_LAW | |
| 137 | ||
| 138 | #define CONFIG_ENV_OVERWRITE | |
| 139 | ||
| 140 | #define CONFIG_CMD_SATA | |
| 141 | #define CONFIG_SATA_SIL | |
| 142 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 143 | #define CONFIG_LIBATA | |
| 144 | #define CONFIG_LBA48 | |
| 145 | ||
| 146 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
| 147 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
| 148 | ||
| 149 | #define CONFIG_HWCONFIG | |
| 150 | ||
| 151 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ | |
| 152 | #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ | |
| 153 | #define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ | |
| 154 | /* | |
| 155 | * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). | |
| 156 | * there will be one entry in this array for each two (dummy) sensors in | |
| 157 | * CONFIG_DTT_SENSORS. | |
| 158 | * | |
| 159 | * For uCP1020 module: | |
| 160 | * - only one ADM1021/NCT72 | |
| 161 | * - i2c addr 0x41 | |
| 162 | * - conversion rate 0x02 = 0.25 conversions/second | |
| 163 | * - ALERT output disabled | |
| 164 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
| 165 | * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg | |
| 166 | */ | |
| 167 | #define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ | |
| 168 | 0x02, 0, 1, 0, 85, 1, 0, 85} } | |
| 169 | ||
| 170 | #define CONFIG_CMD_DTT | |
| 171 | ||
| 172 | /* | |
| 173 | * These can be toggled for performance analysis, otherwise use default. | |
| 174 | */ | |
| 175 | #define CONFIG_L2_CACHE | |
| 176 | #define CONFIG_BTB | |
| 177 | ||
| 178 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ | |
| 179 | ||
| 180 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 181 | ||
| 182 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 183 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
| 184 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 185 | ||
| 186 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 187 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 188 | ||
| 189 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k | |
| 190 | SPL code*/ | |
| 191 | #ifdef CONFIG_SPL_BUILD | |
| 192 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| 193 | #endif | |
| 194 | ||
| 195 | /* DDR Setup */ | |
| 196 | #define CONFIG_DDR_ECC_ENABLE | |
| 197 | #define CONFIG_SYS_FSL_DDR3 | |
| 198 | #ifndef CONFIG_DDR_ECC_ENABLE | |
| 199 | #define CONFIG_SYS_DDR_RAW_TIMING | |
| 200 | #define CONFIG_DDR_SPD | |
| 201 | #endif | |
| 202 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
| 203 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 204 | ||
| 205 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M | |
| 206 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 207 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) | |
| 208 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 209 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 210 | ||
| 211 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 212 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 213 | ||
| 214 | /* Default settings for DDR3 */ | |
| 215 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
| 216 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 217 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 218 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f | |
| 219 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 | |
| 220 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 | |
| 221 | ||
| 222 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 223 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 224 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 225 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 226 | ||
| 227 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 228 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 | |
| 229 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 230 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 231 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| 232 | #ifdef CONFIG_DDR_ECC_ENABLE | |
| 233 | #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ | |
| 234 | #else | |
| 235 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ | |
| 236 | #endif | |
| 237 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 | |
| 238 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
| 239 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 240 | ||
| 241 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 242 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
| 243 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 | |
| 244 | #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF | |
| 245 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
| 246 | #define CONFIG_SYS_DDR_MODE_1 0x40461520 | |
| 247 | #define CONFIG_SYS_DDR_MODE_2 0x8000c000 | |
| 248 | #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 | |
| 249 | ||
| 250 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 251 | ||
| 252 | /* | |
| 253 | * Memory map | |
| 254 | * | |
| 255 | * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable | |
| 256 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) | |
| 257 | * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 | |
| 258 | * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable | |
| 259 | * (early boot only) | |
| 260 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 261 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable | |
| 262 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 263 | */ | |
| 264 | ||
| 265 | /* | |
| 266 | * Local Bus Definitions | |
| 267 | */ | |
| 268 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ | |
| 269 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
| 270 | ||
| 271 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 272 | ||
| 273 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
| 274 | | BR_PS_16 | BR_V) | |
| 275 | ||
| 276 | #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 | |
| 277 | ||
| 278 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 279 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 280 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 281 | ||
| 282 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 283 | ||
| 284 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 285 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 286 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 287 | ||
| 288 | #define CONFIG_FLASH_CFI_DRIVER | |
| 289 | #define CONFIG_SYS_FLASH_CFI | |
| 290 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 291 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 292 | ||
| 293 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 294 | ||
| 295 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 296 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| 297 | /* Initial L1 address */ | |
| 298 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
| 299 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
| 300 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
| 301 | /* Size of used area in RAM */ | |
| 302 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
| 303 | ||
| 304 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 305 | GENERATED_GBL_DATA_SIZE) | |
| 306 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 307 | ||
| 308 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ | |
| 309 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ | |
| 310 | ||
| 311 | #define CONFIG_SYS_PMC_BASE 0xff980000 | |
| 312 | #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE | |
| 313 | #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ | |
| 314 | BR_PS_8 | BR_V) | |
| 315 | #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
| 316 | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ | |
| 317 | OR_GPCM_EAD) | |
| 318 | ||
| 319 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 320 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 321 | #ifdef CONFIG_NAND_FSL_ELBC | |
| 322 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ | |
| 323 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 324 | #endif | |
| 325 | ||
| 326 | /* Serial Port - controlled on board with jumper J8 | |
| 327 | * open - index 2 | |
| 328 | * shorted - index 1 | |
| 329 | */ | |
| 330 | #define CONFIG_CONS_INDEX 1 | |
| 331 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 8b0044ff OZ |
332 | #define CONFIG_SYS_NS16550_SERIAL |
| 333 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 334 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 335 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) | |
| 336 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 337 | #endif | |
| 338 | ||
| 339 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 340 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 341 | ||
| 342 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) | |
| 343 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 344 | ||
| 345 | /* Use the HUSH parser */ | |
| 346 | #define CONFIG_SYS_HUSH_PARSER | |
| 347 | ||
| 348 | /* | |
| 349 | * Pass open firmware flat tree | |
| 350 | */ | |
| 8b0044ff OZ |
351 | #define CONFIG_OF_BOARD_SETUP |
| 352 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 353 | ||
| 354 | /* new uImage format support */ | |
| 355 | #define CONFIG_FIT | |
| 356 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 357 | ||
| 358 | /* I2C */ | |
| 359 | #define CONFIG_SYS_I2C | |
| 360 | #define CONFIG_SYS_I2C_FSL | |
| 361 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 362 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 363 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 364 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 365 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 366 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 367 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
| 368 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ | |
| 369 | ||
| 370 | #define CONFIG_RTC_DS1337 | |
| 371 | #define CONFIG_SYS_RTC_DS1337_NOOSC | |
| 372 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 373 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 | |
| 374 | #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C | |
| 375 | #define CONFIG_SYS_I2C_IDT6V49205B 0x69 | |
| 376 | ||
| 377 | /* | |
| 378 | * eSPI - Enhanced SPI | |
| 379 | */ | |
| 380 | #define CONFIG_HARD_SPI | |
| 8b0044ff | 381 | |
| 8b0044ff OZ |
382 | #define CONFIG_CMD_SF 1 |
| 383 | #define CONFIG_CMD_SPI 1 | |
| 384 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 385 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 386 | ||
| 387 | #if defined(CONFIG_PCI) | |
| 388 | /* | |
| 389 | * General PCI | |
| 390 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 391 | */ | |
| 392 | ||
| 393 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
| 394 | #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" | |
| 395 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 396 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 397 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 398 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 399 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 400 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 401 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 402 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 403 | ||
| 404 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
| 405 | #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" | |
| 406 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
| 407 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 408 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
| 409 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 410 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
| 411 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 412 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
| 413 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 414 | ||
| 415 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 8b0044ff | 416 | #define CONFIG_CMD_PCI |
| 8b0044ff OZ |
417 | |
| 418 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 419 | #define CONFIG_DOS_PARTITION | |
| 420 | #endif /* CONFIG_PCI */ | |
| 421 | ||
| 422 | /* | |
| 423 | * Environment | |
| 424 | */ | |
| 425 | #ifdef CONFIG_ENV_FIT_UCBOOT | |
| 426 | ||
| 427 | #define CONFIG_ENV_IS_IN_FLASH | |
| 428 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) | |
| 429 | #define CONFIG_ENV_SIZE 0x20000 | |
| 430 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 431 | ||
| 432 | #else | |
| 433 | ||
| 434 | #define CONFIG_ENV_SPI_BUS 0 | |
| 435 | #define CONFIG_ENV_SPI_CS 0 | |
| 436 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 437 | #define CONFIG_ENV_SPI_MODE 0 | |
| 438 | ||
| 439 | #ifdef CONFIG_RAMBOOT_SPIFLASH | |
| 440 | ||
| 441 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 442 | #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ | |
| 443 | #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ | |
| 444 | #define CONFIG_ENV_SECT_SIZE 0x1000 | |
| 445 | ||
| 446 | #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) | |
| 447 | /* Address and size of Redundant Environment Sector */ | |
| 448 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
| 449 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 450 | #endif | |
| 451 | ||
| 452 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
| 453 | #define CONFIG_ENV_IS_IN_MMC | |
| 454 | #define CONFIG_FSL_FIXED_MMC_LOCATION | |
| 455 | #define CONFIG_ENV_SIZE 0x2000 | |
| 456 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 457 | ||
| 458 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 459 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
| 460 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 461 | #define CONFIG_ENV_SIZE 0x2000 | |
| 462 | ||
| 463 | #else | |
| 464 | #define CONFIG_ENV_IS_IN_FLASH | |
| 465 | #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) | |
| 466 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 467 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
| 468 | #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) | |
| 469 | #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) | |
| 470 | /* Address and size of Redundant Environment Sector */ | |
| 471 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) | |
| 472 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 473 | #endif | |
| 474 | ||
| 475 | #endif | |
| 476 | ||
| 477 | #endif /* CONFIG_ENV_FIT_UCBOOT */ | |
| 478 | ||
| 479 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 480 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 481 | ||
| 482 | /* | |
| 483 | * Command line configuration. | |
| 484 | */ | |
| 8b0044ff OZ |
485 | #define CONFIG_CMD_IRQ |
| 486 | #define CONFIG_CMD_PING | |
| 487 | #define CONFIG_CMD_I2C | |
| 488 | #define CONFIG_CMD_MII | |
| 489 | #define CONFIG_CMD_DATE | |
| 8b0044ff OZ |
490 | #define CONFIG_CMD_I2C |
| 491 | #define CONFIG_CMD_IRQ | |
| 492 | #define CONFIG_CMD_MII | |
| 493 | #define CONFIG_CMD_PING | |
| 8b0044ff OZ |
494 | #define CONFIG_CMD_REGINFO |
| 495 | #define CONFIG_CMD_ERRATA | |
| 496 | #define CONFIG_CMD_CRAMFS | |
| 497 | #define CONFIG_CRAMFS_CMDLINE | |
| 498 | ||
| 499 | /* | |
| 500 | * USB | |
| 501 | */ | |
| 502 | #define CONFIG_HAS_FSL_DR_USB | |
| 503 | ||
| 504 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 505 | #define CONFIG_USB_EHCI | |
| 506 | ||
| 507 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
| 508 | ||
| 509 | #ifdef CONFIG_USB_EHCI | |
| 510 | #define CONFIG_CMD_USB | |
| 511 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 512 | #define CONFIG_USB_EHCI_FSL | |
| 513 | #define CONFIG_USB_STORAGE | |
| 514 | #endif | |
| 515 | #endif | |
| 516 | ||
| 517 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 518 | ||
| 519 | #ifdef CONFIG_MMC | |
| 520 | #define CONFIG_FSL_ESDHC | |
| 521 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 522 | #define CONFIG_CMD_MMC | |
| 523 | #define CONFIG_MMC_SPI | |
| 524 | #define CONFIG_CMD_MMC_SPI | |
| 525 | #define CONFIG_GENERIC_MMC | |
| 526 | #endif | |
| 527 | ||
| 528 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA) | |
| 529 | #define CONFIG_CMD_EXT2 | |
| 530 | #define CONFIG_CMD_FAT | |
| 531 | #define CONFIG_DOS_PARTITION | |
| 532 | #endif | |
| 533 | ||
| 534 | /* Misc Extra Settings */ | |
| 8b0044ff OZ |
535 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 536 | ||
| 537 | /* | |
| 538 | * Miscellaneous configurable options | |
| 539 | */ | |
| 540 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 541 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 542 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 8b0044ff OZ |
543 | #if defined(CONFIG_CMD_KGDB) |
| 544 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 545 | #else | |
| 546 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 547 | #endif | |
| 548 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 549 | /* Print Buffer Size */ | |
| 550 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 551 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 552 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ | |
| 553 | ||
| 554 | /* | |
| 555 | * For booting Linux, the board info and command line data | |
| 556 | * have to be in the first 64 MB of memory, since this is | |
| 557 | * the maximum mapped by the Linux kernel during initialization. | |
| 558 | */ | |
| 559 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ | |
| 560 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 561 | ||
| 562 | #if defined(CONFIG_CMD_KGDB) | |
| 563 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 564 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 565 | #endif | |
| 566 | ||
| 567 | /* | |
| 568 | * Environment Configuration | |
| 569 | */ | |
| 570 | ||
| 571 | #if defined(CONFIG_TSEC_ENET) | |
| 572 | ||
| 573 | #if defined(CONFIG_UCP1020_REV_1_2) | |
| 574 | #define CONFIG_PHY_MICREL_KSZ9021 | |
| 575 | #elif defined(CONFIG_UCP1020_REV_1_3) | |
| 576 | #define CONFIG_PHY_MICREL_KSZ9031 | |
| 577 | #else | |
| 578 | #error "UCP1020 module revision is not defined !!!" | |
| 579 | #endif | |
| 580 | ||
| 581 | #define CONFIG_CMD_DHCP | |
| 582 | #define CONFIG_BOOTP_SERVERIP | |
| 583 | ||
| 584 | #define CONFIG_MII /* MII PHY management */ | |
| 585 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 586 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 587 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 588 | ||
| 589 | #define TSEC1_PHY_ADDR 4 | |
| 590 | #define TSEC2_PHY_ADDR 0 | |
| 591 | #define TSEC2_PHY_ADDR_SGMII 0x00 | |
| 592 | #define TSEC3_PHY_ADDR 6 | |
| 593 | ||
| 594 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 595 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 596 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 597 | ||
| 598 | #define TSEC1_PHYIDX 0 | |
| 599 | #define TSEC2_PHYIDX 0 | |
| 600 | #define TSEC3_PHYIDX 0 | |
| 601 | ||
| 602 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 603 | ||
| 604 | #endif | |
| 605 | ||
| 606 | #define CONFIG_HOSTNAME UCP1020 | |
| 607 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
| 608 | #define CONFIG_BOOTFILE "uImage" | |
| 609 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
| 610 | ||
| 611 | /* default location for tftp and bootm */ | |
| 612 | #define CONFIG_LOADADDR 1000000 | |
| 613 | ||
| 8b0044ff OZ |
614 | #define CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 615 | ||
| 616 | #define CONFIG_BAUDRATE 115200 | |
| 617 | ||
| 618 | #if defined(CONFIG_DONGLE) | |
| 619 | ||
| 620 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ | |
| 621 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 622 | "bootcmd=run prog_spi_mbrbootcramfs\0" \ | |
| 623 | "bootfile=uImage\0" \ | |
| 624 | "consoledev=ttyS0\0" \ | |
| 625 | "cramfsfile=image.cramfs\0" \ | |
| 626 | "dtbaddr=0x00c00000\0" \ | |
| 627 | "dtbfile=image.dtb\0" \ | |
| 628 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ | |
| 629 | "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ | |
| 630 | "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ | |
| 631 | "fileaddr=0x01000000\0" \ | |
| 632 | "filesize=0x00080000\0" \ | |
| 633 | "flashmbr=sf probe 0; " \ | |
| 634 | "tftp $loadaddr $mbr; " \ | |
| 635 | "sf erase $mbr_offset +$filesize; " \ | |
| 636 | "sf write $loadaddr $mbr_offset $filesize\0" \ | |
| 637 | "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ | |
| 638 | "protect off $nor_recoveryaddr +$filesize; " \ | |
| 639 | "erase $nor_recoveryaddr +$filesize; " \ | |
| 640 | "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ | |
| 641 | "protect on $nor_recoveryaddr +$filesize\0 " \ | |
| 642 | "flashuboot=tftp $ubootaddr $ubootfile; " \ | |
| 643 | "protect off $nor_ubootaddr +$filesize; " \ | |
| 644 | "erase $nor_ubootaddr +$filesize; " \ | |
| 645 | "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ | |
| 646 | "protect on $nor_ubootaddr +$filesize\0 " \ | |
| 647 | "flashworking=tftp $workingaddr $cramfsfile; " \ | |
| 648 | "protect off $nor_workingaddr +$filesize; " \ | |
| 649 | "erase $nor_workingaddr +$filesize; " \ | |
| 650 | "cp.b $workingaddr $nor_workingaddr $filesize; " \ | |
| 651 | "protect on $nor_workingaddr +$filesize\0 " \ | |
| 652 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ | |
| 653 | "kerneladdr=0x01100000\0" \ | |
| 654 | "kernelfile=uImage\0" \ | |
| 655 | "loadaddr=0x01000000\0" \ | |
| 656 | "mbr=uCP1020d.mbr\0" \ | |
| 657 | "mbr_offset=0x00000000\0" \ | |
| 658 | "mmbr=uCP1020Quiet.mbr\0" \ | |
| 659 | "mmcpart=0:2\0" \ | |
| 660 | "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ | |
| 661 | "mmc erase 1 1; " \ | |
| 662 | "mmc write $loadaddr 1 1\0" \ | |
| 663 | "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ | |
| 664 | "mmc erase 0x40 0x400; " \ | |
| 665 | "mmc write $loadaddr 0x40 0x400\0" \ | |
| 666 | "netdev=eth0\0" \ | |
| 667 | "nor_recoveryaddr=0xEC0A0000\0" \ | |
| 668 | "nor_ubootaddr=0xEFF80000\0" \ | |
| 669 | "nor_workingaddr=0xECFA0000\0" \ | |
| 670 | "norbootrecovery=setenv bootargs $recoverybootargs" \ | |
| 671 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 672 | "run norloadrecovery; " \ | |
| 673 | "bootm $kerneladdr - $dtbaddr\0" \ | |
| 674 | "norbootworking=setenv bootargs $workingbootargs" \ | |
| 675 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 676 | "run norloadworking; " \ | |
| 677 | "bootm $kerneladdr - $dtbaddr\0" \ | |
| 678 | "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ | |
| 679 | "setenv cramfsaddr $nor_recoveryaddr; " \ | |
| 680 | "cramfsload $dtbaddr $dtbfile; " \ | |
| 681 | "cramfsload $kerneladdr $kernelfile\0" \ | |
| 682 | "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ | |
| 683 | "setenv cramfsaddr $nor_workingaddr; " \ | |
| 684 | "cramfsload $dtbaddr $dtbfile; " \ | |
| 685 | "cramfsload $kerneladdr $kernelfile\0" \ | |
| 686 | "prog_spi_mbr=run spi__mbr\0" \ | |
| 687 | "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ | |
| 688 | "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ | |
| 689 | "run spi__cramfs\0" \ | |
| 690 | "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ | |
| 691 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 692 | "tftp $rootfsaddr $rootfsfile; " \ | |
| 693 | "tftp $loadaddr $kernelfile; " \ | |
| 694 | "tftp $dtbaddr $dtbfile; " \ | |
| 695 | "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ | |
| 696 | "ramdisk_size=120000\0" \ | |
| 697 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 698 | "recoveryaddr=0x02F00000\0" \ | |
| 699 | "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ | |
| 700 | "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ | |
| 701 | "mw.l 0xffe0f008 0x00400000\0" \ | |
| 702 | "rootfsaddr=0x02F00000\0" \ | |
| 703 | "rootfsfile=rootfs.ext2.gz.uboot\0" \ | |
| 704 | "rootpath=/opt/nfsroot\0" \ | |
| 705 | "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ | |
| 706 | "protect off 0xeC000000 +$filesize; " \ | |
| 707 | "erase 0xEC000000 +$filesize; " \ | |
| 708 | "cp.b $loadaddr 0xEC000000 $filesize; " \ | |
| 709 | "cmp.b $loadaddr 0xEC000000 $filesize; " \ | |
| 710 | "protect on 0xeC000000 +$filesize\0" \ | |
| 711 | "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ | |
| 712 | "protect off 0xeFF80000 +$filesize; " \ | |
| 713 | "erase 0xEFF80000 +$filesize; " \ | |
| 714 | "cp.b $loadaddr 0xEFF80000 $filesize; " \ | |
| 715 | "cmp.b $loadaddr 0xEFF80000 $filesize; " \ | |
| 716 | "protect on 0xeFF80000 +$filesize\0" \ | |
| 717 | "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ | |
| 718 | "sf probe 0; sf erase 0x8000 +$filesize; " \ | |
| 719 | "sf write $loadaddr 0x8000 $filesize\0" \ | |
| 720 | "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ | |
| 721 | "protect off 0xec0a0000 +$filesize; " \ | |
| 722 | "erase 0xeC0A0000 +$filesize; " \ | |
| 723 | "cp.b $loadaddr 0xeC0A0000 $filesize; " \ | |
| 724 | "protect on 0xec0a0000 +$filesize\0" \ | |
| 725 | "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ | |
| 726 | "sf probe 1; sf erase 0 +$filesize; " \ | |
| 727 | "sf write $loadaddr 0 $filesize\0" \ | |
| 728 | "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ | |
| 729 | "sf probe 0; sf erase 0 +$filesize; " \ | |
| 730 | "sf write $loadaddr 0 $filesize\0" \ | |
| 731 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 732 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 733 | "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 734 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ | |
| 735 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 736 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ | |
| 737 | "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 738 | "ubootaddr=0x01000000\0" \ | |
| 739 | "ubootfile=u-boot.bin\0" \ | |
| 740 | "ubootd=u-boot4dongle.bin\0" \ | |
| 741 | "upgrade=run flashworking\0" \ | |
| 742 | "usb_phy_type=ulpi\0 " \ | |
| 743 | "workingaddr=0x02F00000\0" \ | |
| 744 | "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" | |
| 745 | ||
| 746 | #else | |
| 747 | ||
| 748 | #if defined(CONFIG_UCP1020T1) | |
| 749 | ||
| 750 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ | |
| 751 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 752 | "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ | |
| 753 | "bootfile=uImage\0" \ | |
| 754 | "consoledev=ttyS0\0" \ | |
| 755 | "cramfsfile=image.cramfs\0" \ | |
| 756 | "dtbaddr=0x00c00000\0" \ | |
| 757 | "dtbfile=image.dtb\0" \ | |
| 758 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ | |
| 759 | "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ | |
| 760 | "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ | |
| 761 | "fileaddr=0x01000000\0" \ | |
| 762 | "filesize=0x00080000\0" \ | |
| 763 | "flashmbr=sf probe 0; " \ | |
| 764 | "tftp $loadaddr $mbr; " \ | |
| 765 | "sf erase $mbr_offset +$filesize; " \ | |
| 766 | "sf write $loadaddr $mbr_offset $filesize\0" \ | |
| 767 | "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ | |
| 768 | "protect off $nor_recoveryaddr +$filesize; " \ | |
| 769 | "erase $nor_recoveryaddr +$filesize; " \ | |
| 770 | "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ | |
| 771 | "protect on $nor_recoveryaddr +$filesize\0 " \ | |
| 772 | "flashuboot=tftp $ubootaddr $ubootfile; " \ | |
| 773 | "protect off $nor_ubootaddr +$filesize; " \ | |
| 774 | "erase $nor_ubootaddr +$filesize; " \ | |
| 775 | "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ | |
| 776 | "protect on $nor_ubootaddr +$filesize\0 " \ | |
| 777 | "flashworking=tftp $workingaddr $cramfsfile; " \ | |
| 778 | "protect off $nor_workingaddr +$filesize; " \ | |
| 779 | "erase $nor_workingaddr +$filesize; " \ | |
| 780 | "cp.b $workingaddr $nor_workingaddr $filesize; " \ | |
| 781 | "protect on $nor_workingaddr +$filesize\0 " \ | |
| 782 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ | |
| 783 | "kerneladdr=0x01100000\0" \ | |
| 784 | "kernelfile=uImage\0" \ | |
| 785 | "loadaddr=0x01000000\0" \ | |
| 786 | "mbr=uCP1020.mbr\0" \ | |
| 787 | "mbr_offset=0x00000000\0" \ | |
| 788 | "netdev=eth0\0" \ | |
| 789 | "nor_recoveryaddr=0xEC0A0000\0" \ | |
| 790 | "nor_ubootaddr=0xEFF80000\0" \ | |
| 791 | "nor_workingaddr=0xECFA0000\0" \ | |
| 792 | "norbootrecovery=setenv bootargs $recoverybootargs" \ | |
| 793 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 794 | "run norloadrecovery; " \ | |
| 795 | "bootm $kerneladdr - $dtbaddr\0" \ | |
| 796 | "norbootworking=setenv bootargs $workingbootargs" \ | |
| 797 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 798 | "run norloadworking; " \ | |
| 799 | "bootm $kerneladdr - $dtbaddr\0" \ | |
| 800 | "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ | |
| 801 | "setenv cramfsaddr $nor_recoveryaddr; " \ | |
| 802 | "cramfsload $dtbaddr $dtbfile; " \ | |
| 803 | "cramfsload $kerneladdr $kernelfile\0" \ | |
| 804 | "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ | |
| 805 | "setenv cramfsaddr $nor_workingaddr; " \ | |
| 806 | "cramfsload $dtbaddr $dtbfile; " \ | |
| 807 | "cramfsload $kerneladdr $kernelfile\0" \ | |
| 808 | "othbootargs=quiet\0" \ | |
| 809 | "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ | |
| 810 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 811 | "tftp $rootfsaddr $rootfsfile; " \ | |
| 812 | "tftp $loadaddr $kernelfile; " \ | |
| 813 | "tftp $dtbaddr $dtbfile; " \ | |
| 814 | "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ | |
| 815 | "ramdisk_size=120000\0" \ | |
| 816 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 817 | "recoveryaddr=0x02F00000\0" \ | |
| 818 | "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ | |
| 819 | "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ | |
| 820 | "mw.l 0xffe0f008 0x00400000\0" \ | |
| 821 | "rootfsaddr=0x02F00000\0" \ | |
| 822 | "rootfsfile=rootfs.ext2.gz.uboot\0" \ | |
| 823 | "rootpath=/opt/nfsroot\0" \ | |
| 824 | "silent=1\0" \ | |
| 825 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 826 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 827 | "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 828 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ | |
| 829 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 830 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ | |
| 831 | "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 832 | "ubootaddr=0x01000000\0" \ | |
| 833 | "ubootfile=u-boot.bin\0" \ | |
| 834 | "upgrade=run flashworking\0" \ | |
| 835 | "workingaddr=0x02F00000\0" \ | |
| 836 | "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" | |
| 837 | ||
| 838 | #else /* For Arcturus Modules */ | |
| 839 | ||
| 840 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */ | |
| 841 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 842 | "bootcmd=run norkernel\0" \ | |
| 843 | "bootfile=uImage\0" \ | |
| 844 | "consoledev=ttyS0\0" \ | |
| 845 | "dtbaddr=0x00c00000\0" \ | |
| 846 | "dtbfile=image.dtb\0" \ | |
| 847 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ | |
| 848 | "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ | |
| 849 | "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ | |
| 850 | "fileaddr=0x01000000\0" \ | |
| 851 | "filesize=0x00080000\0" \ | |
| 852 | "flashmbr=sf probe 0; " \ | |
| 853 | "tftp $loadaddr $mbr; " \ | |
| 854 | "sf erase $mbr_offset +$filesize; " \ | |
| 855 | "sf write $loadaddr $mbr_offset $filesize\0" \ | |
| 856 | "flashuboot=tftp $loadaddr $ubootfile; " \ | |
| 857 | "protect off $nor_ubootaddr0 +$filesize; " \ | |
| 858 | "erase $nor_ubootaddr0 +$filesize; " \ | |
| 859 | "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ | |
| 860 | "protect on $nor_ubootaddr0 +$filesize; " \ | |
| 861 | "protect off $nor_ubootaddr1 +$filesize; " \ | |
| 862 | "erase $nor_ubootaddr1 +$filesize; " \ | |
| 863 | "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ | |
| 864 | "protect on $nor_ubootaddr1 +$filesize\0 " \ | |
| 865 | "format0=protect off $part0base +$part0size; " \ | |
| 866 | "erase $part0base +$part0size\0" \ | |
| 867 | "format1=protect off $part1base +$part1size; " \ | |
| 868 | "erase $part1base +$part1size\0" \ | |
| 869 | "format2=protect off $part2base +$part2size; " \ | |
| 870 | "erase $part2base +$part2size\0" \ | |
| 871 | "format3=protect off $part3base +$part3size; " \ | |
| 872 | "erase $part3base +$part3size\0" \ | |
| 873 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ | |
| 874 | "kerneladdr=0x01100000\0" \ | |
| 875 | "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ | |
| 876 | "kernelfile=uImage\0" \ | |
| 877 | "loadaddr=0x01000000\0" \ | |
| 878 | "mbr=uCP1020.mbr\0" \ | |
| 879 | "mbr_offset=0x00000000\0" \ | |
| 880 | "netdev=eth0\0" \ | |
| 881 | "nor_ubootaddr0=0xEC000000\0" \ | |
| 882 | "nor_ubootaddr1=0xEFF80000\0" \ | |
| 883 | "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ | |
| 884 | "run norkernelload; " \ | |
| 885 | "bootm $kerneladdr - $dtbaddr\0" \ | |
| 886 | "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ | |
| 887 | "setenv cramfsaddr $part0base; " \ | |
| 888 | "cramfsload $dtbaddr $dtbfile; " \ | |
| 889 | "cramfsload $kerneladdr $kernelfile\0" \ | |
| 890 | "part0base=0xEC100000\0" \ | |
| 891 | "part0size=0x00700000\0" \ | |
| 892 | "part1base=0xEC800000\0" \ | |
| 893 | "part1size=0x02000000\0" \ | |
| 894 | "part2base=0xEE800000\0" \ | |
| 895 | "part2size=0x00800000\0" \ | |
| 896 | "part3base=0xEF000000\0" \ | |
| 897 | "part3size=0x00F80000\0" \ | |
| 898 | "partENVbase=0xEC080000\0" \ | |
| 899 | "partENVsize=0x00080000\0" \ | |
| 900 | "program0=tftp part0-000000.bin; " \ | |
| 901 | "protect off $part0base +$filesize; " \ | |
| 902 | "erase $part0base +$filesize; " \ | |
| 903 | "cp.b $loadaddr $part0base $filesize; " \ | |
| 904 | "echo Verifying...; " \ | |
| 905 | "cmp.b $loadaddr $part0base $filesize\0" \ | |
| 906 | "program1=tftp part1-000000.bin; " \ | |
| 907 | "protect off $part1base +$filesize; " \ | |
| 908 | "erase $part1base +$filesize; " \ | |
| 909 | "cp.b $loadaddr $part1base $filesize; " \ | |
| 910 | "echo Verifying...; " \ | |
| 911 | "cmp.b $loadaddr $part1base $filesize\0" \ | |
| 912 | "program2=tftp part2-000000.bin; " \ | |
| 913 | "protect off $part2base +$filesize; " \ | |
| 914 | "erase $part2base +$filesize; " \ | |
| 915 | "cp.b $loadaddr $part2base $filesize; " \ | |
| 916 | "echo Verifying...; " \ | |
| 917 | "cmp.b $loadaddr $part2base $filesize\0" \ | |
| 918 | "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ | |
| 919 | " console=$consoledev,$baudrate $othbootargs; " \ | |
| 920 | "tftp $rootfsaddr $rootfsfile; " \ | |
| 921 | "tftp $loadaddr $kernelfile; " \ | |
| 922 | "tftp $dtbaddr $dtbfile; " \ | |
| 923 | "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ | |
| 924 | "ramdisk_size=120000\0" \ | |
| 925 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 926 | "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ | |
| 927 | "mw.l 0xffe0f008 0x00400000\0" \ | |
| 928 | "rootfsaddr=0x02F00000\0" \ | |
| 929 | "rootfsfile=rootfs.ext2.gz.uboot\0" \ | |
| 930 | "rootpath=/opt/nfsroot\0" \ | |
| 931 | "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ | |
| 932 | "sf probe 0; sf erase 0 +$filesize; " \ | |
| 933 | "sf write $loadaddr 0 $filesize\0" \ | |
| 934 | "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ | |
| 935 | "protect off 0xeC000000 +$filesize; " \ | |
| 936 | "erase 0xEC000000 +$filesize; " \ | |
| 937 | "cp.b $loadaddr 0xEC000000 $filesize; " \ | |
| 938 | "cmp.b $loadaddr 0xEC000000 $filesize; " \ | |
| 939 | "protect on 0xeC000000 +$filesize\0" \ | |
| 940 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 941 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 942 | "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 943 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ | |
| 944 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ | |
| 945 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ | |
| 946 | "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ | |
| 947 | "ubootfile=u-boot.bin\0" \ | |
| 948 | "upgrade=run flashuboot\0" \ | |
| 949 | "usb_phy_type=ulpi\0 " \ | |
| 950 | "boot_nfs= " \ | |
| 951 | "setenv bootargs root=/dev/nfs rw " \ | |
| 952 | "nfsroot=$serverip:$rootpath " \ | |
| 953 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 954 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 955 | "tftp $loadaddr $bootfile;" \ | |
| 956 | "tftp $fdtaddr $fdtfile;" \ | |
| 957 | "bootm $loadaddr - $fdtaddr\0" \ | |
| 958 | "boot_hd = " \ | |
| 959 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 960 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 961 | "usb start;" \ | |
| 962 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 963 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 964 | "bootm $loadaddr - $fdtaddr\0" \ | |
| 965 | "boot_usb_fat = " \ | |
| 966 | "setenv bootargs root=/dev/ram rw " \ | |
| 967 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 968 | "ramdisk_size=$ramdisk_size;" \ | |
| 969 | "usb start;" \ | |
| 970 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 971 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 972 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 973 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ | |
| 974 | "boot_usb_ext2 = " \ | |
| 975 | "setenv bootargs root=/dev/ram rw " \ | |
| 976 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 977 | "ramdisk_size=$ramdisk_size;" \ | |
| 978 | "usb start;" \ | |
| 979 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 980 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 981 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 982 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ | |
| 983 | "boot_nor = " \ | |
| 984 | "setenv bootargs root=/dev/$jffs2nor rw " \ | |
| 985 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
| 986 | "bootm $norbootaddr - $norfdtaddr\0 " \ | |
| 987 | "boot_ram = " \ | |
| 988 | "setenv bootargs root=/dev/ram rw " \ | |
| 989 | "console=$consoledev,$baudrate $othbootargs " \ | |
| 990 | "ramdisk_size=$ramdisk_size;" \ | |
| 991 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 992 | "tftp $loadaddr $bootfile;" \ | |
| 993 | "tftp $fdtaddr $fdtfile;" \ | |
| 994 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" | |
| 995 | ||
| 996 | #endif | |
| 997 | #endif | |
| 998 | ||
| 999 | #endif /* __CONFIG_H */ |