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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_VOH405 1 /* ...on a VOH405 board */ | |
13fdf8a6 | 39 | |
2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
41 | ||
c837dcb1 WD |
42 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
43 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 44 | |
a20b27a3 | 45 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
46 | |
47 | #define CONFIG_BAUDRATE 9600 | |
48 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
49 | ||
50 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
51 | #undef CONFIG_BOOTCOMMAND |
52 | ||
53 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
54 | ||
6d0f6bcf | 55 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 56 | |
b56bd0fc MF |
57 | #undef CONFIG_HAS_ETH1 |
58 | ||
96e21f86 | 59 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 60 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 61 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 62 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
b56bd0fc | 63 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 SR |
64 | |
65 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 66 | |
a5562901 | 67 | |
a1aa0bb5 JL |
68 | /* |
69 | * BOOTP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | ||
76 | ||
a5562901 JL |
77 | /* |
78 | * Command line configuration. | |
79 | */ | |
80 | #include <config_cmd_default.h> | |
81 | ||
82 | #define CONFIG_CMD_DHCP | |
83 | #define CONFIG_CMD_PCI | |
84 | #define CONFIG_CMD_IRQ | |
85 | #define CONFIG_CMD_IDE | |
86 | #define CONFIG_CMD_FAT | |
87 | #define CONFIG_CMD_ELF | |
88 | #define CONFIG_CMD_NAND | |
89 | #define CONFIG_CMD_DATE | |
90 | #define CONFIG_CMD_I2C | |
91 | #define CONFIG_CMD_MII | |
92 | #define CONFIG_CMD_PING | |
93 | #define CONFIG_CMD_EEPROM | |
94 | ||
13fdf8a6 SR |
95 | |
96 | #define CONFIG_MAC_PARTITION | |
97 | #define CONFIG_DOS_PARTITION | |
98 | ||
a20b27a3 SR |
99 | #define CONFIG_SUPPORT_VFAT |
100 | ||
c837dcb1 | 101 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 102 | |
c837dcb1 | 103 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 104 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 105 | |
c837dcb1 | 106 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
107 | |
108 | /* | |
109 | * Miscellaneous configurable options | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
112 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
13fdf8a6 | 113 | |
6d0f6bcf | 114 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
13fdf8a6 | 115 | |
a5562901 | 116 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 117 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 118 | #else |
6d0f6bcf | 119 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 120 | #endif |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
122 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
123 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 128 | |
a20b27a3 SR |
129 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
130 | ||
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
132 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 133 | |
550650dd SR |
134 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
135 | #define CONFIG_SYS_NS16550 | |
136 | #define CONFIG_SYS_NS16550_SERIAL | |
137 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
138 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
139 | ||
6d0f6bcf | 140 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 141 | #define CONFIG_SYS_BASE_BAUD 691200 |
13fdf8a6 SR |
142 | |
143 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
145 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
146 | 57600, 115200, 230400, 460800, 921600 } | |
147 | ||
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
149 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 SR |
152 | |
153 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
154 | ||
c837dcb1 | 155 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 156 | |
6d0f6bcf | 157 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 SR |
158 | |
159 | /*----------------------------------------------------------------------- | |
160 | * NAND-FLASH stuff | |
161 | *----------------------------------------------------------------------- | |
162 | */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
6d0f6bcf | 164 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c MF |
165 | #define NAND_BIG_DELAY_US 25 |
166 | ||
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
168 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
169 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
170 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
173 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 174 | |
13fdf8a6 SR |
175 | /*----------------------------------------------------------------------- |
176 | * PCI stuff | |
177 | *----------------------------------------------------------------------- | |
178 | */ | |
a20b27a3 SR |
179 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
180 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
181 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
182 | ||
183 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 184 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
a20b27a3 SR |
185 | #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ |
186 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
187 | /* resource configuration */ | |
188 | ||
189 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
190 | ||
191 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
192 | ||
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
194 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
195 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
196 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
197 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
198 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
199 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
200 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
201 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
13fdf8a6 SR |
202 | |
203 | /*----------------------------------------------------------------------- | |
204 | * IDE/ATA stuff | |
205 | *----------------------------------------------------------------------- | |
206 | */ | |
c837dcb1 WD |
207 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
208 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
209 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
210 | ||
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
212 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ | |
13fdf8a6 | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
215 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
216 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010 | |
13fdf8a6 | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
219 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
220 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
221 | |
222 | /* | |
223 | * For booting Linux, the board info and command line data | |
224 | * have to be in the first 8 MB of memory, since this is | |
225 | * the maximum mapped by the Linux kernel during initialization. | |
226 | */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
13fdf8a6 SR |
228 | /*----------------------------------------------------------------------- |
229 | * FLASH organization | |
230 | */ | |
231 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
232 | ||
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
234 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 235 | |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
237 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 238 | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
240 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
241 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
13fdf8a6 SR |
242 | /* |
243 | * The following defines are added for buggy IOP480 byte interface. | |
244 | * All other boards should use the standard values (CPCI405 etc.) | |
245 | */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
247 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
248 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 249 | |
6d0f6bcf | 250 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
13fdf8a6 | 251 | |
13fdf8a6 SR |
252 | /*----------------------------------------------------------------------- |
253 | * Start addresses for the final memory configuration | |
254 | * (Set up by the startup code) | |
6d0f6bcf | 255 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 256 | */ |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
258 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
14d0a02a | 259 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
261 | #define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */ | |
262 | ||
263 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
264 | # define CONFIG_SYS_RAMBOOT 1 | |
13fdf8a6 | 265 | #else |
6d0f6bcf | 266 | # undef CONFIG_SYS_RAMBOOT |
13fdf8a6 SR |
267 | #endif |
268 | ||
269 | /*----------------------------------------------------------------------- | |
270 | * Environment Variable setup | |
271 | */ | |
bb1f8b4f | 272 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
273 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
274 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
13fdf8a6 SR |
275 | /* total size of a CAT24WC16 is 2048 bytes */ |
276 | ||
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
278 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
13fdf8a6 SR |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * I2C EEPROM (CAT24WC16) for environment | |
282 | */ | |
880540de DE |
283 | #define CONFIG_SYS_I2C |
284 | #define CONFIG_SYS_I2C_PPC4XX | |
285 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
286 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 | |
287 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
13fdf8a6 | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ |
290 | #define CONFIG_SYS_EEPROM_WREN 1 | |
b56bd0fc | 291 | |
13fdf8a6 | 292 | /* CAT24WC32/64... */ |
6d0f6bcf | 293 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
c837dcb1 | 294 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
296 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ | |
13fdf8a6 | 297 | /* 32 byte page write mode using*/ |
c837dcb1 | 298 | /* last 5 bits of the address */ |
6d0f6bcf | 299 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 300 | |
13fdf8a6 SR |
301 | /*----------------------------------------------------------------------- |
302 | * External Bus Controller (EBC) Setup | |
303 | */ | |
304 | ||
c837dcb1 WD |
305 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
306 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ | |
307 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
308 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
309 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 310 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
13fdf8a6 | 311 | |
c837dcb1 | 312 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
314 | /*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
315 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 316 | |
c837dcb1 | 317 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
319 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 320 | |
c837dcb1 | 321 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
323 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
13fdf8a6 | 324 | |
c837dcb1 | 325 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
327 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 328 | |
c837dcb1 | 329 | /* Memory Bank 4 (Epson VGA) initialization */ |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */ |
331 | #define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */ | |
13fdf8a6 | 332 | |
a20b27a3 SR |
333 | /*----------------------------------------------------------------------- |
334 | * LCD Setup | |
335 | */ | |
336 | ||
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ |
338 | #define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ | |
339 | #define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */ | |
340 | #define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */ | |
a20b27a3 | 341 | |
6d0f6bcf | 342 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20) |
a20b27a3 | 343 | |
13fdf8a6 SR |
344 | /*----------------------------------------------------------------------- |
345 | * FPGA stuff | |
346 | */ | |
347 | ||
6d0f6bcf | 348 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
349 | |
350 | /* FPGA internal regs */ | |
6d0f6bcf | 351 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
352 | |
353 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
355 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
356 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 357 | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
359 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
360 | |
361 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
363 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
364 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
365 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
366 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 SR |
367 | |
368 | /*----------------------------------------------------------------------- | |
369 | * Definitions for initial stack pointer and data area (in data cache) | |
370 | */ | |
371 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
373 | |
374 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
376 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
377 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 378 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
13fdf8a6 | 379 | |
25ddd1fb | 380 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 381 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
13fdf8a6 SR |
382 | |
383 | /*----------------------------------------------------------------------- | |
384 | * Definitions for GPIO setup (PPC405EP specific) | |
385 | * | |
c837dcb1 WD |
386 | * GPIO0[0] - External Bus Controller BLAST output |
387 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
388 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
389 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
390 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
391 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
392 | * GPIO0[28-29] - UART1 data signal input/output | |
a20b27a3 | 393 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO |
13fdf8a6 | 394 | */ |
afabb498 SR |
395 | #define CONFIG_SYS_GPIO0_OSRL 0x00000550 |
396 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 | |
397 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 | |
398 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555440 | |
6d0f6bcf | 399 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
afabb498 | 400 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_GPIO0_TCR 0x777E0017 |
402 | ||
403 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) | |
404 | #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) | |
405 | #define CONFIG_SYS_IIC_ON (0x80000000 >> 8) | |
406 | #define CONFIG_SYS_LCD0_RST (0x80000000 >> 30) | |
407 | #define CONFIG_SYS_LCD1_RST (0x80000000 >> 31) | |
408 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 | 409 | |
13fdf8a6 SR |
410 | /* |
411 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
412 | * This value will be set if iic boot eprom is disabled. | |
413 | */ | |
414 | #if 1 | |
c837dcb1 WD |
415 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
416 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
417 | #endif |
418 | #if 0 | |
c837dcb1 WD |
419 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
420 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 SR |
421 | #endif |
422 | #if 0 | |
c837dcb1 WD |
423 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
424 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
425 | #endif |
426 | ||
427 | #endif /* __CONFIG_H */ |