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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a20b27a3 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
a20b27a3 SR |
11 | #ifndef __CONFIG_H |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
a20b27a3 | 18 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
a20b27a3 SR |
19 | #define CONFIG_VOM405 1 /* ...on a VOM405 board */ |
20 | ||
2ae18241 | 21 | #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 |
3c3b55d9 | 22 | #define CONFIG_DISPLAY_BOARDINFO |
2ae18241 | 23 | |
a20b27a3 SR |
24 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
25 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
26 | ||
27 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ | |
28 | ||
29 | #define CONFIG_BAUDRATE 9600 | |
30 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
31 | ||
32 | #undef CONFIG_BOOTARGS | |
33 | #undef CONFIG_BOOTCOMMAND | |
34 | ||
35 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
36 | ||
6d0f6bcf | 37 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
a20b27a3 | 38 | |
feaedfcf SR |
39 | #undef CONFIG_HAS_ETH1 |
40 | ||
96e21f86 | 41 | #define CONFIG_PPC4xx_EMAC |
a20b27a3 SR |
42 | #define CONFIG_MII 1 /* MII PHY management */ |
43 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
44 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ | |
feaedfcf | 45 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
a20b27a3 | 46 | |
37d4bb70 JL |
47 | /* |
48 | * BOOTP options | |
49 | */ | |
50 | #define CONFIG_BOOTP_SUBNETMASK | |
51 | #define CONFIG_BOOTP_GATEWAY | |
52 | #define CONFIG_BOOTP_HOSTNAME | |
53 | #define CONFIG_BOOTP_BOOTPATH | |
54 | #define CONFIG_BOOTP_DNS | |
55 | #define CONFIG_BOOTP_DNS2 | |
56 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
a20b27a3 | 57 | |
a5562901 JL |
58 | /* |
59 | * Command line configuration. | |
60 | */ | |
a5562901 JL |
61 | #define CONFIG_CMD_DHCP |
62 | #define CONFIG_CMD_BSP | |
a5562901 | 63 | #define CONFIG_CMD_IRQ |
a5562901 JL |
64 | #define CONFIG_CMD_I2C |
65 | #define CONFIG_CMD_MII | |
66 | #define CONFIG_CMD_PING | |
67 | #define CONFIG_CMD_EEPROM | |
68 | ||
a20b27a3 SR |
69 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
70 | ||
71 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
72 | ||
73 | #undef CONFIG_PRAM /* no "protected RAM" */ | |
74 | ||
75 | /* | |
76 | * Miscellaneous configurable options | |
77 | */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a20b27a3 | 79 | |
a20b27a3 | 80 | |
a5562901 | 81 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 82 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 83 | #else |
6d0f6bcf | 84 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 85 | #endif |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
87 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
88 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 89 | |
6d0f6bcf | 90 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a20b27a3 | 91 | |
6d0f6bcf | 92 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
a20b27a3 | 93 | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
95 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
a20b27a3 | 96 | |
550650dd | 97 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
98 | #define CONFIG_SYS_NS16550_SERIAL |
99 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
100 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
101 | ||
6d0f6bcf | 102 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 103 | #define CONFIG_SYS_BASE_BAUD 691200 |
a20b27a3 SR |
104 | |
105 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
a20b27a3 SR |
107 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
108 | 57600, 115200, 230400, 460800, 921600 } | |
109 | ||
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
111 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
a20b27a3 | 112 | |
1092ce21 | 113 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a20b27a3 SR |
114 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
115 | ||
116 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
117 | ||
6d0f6bcf | 118 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 | 119 | |
a20b27a3 SR |
120 | /* |
121 | * For booting Linux, the board info and command line data | |
122 | * have to be in the first 8 MB of memory, since this is | |
123 | * the maximum mapped by the Linux kernel during initialization. | |
124 | */ | |
6d0f6bcf | 125 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
1092ce21 | 126 | /* |
a20b27a3 SR |
127 | * FLASH organization |
128 | */ | |
129 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ | |
130 | ||
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
132 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
a20b27a3 | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
135 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
a20b27a3 | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
138 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
139 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
a20b27a3 SR |
140 | /* |
141 | * The following defines are added for buggy IOP480 byte interface. | |
142 | * All other boards should use the standard values (CPCI405 etc.) | |
143 | */ | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
145 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
146 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
a20b27a3 | 147 | |
6d0f6bcf | 148 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
a20b27a3 | 149 | |
1092ce21 | 150 | /* |
a20b27a3 SR |
151 | * Start addresses for the final memory configuration |
152 | * (Set up by the startup code) | |
6d0f6bcf | 153 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 154 | */ |
6d0f6bcf | 155 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
700d553f | 156 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
14d0a02a WD |
157 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
158 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
700d553f | 159 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf JCPV |
160 | |
161 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) | |
162 | # define CONFIG_SYS_RAMBOOT 1 | |
a20b27a3 | 163 | #else |
6d0f6bcf | 164 | # undef CONFIG_SYS_RAMBOOT |
a20b27a3 SR |
165 | #endif |
166 | ||
1092ce21 | 167 | /* |
a20b27a3 SR |
168 | * Environment Variable setup |
169 | */ | |
bb1f8b4f | 170 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
171 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
172 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ | |
a20b27a3 SR |
173 | /* total size of a CAT24WC16 is 2048 bytes */ |
174 | ||
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
176 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ | |
a20b27a3 | 177 | |
1092ce21 | 178 | /* |
a20b27a3 SR |
179 | * I2C EEPROM (CAT24WC16) for environment |
180 | */ | |
880540de DE |
181 | #define CONFIG_SYS_I2C |
182 | #define CONFIG_SYS_I2C_PPC4XX | |
183 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
184 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
185 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
a20b27a3 | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
188 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
a20b27a3 | 189 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
191 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
a20b27a3 SR |
192 | /* 16 byte page write mode using*/ |
193 | /* last 4 bits of the address */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
a20b27a3 | 195 | |
1092ce21 | 196 | /* |
a20b27a3 SR |
197 | * External Bus Controller (EBC) Setup |
198 | */ | |
a20b27a3 SR |
199 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
200 | ||
201 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
203 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
204 | |
205 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
207 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 | 208 | |
1092ce21 | 209 | /* |
a20b27a3 SR |
210 | * FPGA stuff |
211 | */ | |
700d553f | 212 | #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 |
a20b27a3 SR |
213 | |
214 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
216 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ | |
217 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ | |
218 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ | |
219 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ | |
a20b27a3 | 220 | |
1092ce21 | 221 | /* |
a20b27a3 SR |
222 | * Definitions for initial stack pointer and data area (in data cache) |
223 | */ | |
224 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
a20b27a3 SR |
226 | |
227 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
229 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
230 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 231 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
a20b27a3 | 232 | |
25ddd1fb | 233 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 234 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a20b27a3 | 235 | |
1092ce21 | 236 | /* |
a20b27a3 SR |
237 | * Definitions for GPIO setup (PPC405EP specific) |
238 | * | |
239 | * GPIO0[0] - External Bus Controller BLAST output | |
240 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
241 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs | |
242 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
243 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
244 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
245 | * GPIO0[28-29] - UART1 data signal input/output | |
246 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
247 | */ | |
248 | /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ | |
249 | /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ | |
250 | /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ | |
251 | /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ | |
afabb498 SR |
252 | #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ |
253 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ | |
254 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ | |
255 | #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ | |
256 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ | |
257 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ |
a20b27a3 | 259 | |
a20b27a3 SR |
260 | /* |
261 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
262 | * This value will be set if iic boot eprom is disabled. | |
263 | */ | |
a20b27a3 SR |
264 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
265 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
a20b27a3 SR |
266 | |
267 | #endif /* __CONFIG_H */ |