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ccf0fdd0 PT |
1 | /* |
2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * xpedite5370 board configuration file | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
36 | #define CONFIG_MPC8572 1 | |
37 | #define CONFIG_XPEDITE5370 1 | |
38 | #define CONFIG_SYS_BOARD_NAME "XPedite5370" | |
ccf0fdd0 | 39 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
ccf0fdd0 PT |
40 | |
41 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
42 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
43 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
44 | #define CONFIG_PCIE1 1 /* PCIE controler 1 */ | |
45 | #define CONFIG_PCIE2 1 /* PCIE controler 2 */ | |
46 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
47 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
48 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
49 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
50 | ||
48618126 PT |
51 | /* |
52 | * Multicore config | |
53 | */ | |
54 | #define CONFIG_MP | |
55 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ | |
56 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ | |
57 | ||
ccf0fdd0 PT |
58 | /* |
59 | * DDR config | |
60 | */ | |
61 | #define CONFIG_FSL_DDR2 | |
62 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
63 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
64 | #define CONFIG_DDR_SPD | |
65 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
66 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
67 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
68 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
69 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
70 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
71 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
72 | #define CONFIG_DDR_ECC | |
73 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
74 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
75 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
76 | #define CONFIG_VERY_BIG_RAM | |
77 | ||
78 | #ifndef __ASSEMBLY__ | |
79 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
80 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
81 | #endif | |
82 | ||
83 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
84 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
85 | ||
86 | /* | |
87 | * These can be toggled for performance analysis, otherwise use default. | |
88 | */ | |
89 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
90 | #define CONFIG_BTB /* toggle branch predition */ | |
91 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
92 | ||
93 | /* | |
94 | * Base addresses -- Note these are effective addresses where the | |
95 | * actual resources get mapped (not physical addresses) | |
96 | */ | |
97 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
98 | #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ | |
99 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
100 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
101 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) | |
102 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) | |
103 | ||
104 | /* | |
105 | * Diagnostics | |
106 | */ | |
107 | #define CONFIG_SYS_ALT_MEMTEST | |
108 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
109 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
110 | ||
111 | /* | |
112 | * Memory map | |
113 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
114 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
115 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
116 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
117 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
118 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
48618126 | 119 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable |
ccf0fdd0 PT |
120 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable |
121 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
122 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
123 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
124 | */ | |
125 | ||
202d9487 | 126 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
ccf0fdd0 PT |
127 | |
128 | /* | |
129 | * NAND flash configuration | |
130 | */ | |
131 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
132 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
0a6d0c63 PT |
133 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ |
134 | CONFIG_SYS_NAND_BASE2} | |
135 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
136 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
137 | #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ | |
138 | #define CONFIG_NAND_FSL_ELBC | |
ccf0fdd0 PT |
139 | |
140 | /* | |
141 | * NOR flash configuration | |
142 | */ | |
143 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
144 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
145 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
146 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
147 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
148 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
149 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
150 | #define CONFIG_FLASH_CFI_DRIVER | |
151 | #define CONFIG_SYS_FLASH_CFI | |
5ff82100 | 152 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
ccf0fdd0 PT |
153 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
154 | {0xf7f40000, 0xc0000} } | |
155 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
156 | ||
157 | /* | |
158 | * Chip select configuration | |
159 | */ | |
160 | /* NOR Flash 0 on CS0 */ | |
161 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
162 | BR_PS_16 | \ | |
163 | BR_V) | |
164 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ | |
165 | OR_GPCM_CSNT | \ | |
166 | OR_GPCM_XACS | \ | |
167 | OR_GPCM_ACS_DIV2 | \ | |
168 | OR_GPCM_SCY_8 | \ | |
169 | OR_GPCM_TRLX | \ | |
170 | OR_GPCM_EHTR | \ | |
171 | OR_GPCM_EAD) | |
172 | ||
173 | /* NOR Flash 1 on CS1 */ | |
174 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
175 | BR_PS_16 | \ | |
176 | BR_V) | |
177 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
178 | ||
179 | /* NAND flash on CS2 */ | |
180 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
181 | (2<<BR_DECC_SHIFT) | \ | |
182 | BR_PS_8 | \ | |
183 | BR_MS_FCM | \ | |
184 | BR_V) | |
185 | ||
186 | /* NAND flash on CS2 */ | |
187 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
188 | OR_FCM_PGS | \ | |
189 | OR_FCM_CSCT | \ | |
190 | OR_FCM_CST | \ | |
191 | OR_FCM_CHT | \ | |
192 | OR_FCM_SCY_1 | \ | |
193 | OR_FCM_TRLX | \ | |
194 | OR_FCM_EHTR) | |
195 | ||
196 | /* NAND flash on CS3 */ | |
197 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
198 | (2<<BR_DECC_SHIFT) | \ | |
199 | BR_PS_8 | \ | |
200 | BR_MS_FCM | \ | |
201 | BR_V) | |
202 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
203 | ||
204 | /* | |
205 | * Use L1 as initial stack | |
206 | */ | |
207 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
208 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
209 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 | |
210 | ||
211 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
212 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
213 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
214 | ||
215 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
216 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
217 | ||
218 | /* | |
219 | * Serial Port | |
220 | */ | |
221 | #define CONFIG_CONS_INDEX 1 | |
222 | #define CONFIG_SYS_NS16550 | |
223 | #define CONFIG_SYS_NS16550_SERIAL | |
224 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
225 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
226 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
227 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
228 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
229 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
230 | #define CONFIG_BAUDRATE 115200 | |
231 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
232 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
233 | ||
234 | /* | |
235 | * Use the HUSH parser | |
236 | */ | |
237 | #define CONFIG_SYS_HUSH_PARSER | |
238 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
239 | ||
240 | /* | |
241 | * Pass open firmware flat tree | |
242 | */ | |
243 | #define CONFIG_OF_LIBFDT 1 | |
244 | #define CONFIG_OF_BOARD_SETUP 1 | |
245 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
246 | ||
ccf0fdd0 PT |
247 | /* |
248 | * I2C | |
249 | */ | |
250 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
251 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
252 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
253 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
254 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
255 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
256 | #define CONFIG_I2C_MULTI_BUS | |
ccf0fdd0 PT |
257 | |
258 | /* PEX8518 slave I2C interface */ | |
259 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
260 | ||
261 | /* I2C DS1631 temperature sensor */ | |
262 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
263 | #define CONFIG_DTT_DS1621 | |
264 | #define CONFIG_DTT_SENSORS { 0 } | |
265 | ||
266 | /* I2C EEPROM - AT24C128B */ | |
267 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
268 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
269 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
270 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
271 | ||
272 | /* I2C RTC */ | |
273 | #define CONFIG_RTC_M41T11 1 | |
274 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
275 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
276 | ||
277 | /* GPIO/EEPROM/SRAM */ | |
278 | #define CONFIG_DS4510 | |
279 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
280 | ||
281 | /* GPIO */ | |
282 | #define CONFIG_PCA953X | |
283 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
284 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
285 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
286 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
287 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
288 | ||
289 | /* | |
290 | * PU = pulled high, PD = pulled low | |
291 | * I = input, O = output, IO = input/output | |
292 | */ | |
293 | /* PCA9557 @ 0x18*/ | |
294 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
295 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
296 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
297 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
298 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
299 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
300 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ | |
301 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ | |
302 | ||
303 | /* PCA9557 @ 0x1c*/ | |
304 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
305 | #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ | |
306 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
307 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
308 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
309 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
310 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
311 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
312 | ||
313 | /* PCA9557 @ 0x1e*/ | |
314 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
315 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
316 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
317 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
318 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
319 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ | |
320 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ | |
321 | ||
322 | /* PCA9557 @ 0x1f */ | |
323 | #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ | |
324 | #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ | |
325 | #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ | |
326 | #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ | |
327 | #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ | |
328 | ||
329 | /* | |
330 | * General PCI | |
331 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
332 | */ | |
333 | /* PCIE1 - VPX P1 */ | |
334 | #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 | |
335 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE | |
336 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ | |
337 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
338 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 | |
339 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
340 | ||
341 | /* PCIE2 - PEX8518 */ | |
342 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 | |
343 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE | |
344 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
345 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
346 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 | |
347 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
348 | ||
349 | /* | |
350 | * Networking options | |
351 | */ | |
352 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
353 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
354 | #define CONFIG_NET_MULTI 1 | |
355 | #define CONFIG_TSEC_TBI | |
356 | #define CONFIG_MII 1 /* MII PHY management */ | |
357 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
358 | #define CONFIG_ETHPRIME "eTSEC2" | |
359 | ||
360 | #define CONFIG_TSEC1 1 | |
361 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
362 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
363 | #define TSEC1_PHY_ADDR 1 | |
364 | #define TSEC1_PHYIDX 0 | |
365 | #define CONFIG_HAS_ETH0 | |
366 | ||
367 | #define CONFIG_TSEC2 1 | |
368 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
369 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
370 | #define TSEC2_PHY_ADDR 2 | |
371 | #define TSEC2_PHYIDX 0 | |
372 | #define CONFIG_HAS_ETH1 | |
373 | ||
374 | /* | |
375 | * Command configuration. | |
376 | */ | |
377 | #include <config_cmd_default.h> | |
378 | ||
379 | #define CONFIG_CMD_ASKENV | |
380 | #define CONFIG_CMD_DATE | |
381 | #define CONFIG_CMD_DHCP | |
382 | #define CONFIG_CMD_DS4510 | |
383 | #define CONFIG_CMD_DS4510_INFO | |
384 | #define CONFIG_CMD_DTT | |
385 | #define CONFIG_CMD_EEPROM | |
386 | #define CONFIG_CMD_ELF | |
ccf0fdd0 PT |
387 | #define CONFIG_CMD_FLASH |
388 | #define CONFIG_CMD_I2C | |
389 | #define CONFIG_CMD_JFFS2 | |
390 | #define CONFIG_CMD_MII | |
0a6d0c63 | 391 | #define CONFIG_CMD_NAND |
ccf0fdd0 PT |
392 | #define CONFIG_CMD_NET |
393 | #define CONFIG_CMD_PCA953X | |
394 | #define CONFIG_CMD_PCA953X_INFO | |
395 | #define CONFIG_CMD_PCI | |
396 | #define CONFIG_CMD_PING | |
0a6d0c63 | 397 | #define CONFIG_CMD_SAVEENV |
ccf0fdd0 PT |
398 | #define CONFIG_CMD_SNTP |
399 | ||
400 | /* | |
401 | * Miscellaneous configurable options | |
402 | */ | |
403 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
404 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
405 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
406 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
407 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
408 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
409 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
410 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
411 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
412 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ | |
413 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
414 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
415 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
416 | #define CONFIG_FIT 1 | |
417 | #define CONFIG_FIT_VERBOSE 1 | |
418 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
419 | ||
420 | /* | |
421 | * For booting Linux, the board info and command line data | |
422 | * have to be in the first 16 MB of memory, since this is | |
423 | * the maximum mapped by the Linux kernel during initialization. | |
424 | */ | |
425 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
39121c08 | 426 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
ccf0fdd0 PT |
427 | |
428 | /* | |
429 | * Boot Flags | |
430 | */ | |
431 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
432 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
433 | ||
434 | /* | |
435 | * Environment Configuration | |
436 | */ | |
437 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
438 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
439 | #define CONFIG_ENV_SIZE 0x8000 | |
440 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
441 | ||
442 | /* | |
443 | * Flash memory map: | |
444 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
445 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
446 | * fff00000 - fff3ffff Pri FDT (256KB) | |
447 | * fef00000 - ffefffff Pri OS image (16MB) | |
448 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
449 | * | |
450 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) | |
451 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) | |
452 | * f7f00000 - f7f3ffff Sec FDT (256KB) | |
453 | * f6f00000 - f7efffff Sec OS image (16MB) | |
454 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
455 | */ | |
456 | #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) | |
457 | #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000) | |
458 | #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) | |
459 | #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000) | |
460 | #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) | |
461 | #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) | |
462 | ||
463 | #define CONFIG_PROG_UBOOT1 \ | |
464 | "$download_cmd $loadaddr $ubootfile; " \ | |
465 | "if test $? -eq 0; then " \ | |
466 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
467 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
468 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
469 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
470 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
471 | "if test $? -ne 0; then " \ | |
472 | "echo PROGRAM FAILED; " \ | |
473 | "else; " \ | |
474 | "echo PROGRAM SUCCEEDED; " \ | |
475 | "fi; " \ | |
476 | "else; " \ | |
477 | "echo DOWNLOAD FAILED; " \ | |
478 | "fi;" | |
479 | ||
480 | #define CONFIG_PROG_UBOOT2 \ | |
481 | "$download_cmd $loadaddr $ubootfile; " \ | |
482 | "if test $? -eq 0; then " \ | |
483 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
484 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
485 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
486 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
487 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
488 | "if test $? -ne 0; then " \ | |
489 | "echo PROGRAM FAILED; " \ | |
490 | "else; " \ | |
491 | "echo PROGRAM SUCCEEDED; " \ | |
492 | "fi; " \ | |
493 | "else; " \ | |
494 | "echo DOWNLOAD FAILED; " \ | |
495 | "fi;" | |
496 | ||
497 | #define CONFIG_BOOT_OS_NET \ | |
498 | "$download_cmd $osaddr $osfile; " \ | |
499 | "if test $? -eq 0; then " \ | |
500 | "if test -n $fdtaddr; then " \ | |
501 | "$download_cmd $fdtaddr $fdtfile; " \ | |
502 | "if test $? -eq 0; then " \ | |
503 | "bootm $osaddr - $fdtaddr; " \ | |
504 | "else; " \ | |
505 | "echo FDT DOWNLOAD FAILED; " \ | |
506 | "fi; " \ | |
507 | "else; " \ | |
508 | "bootm $osaddr; " \ | |
509 | "fi; " \ | |
510 | "else; " \ | |
511 | "echo OS DOWNLOAD FAILED; " \ | |
512 | "fi;" | |
513 | ||
514 | #define CONFIG_PROG_OS1 \ | |
515 | "$download_cmd $osaddr $osfile; " \ | |
516 | "if test $? -eq 0; then " \ | |
517 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
518 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
519 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
520 | "if test $? -ne 0; then " \ | |
521 | "echo OS PROGRAM FAILED; " \ | |
522 | "else; " \ | |
523 | "echo OS PROGRAM SUCCEEDED; " \ | |
524 | "fi; " \ | |
525 | "else; " \ | |
526 | "echo OS DOWNLOAD FAILED; " \ | |
527 | "fi;" | |
528 | ||
529 | #define CONFIG_PROG_OS2 \ | |
530 | "$download_cmd $osaddr $osfile; " \ | |
531 | "if test $? -eq 0; then " \ | |
532 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
533 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
534 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
535 | "if test $? -ne 0; then " \ | |
536 | "echo OS PROGRAM FAILED; " \ | |
537 | "else; " \ | |
538 | "echo OS PROGRAM SUCCEEDED; " \ | |
539 | "fi; " \ | |
540 | "else; " \ | |
541 | "echo OS DOWNLOAD FAILED; " \ | |
542 | "fi;" | |
543 | ||
544 | #define CONFIG_PROG_FDT1 \ | |
545 | "$download_cmd $fdtaddr $fdtfile; " \ | |
546 | "if test $? -eq 0; then " \ | |
547 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
548 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
549 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
550 | "if test $? -ne 0; then " \ | |
551 | "echo FDT PROGRAM FAILED; " \ | |
552 | "else; " \ | |
553 | "echo FDT PROGRAM SUCCEEDED; " \ | |
554 | "fi; " \ | |
555 | "else; " \ | |
556 | "echo FDT DOWNLOAD FAILED; " \ | |
557 | "fi;" | |
558 | ||
559 | #define CONFIG_PROG_FDT2 \ | |
560 | "$download_cmd $fdtaddr $fdtfile; " \ | |
561 | "if test $? -eq 0; then " \ | |
562 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
563 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
564 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
565 | "if test $? -ne 0; then " \ | |
566 | "echo FDT PROGRAM FAILED; " \ | |
567 | "else; " \ | |
568 | "echo FDT PROGRAM SUCCEEDED; " \ | |
569 | "fi; " \ | |
570 | "else; " \ | |
571 | "echo FDT DOWNLOAD FAILED; " \ | |
572 | "fi;" | |
573 | ||
574 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
575 | "autoload=yes\0" \ | |
576 | "download_cmd=tftp\0" \ | |
577 | "console_args=console=ttyS0,115200\0" \ | |
578 | "root_args=root=/dev/nfs rw\0" \ | |
579 | "misc_args=ip=on\0" \ | |
580 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
581 | "bootfile=/home/user/file\0" \ | |
582 | "osfile=/home/user/uImage-XPedite5370\0" \ | |
583 | "fdtfile=/home/user/xpedite5370.dtb\0" \ | |
584 | "ubootfile=/home/user/u-boot.bin\0" \ | |
585 | "fdtaddr=c00000\0" \ | |
586 | "osaddr=0x1000000\0" \ | |
587 | "loadaddr=0x1000000\0" \ | |
588 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
589 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
590 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
591 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
592 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
593 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
594 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
595 | "bootcmd_flash1=run set_bootargs; " \ | |
596 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
597 | "bootcmd_flash2=run set_bootargs; " \ | |
598 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
599 | "bootcmd=run bootcmd_flash1\0" | |
600 | #endif /* __CONFIG_H */ |