projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ccf0fdd0 PT |
1 | /* |
| 2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
| 3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * xpedite5370 board configuration file | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 30 | /* | |
| 31 | * High Level Configuration Options | |
| 32 | */ | |
| 33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 36 | #define CONFIG_MPC8572 1 | |
| 37 | #define CONFIG_XPEDITE5370 1 | |
| 38 | #define CONFIG_SYS_BOARD_NAME "XPedite5370" | |
| ccf0fdd0 | 39 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
| ccf0fdd0 | 40 | |
| 2ae18241 WD |
41 | #ifndef CONFIG_SYS_TEXT_BASE |
| 42 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
| 43 | #endif | |
| 44 | ||
| ccf0fdd0 PT |
45 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 46 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
| 47 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
| 48 | #define CONFIG_PCIE1 1 /* PCIE controler 1 */ | |
| 49 | #define CONFIG_PCIE2 1 /* PCIE controler 2 */ | |
| 50 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 51 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| 52 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 53 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| 0914f483 | 54 | #define CONFIG_FSL_ELBC 1 |
| ccf0fdd0 | 55 | |
| 48618126 PT |
56 | /* |
| 57 | * Multicore config | |
| 58 | */ | |
| 59 | #define CONFIG_MP | |
| 60 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ | |
| 61 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ | |
| 62 | ||
| ccf0fdd0 PT |
63 | /* |
| 64 | * DDR config | |
| 65 | */ | |
| 66 | #define CONFIG_FSL_DDR2 | |
| 67 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 68 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 69 | #define CONFIG_DDR_SPD | |
| 70 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 71 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
| 72 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
| 73 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
| 74 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 75 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 76 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 77 | #define CONFIG_DDR_ECC | |
| 78 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 79 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 81 | #define CONFIG_VERY_BIG_RAM | |
| 82 | ||
| 83 | #ifndef __ASSEMBLY__ | |
| 84 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 85 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
| 86 | #endif | |
| 87 | ||
| 88 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
| 89 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
| 90 | ||
| 91 | /* | |
| 92 | * These can be toggled for performance analysis, otherwise use default. | |
| 93 | */ | |
| 94 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 95 | #define CONFIG_BTB /* toggle branch predition */ | |
| 96 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 97 | ||
| 98 | /* | |
| 99 | * Base addresses -- Note these are effective addresses where the | |
| 100 | * actual resources get mapped (not physical addresses) | |
| 101 | */ | |
| 102 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 103 | #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ | |
| 104 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
| 105 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
| ccf0fdd0 PT |
106 | |
| 107 | /* | |
| 108 | * Diagnostics | |
| 109 | */ | |
| 110 | #define CONFIG_SYS_ALT_MEMTEST | |
| 111 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
| 112 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
| 113 | ||
| 114 | /* | |
| 115 | * Memory map | |
| 116 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 117 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
| 118 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
| 119 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
| 120 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
| 121 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
| 48618126 | 122 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable |
| ccf0fdd0 PT |
123 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable |
| 124 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
| 125 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
| 126 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
| 127 | */ | |
| 128 | ||
| 202d9487 | 129 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
| ccf0fdd0 PT |
130 | |
| 131 | /* | |
| 132 | * NAND flash configuration | |
| 133 | */ | |
| 134 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
| 135 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
| 0a6d0c63 PT |
136 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ |
| 137 | CONFIG_SYS_NAND_BASE2} | |
| 138 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
| 139 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 140 | #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ | |
| 141 | #define CONFIG_NAND_FSL_ELBC | |
| ccf0fdd0 PT |
142 | |
| 143 | /* | |
| 144 | * NOR flash configuration | |
| 145 | */ | |
| 146 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
| 147 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
| 148 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
| 149 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 150 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 151 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 152 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 153 | #define CONFIG_FLASH_CFI_DRIVER | |
| 154 | #define CONFIG_SYS_FLASH_CFI | |
| 5ff82100 | 155 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| ccf0fdd0 PT |
156 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
| 157 | {0xf7f40000, 0xc0000} } | |
| 14d0a02a | 158 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| ccf0fdd0 PT |
159 | |
| 160 | /* | |
| 161 | * Chip select configuration | |
| 162 | */ | |
| 163 | /* NOR Flash 0 on CS0 */ | |
| 164 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
| 165 | BR_PS_16 | \ | |
| 166 | BR_V) | |
| 167 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ | |
| 168 | OR_GPCM_CSNT | \ | |
| 169 | OR_GPCM_XACS | \ | |
| 170 | OR_GPCM_ACS_DIV2 | \ | |
| 171 | OR_GPCM_SCY_8 | \ | |
| 172 | OR_GPCM_TRLX | \ | |
| 173 | OR_GPCM_EHTR | \ | |
| 174 | OR_GPCM_EAD) | |
| 175 | ||
| 176 | /* NOR Flash 1 on CS1 */ | |
| 177 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
| 178 | BR_PS_16 | \ | |
| 179 | BR_V) | |
| 180 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
| 181 | ||
| 182 | /* NAND flash on CS2 */ | |
| 183 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
| 184 | (2<<BR_DECC_SHIFT) | \ | |
| 185 | BR_PS_8 | \ | |
| 186 | BR_MS_FCM | \ | |
| 187 | BR_V) | |
| 188 | ||
| 189 | /* NAND flash on CS2 */ | |
| 190 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
| 191 | OR_FCM_PGS | \ | |
| 192 | OR_FCM_CSCT | \ | |
| 193 | OR_FCM_CST | \ | |
| 194 | OR_FCM_CHT | \ | |
| 195 | OR_FCM_SCY_1 | \ | |
| 196 | OR_FCM_TRLX | \ | |
| 197 | OR_FCM_EHTR) | |
| 198 | ||
| 199 | /* NAND flash on CS3 */ | |
| 200 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
| 201 | (2<<BR_DECC_SHIFT) | \ | |
| 202 | BR_PS_8 | \ | |
| 203 | BR_MS_FCM | \ | |
| 204 | BR_V) | |
| 205 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
| 206 | ||
| 207 | /* | |
| 208 | * Use L1 as initial stack | |
| 209 | */ | |
| 210 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 211 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
| 212 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 | |
| 213 | ||
| 214 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 215 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 216 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 217 | ||
| 218 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
| 219 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 220 | ||
| 221 | /* | |
| 222 | * Serial Port | |
| 223 | */ | |
| 224 | #define CONFIG_CONS_INDEX 1 | |
| 225 | #define CONFIG_SYS_NS16550 | |
| 226 | #define CONFIG_SYS_NS16550_SERIAL | |
| 227 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 228 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 229 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 230 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 231 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 232 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 233 | #define CONFIG_BAUDRATE 115200 | |
| 234 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 235 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 236 | ||
| 237 | /* | |
| 238 | * Use the HUSH parser | |
| 239 | */ | |
| 240 | #define CONFIG_SYS_HUSH_PARSER | |
| 241 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 242 | ||
| 243 | /* | |
| 244 | * Pass open firmware flat tree | |
| 245 | */ | |
| 246 | #define CONFIG_OF_LIBFDT 1 | |
| 247 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 248 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 249 | ||
| ccf0fdd0 PT |
250 | /* |
| 251 | * I2C | |
| 252 | */ | |
| 253 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 254 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 255 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 256 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 257 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 258 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 259 | #define CONFIG_I2C_MULTI_BUS | |
| ccf0fdd0 PT |
260 | |
| 261 | /* PEX8518 slave I2C interface */ | |
| 262 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
| 263 | ||
| 264 | /* I2C DS1631 temperature sensor */ | |
| 265 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
| 266 | #define CONFIG_DTT_DS1621 | |
| 267 | #define CONFIG_DTT_SENSORS { 0 } | |
| 268 | ||
| 269 | /* I2C EEPROM - AT24C128B */ | |
| 270 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
| 271 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 272 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
| 273 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
| 274 | ||
| 275 | /* I2C RTC */ | |
| 276 | #define CONFIG_RTC_M41T11 1 | |
| 277 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 278 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
| 279 | ||
| 280 | /* GPIO/EEPROM/SRAM */ | |
| 281 | #define CONFIG_DS4510 | |
| 282 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
| 283 | ||
| 284 | /* GPIO */ | |
| 285 | #define CONFIG_PCA953X | |
| 286 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
| 287 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
| 288 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
| 289 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
| 290 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
| 291 | ||
| 292 | /* | |
| 293 | * PU = pulled high, PD = pulled low | |
| 294 | * I = input, O = output, IO = input/output | |
| 295 | */ | |
| 296 | /* PCA9557 @ 0x18*/ | |
| 297 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
| 298 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
| 299 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
| 300 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
| 301 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
| 302 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
| 303 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ | |
| 304 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ | |
| 305 | ||
| 306 | /* PCA9557 @ 0x1c*/ | |
| 307 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
| 308 | #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ | |
| 309 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
| 310 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
| 311 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
| 312 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
| 313 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
| 314 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
| 315 | ||
| 316 | /* PCA9557 @ 0x1e*/ | |
| 317 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
| 318 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
| 319 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
| 320 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
| 321 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
| 322 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ | |
| 323 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ | |
| 324 | ||
| 325 | /* PCA9557 @ 0x1f */ | |
| 326 | #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ | |
| 327 | #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ | |
| 328 | #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ | |
| 329 | #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ | |
| 330 | #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ | |
| 331 | ||
| 332 | /* | |
| 333 | * General PCI | |
| 334 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 335 | */ | |
| 336 | /* PCIE1 - VPX P1 */ | |
| 337 | #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 | |
| 338 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE | |
| 339 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ | |
| 340 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
| 341 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 | |
| 342 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
| 343 | ||
| 344 | /* PCIE2 - PEX8518 */ | |
| 345 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 | |
| 346 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE | |
| 347 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 348 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
| 349 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 | |
| 350 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
| 351 | ||
| 352 | /* | |
| 353 | * Networking options | |
| 354 | */ | |
| 355 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 356 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 357 | #define CONFIG_NET_MULTI 1 | |
| 358 | #define CONFIG_TSEC_TBI | |
| 359 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 360 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 361 | #define CONFIG_ETHPRIME "eTSEC2" | |
| 362 | ||
| 363 | #define CONFIG_TSEC1 1 | |
| 364 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 365 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 366 | #define TSEC1_PHY_ADDR 1 | |
| 367 | #define TSEC1_PHYIDX 0 | |
| 368 | #define CONFIG_HAS_ETH0 | |
| 369 | ||
| 370 | #define CONFIG_TSEC2 1 | |
| 371 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 372 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 373 | #define TSEC2_PHY_ADDR 2 | |
| 374 | #define TSEC2_PHYIDX 0 | |
| 375 | #define CONFIG_HAS_ETH1 | |
| 376 | ||
| 377 | /* | |
| 378 | * Command configuration. | |
| 379 | */ | |
| 380 | #include <config_cmd_default.h> | |
| 381 | ||
| 382 | #define CONFIG_CMD_ASKENV | |
| 383 | #define CONFIG_CMD_DATE | |
| 384 | #define CONFIG_CMD_DHCP | |
| 385 | #define CONFIG_CMD_DS4510 | |
| 386 | #define CONFIG_CMD_DS4510_INFO | |
| 387 | #define CONFIG_CMD_DTT | |
| 388 | #define CONFIG_CMD_EEPROM | |
| 389 | #define CONFIG_CMD_ELF | |
| ccf0fdd0 PT |
390 | #define CONFIG_CMD_FLASH |
| 391 | #define CONFIG_CMD_I2C | |
| 392 | #define CONFIG_CMD_JFFS2 | |
| 393 | #define CONFIG_CMD_MII | |
| 0a6d0c63 | 394 | #define CONFIG_CMD_NAND |
| ccf0fdd0 PT |
395 | #define CONFIG_CMD_NET |
| 396 | #define CONFIG_CMD_PCA953X | |
| 397 | #define CONFIG_CMD_PCA953X_INFO | |
| 398 | #define CONFIG_CMD_PCI | |
| 399 | #define CONFIG_CMD_PING | |
| 0a6d0c63 | 400 | #define CONFIG_CMD_SAVEENV |
| ccf0fdd0 | 401 | #define CONFIG_CMD_SNTP |
| 199e262e | 402 | #define CONFIG_CMD_REGINFO |
| ccf0fdd0 PT |
403 | |
| 404 | /* | |
| 405 | * Miscellaneous configurable options | |
| 406 | */ | |
| 407 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 408 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 409 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 410 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 411 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 412 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 413 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 414 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 415 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 5be58f5f | 416 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| ccf0fdd0 PT |
417 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
| 418 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
| 419 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 420 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
| 421 | #define CONFIG_FIT 1 | |
| 422 | #define CONFIG_FIT_VERBOSE 1 | |
| 423 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
| 424 | ||
| 425 | /* | |
| 426 | * For booting Linux, the board info and command line data | |
| 427 | * have to be in the first 16 MB of memory, since this is | |
| 428 | * the maximum mapped by the Linux kernel during initialization. | |
| 429 | */ | |
| 430 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
| 39121c08 | 431 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
| ccf0fdd0 | 432 | |
| ccf0fdd0 PT |
433 | /* |
| 434 | * Environment Configuration | |
| 435 | */ | |
| 436 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 437 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
| 438 | #define CONFIG_ENV_SIZE 0x8000 | |
| 439 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
| 440 | ||
| 441 | /* | |
| 442 | * Flash memory map: | |
| 443 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
| 444 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
| 445 | * fff00000 - fff3ffff Pri FDT (256KB) | |
| 446 | * fef00000 - ffefffff Pri OS image (16MB) | |
| 447 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
| 448 | * | |
| 449 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) | |
| 450 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) | |
| 451 | * f7f00000 - f7f3ffff Sec FDT (256KB) | |
| 452 | * f6f00000 - f7efffff Sec OS image (16MB) | |
| 453 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
| 454 | */ | |
| 455 | #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) | |
| 456 | #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000) | |
| 457 | #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) | |
| 458 | #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000) | |
| 459 | #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) | |
| 460 | #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) | |
| 461 | ||
| 462 | #define CONFIG_PROG_UBOOT1 \ | |
| 463 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 464 | "if test $? -eq 0; then " \ | |
| 465 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 466 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 467 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
| 468 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 469 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
| 470 | "if test $? -ne 0; then " \ | |
| 471 | "echo PROGRAM FAILED; " \ | |
| 472 | "else; " \ | |
| 473 | "echo PROGRAM SUCCEEDED; " \ | |
| 474 | "fi; " \ | |
| 475 | "else; " \ | |
| 476 | "echo DOWNLOAD FAILED; " \ | |
| 477 | "fi;" | |
| 478 | ||
| 479 | #define CONFIG_PROG_UBOOT2 \ | |
| 480 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 481 | "if test $? -eq 0; then " \ | |
| 482 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 483 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 484 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
| 485 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 486 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
| 487 | "if test $? -ne 0; then " \ | |
| 488 | "echo PROGRAM FAILED; " \ | |
| 489 | "else; " \ | |
| 490 | "echo PROGRAM SUCCEEDED; " \ | |
| 491 | "fi; " \ | |
| 492 | "else; " \ | |
| 493 | "echo DOWNLOAD FAILED; " \ | |
| 494 | "fi;" | |
| 495 | ||
| 496 | #define CONFIG_BOOT_OS_NET \ | |
| 497 | "$download_cmd $osaddr $osfile; " \ | |
| 498 | "if test $? -eq 0; then " \ | |
| 499 | "if test -n $fdtaddr; then " \ | |
| 500 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 501 | "if test $? -eq 0; then " \ | |
| 502 | "bootm $osaddr - $fdtaddr; " \ | |
| 503 | "else; " \ | |
| 504 | "echo FDT DOWNLOAD FAILED; " \ | |
| 505 | "fi; " \ | |
| 506 | "else; " \ | |
| 507 | "bootm $osaddr; " \ | |
| 508 | "fi; " \ | |
| 509 | "else; " \ | |
| 510 | "echo OS DOWNLOAD FAILED; " \ | |
| 511 | "fi;" | |
| 512 | ||
| 513 | #define CONFIG_PROG_OS1 \ | |
| 514 | "$download_cmd $osaddr $osfile; " \ | |
| 515 | "if test $? -eq 0; then " \ | |
| 516 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
| 517 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 518 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 519 | "if test $? -ne 0; then " \ | |
| 520 | "echo OS PROGRAM FAILED; " \ | |
| 521 | "else; " \ | |
| 522 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 523 | "fi; " \ | |
| 524 | "else; " \ | |
| 525 | "echo OS DOWNLOAD FAILED; " \ | |
| 526 | "fi;" | |
| 527 | ||
| 528 | #define CONFIG_PROG_OS2 \ | |
| 529 | "$download_cmd $osaddr $osfile; " \ | |
| 530 | "if test $? -eq 0; then " \ | |
| 531 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
| 532 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 533 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 534 | "if test $? -ne 0; then " \ | |
| 535 | "echo OS PROGRAM FAILED; " \ | |
| 536 | "else; " \ | |
| 537 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 538 | "fi; " \ | |
| 539 | "else; " \ | |
| 540 | "echo OS DOWNLOAD FAILED; " \ | |
| 541 | "fi;" | |
| 542 | ||
| 543 | #define CONFIG_PROG_FDT1 \ | |
| 544 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 545 | "if test $? -eq 0; then " \ | |
| 546 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
| 547 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 548 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 549 | "if test $? -ne 0; then " \ | |
| 550 | "echo FDT PROGRAM FAILED; " \ | |
| 551 | "else; " \ | |
| 552 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 553 | "fi; " \ | |
| 554 | "else; " \ | |
| 555 | "echo FDT DOWNLOAD FAILED; " \ | |
| 556 | "fi;" | |
| 557 | ||
| 558 | #define CONFIG_PROG_FDT2 \ | |
| 559 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 560 | "if test $? -eq 0; then " \ | |
| 561 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
| 562 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 563 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 564 | "if test $? -ne 0; then " \ | |
| 565 | "echo FDT PROGRAM FAILED; " \ | |
| 566 | "else; " \ | |
| 567 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 568 | "fi; " \ | |
| 569 | "else; " \ | |
| 570 | "echo FDT DOWNLOAD FAILED; " \ | |
| 571 | "fi;" | |
| 572 | ||
| 573 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 574 | "autoload=yes\0" \ | |
| 575 | "download_cmd=tftp\0" \ | |
| 576 | "console_args=console=ttyS0,115200\0" \ | |
| 577 | "root_args=root=/dev/nfs rw\0" \ | |
| 578 | "misc_args=ip=on\0" \ | |
| 579 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
| 580 | "bootfile=/home/user/file\0" \ | |
| 581 | "osfile=/home/user/uImage-XPedite5370\0" \ | |
| 582 | "fdtfile=/home/user/xpedite5370.dtb\0" \ | |
| 583 | "ubootfile=/home/user/u-boot.bin\0" \ | |
| 584 | "fdtaddr=c00000\0" \ | |
| 585 | "osaddr=0x1000000\0" \ | |
| 586 | "loadaddr=0x1000000\0" \ | |
| 587 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
| 588 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
| 589 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
| 590 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
| 591 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
| 592 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
| 593 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
| 594 | "bootcmd_flash1=run set_bootargs; " \ | |
| 595 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
| 596 | "bootcmd_flash2=run set_bootargs; " \ | |
| 597 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
| 598 | "bootcmd=run bootcmd_flash1\0" | |
| 599 | #endif /* __CONFIG_H */ |