[people/ms/u-boot.git] / include / configs / a3m071.h

/*
 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_A3M071			/* A3M071 board */

#define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */

#define CONFIG_SPL_TARGET	"u-boot-img.bin"

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */

#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LOWBOOT		/* Enable lowboot	*/

#ifdef CONFIG_A4M2K
#define CONFIG_HOSTNAME		a4m2k
#else
#define CONFIG_HOSTNAME		a3m071
#endif

#define CONFIG_BOOTCOUNT_LIMIT

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	    /* console is on PSC1 */
#define CONFIG_SYS_BAUDRATE_TABLE		\
	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Command line configuration.
 */
#define CONFIG_CMD_REGINFO
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_MAY_FAIL
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_NET_RETRY_COUNT 3
#define CONFIG_NETCONSOLE
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS	/* needed for UBI */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT          "nor0=fc000000.flash"
#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:512k(u-boot),"	\
						"128k(env1),"	\
						"128k(env2),"	\
						"128k(hwinfo),"	\
						"1M(nvramsim),"	\
						"128k(dtb),"	\
						"5M(kernel),"	\
						"128k(sysinfo),"	\
						"7552k(root),"	\
						"4M(app),"	\
						"5376k(data),"	\
						"8M(install)"

#define CONFIG_LZO			/* needed for UBI */
#define CONFIG_RBTREE			/* needed for UBI */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_UBIFS

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
/* define for 66MHz speed - undef for 33MHz PCI clock speed */
#ifdef CONFIG_A4M2K
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
#else
#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
#endif

/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE	8192

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xfc000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x80000)

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500
#define CONFIG_SYS_FLASH_LOCK_TOUT	5
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_FLASH_VERIFY

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR			0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR		0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
#ifdef CONFIG_A4M2K
#define CONFIG_PHY_ADDR			0x01
#else
#define CONFIG_PHY_ADDR			0x00
#endif

/*
 * GPIO configuration
 */

/*
 * GPIO-config depends on failsave-level
 * failsave 0 means just MPX-config, no digiboard, no fpga
 *          1 means digiboard ok
 *          2 means fpga ok
 */

#ifdef CONFIG_A4M2K
#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C805
#else
/* for failsave-level 0 - full failsave */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C005
/* for failsave-level 1 - only digiboard ok */
#define CONFIG_SYS_GPS_PORT_CONFIG_1	0x1005C065
/* for failsave-level 2 - all ok */
#define CONFIG_SYS_GPS_PORT_CONFIG_2	0x1005C065
#endif

#define CONFIG_WDOG_GPIO_PIN		GPIO_WKUP_7
#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_HW_WATCHDOG		/* Use external HW-Watchdog	*/
#endif

/*
 * Configuration matrix
 *                        MSB                            LSB
 * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
 * failsave 1  0x1005C065  00010000000001011100000001100101  ( digib.-ver ok )
 * failsave 2  0x1005C065  00010000000001011100000001100101  ( all ok )
 *                         || ||| ||  |   ||| |   |   |   |
 *                         || ||| ||  |   ||| |   |   |   |  bit rev name
 *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
 *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
 *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
 *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
 *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
 *                              +-++--+---+++-+---+---+---+-  5   26 CS6
 *                                ||  |   ||| |   |   |   |   6   25 ATA
 *                                ++--+---+++-+---+---+---+-  7   24 ATA
 *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
 *                                    |   ||| |   |   |   |   9   22 IRDA
 *                                    |   ||| |   |   |   |  10   21 IRDA
 *                                    +---+++-+---+---+---+- 11   20 IRDA
 *                                        ||| |   |   |   |  12   19 Ether
 *                                        ||| |   |   |   |  13   18 Ether
 *                                        ||| |   |   |   |  14   17 Ether
 *                                        +++-+---+---+---+- 15   16 Ether
 *                                         ++-+---+---+---+- 16   15 PCI_DIS
 *                                          +-+---+---+---+- 17   14 USB_SE
 *                                            |   |   |   |  18   13 USB
 *                                            +---+---+---+- 19   12 USB
 *                                                |   |   |  20   11 PSC3
 *                                                |   |   |  21   10 PSC3
 *                                                |   |   |  22    9 PSC3
 *                                                +---+---+- 23    8 PSC3
 *                                                    |   |  24    7 -
 *                                                    |   |  25    6 PSC2
 *                                                    |   |  26    5 PSC2
 *                                                    +---+- 27    4 PSC2
 *                                                        |  28    3 -
 *                                                        |  29    2 PSC1
 *                                                        |  30    1 PSC1
 *                                                        +- 31    0 PSC1
 */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP

#define CONFIG_CMDLINE_EDITING

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024
#else
#define CONFIG_SYS_CBSIZE		256
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00100000
#define CONFIG_SYS_MEMTEST_END		0x00f00000

#define CONFIG_SYS_LOAD_ADDR		0x00100000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#ifdef CONFIG_A4M2K
/* external MRAM */
#define CONFIG_SYS_CS1_START		0xf1000000
#define CONFIG_SYS_CS1_SIZE		(512 << 10)	/* 512KiB MRAM */
#endif

#define CONFIG_SYS_CS2_START		0xe0000000
#define CONFIG_SYS_CS2_SIZE		0x00100000

/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
#define CONFIG_SYS_CS3_START		0xE9000000
#ifdef CONFIG_A4M2K
#define CONFIG_SYS_CS3_SIZE		0x00100000
#else
#define CONFIG_SYS_CS3_SIZE		0x00080000
#endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
#define CONFIG_SYS_CS3_CFG		0x0032B900

#ifndef CONFIG_A4M2K
/* Diagnosis Interface - see ticket #63 */
#define CONFIG_SYS_CS4_START		0xEA000000
#define CONFIG_SYS_CS4_SIZE		0x00000001
/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
#define CONFIG_SYS_CS4_CFG		0x0002B900
#endif

/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
#define CONFIG_SYS_CS5_START		0xE8000000
#ifdef CONFIG_A4M2K
#define CONFIG_SYS_CS5_SIZE		0x00100000
#else
#define CONFIG_SYS_CS5_SIZE		0x00010000
#endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
#define CONFIG_SYS_CS5_CFG		0x0032B900

#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for pci_clk  = 66 MHz */
#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
#define CONFIG_SYS_CS1_CFG		0x0008FD00
#define CONFIG_SYS_CS2_CFG		0x0006F90C
#else	/* for pci_clk = 33 MHz */
#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
#define CONFIG_SYS_CS1_CFG		0x0001FB00
#define CONFIG_SYS_CS2_CFG		0x0002F90C
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
/* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
#define CONFIG_SYS_CS_DEADCYCLE		0x33030000

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * Environment Configuration
 */

#undef  CONFIG_BOOTARGS

#define CONFIG_SYS_AUTOLOAD	"n"

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_SYS_FDT_BASE	0xfc1e0000
#define CONFIG_SYS_FDT_SIZE	(16<<10)

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"verify=no\0"							\
	"loadaddr=200000\0"						\
	"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0"		\
	"kernel_addr_r=1000000\0"					\
	"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0"		\
	"fdt_addr_r=1800000\0"						\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"fdtfile=" __stringify(CONFIG_HOSTNAME) "/"			\
		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
	"rootpath=/opt/eldk-5.2.1/powerpc/"				\
		"core-image-minimal-mtdutils-dropbear-generic\0"	\
	"consoledev=ttyPSC0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"mtdargs=setenv bootargs root=/dev/mtdblock8 "			\
		"rootfstype=squashfs,jffs2\0"				\
	"addhost=setenv bootargs ${bootargs} "				\
		"hostname=${hostname}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consoledev},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addtty addmtd addhost;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_mtd=run mtdargs addip addtty addmtd addhost;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self=run ramargs addip addtty addmtd addhost;"		\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty addmtd addhost;"		\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME)		\
		"/u-boot-img.bin\0"					\
	"update=protect off fc000000 fc07ffff;"				\
		"era fc000000 fc07ffff;"				\
		"cp.b ${loadaddr} fc000000 ${filesize}\0"		\
	"upd=run load;run update\0"					\
	"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;"			\
		"run mtdargs addip addtty addmtd addhost;"		\
		"fdt addr 1800000;fdt boardsetup;fdt chosen;"		\
		"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000"	\
	"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;"		\
		"erase fc200000 fc6fffff;"				\
		"cp.b 1000000 fc200000 ${filesize}"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"mtdids=" MTDIDS_DEFAULT "\0"					\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_mtd"

/*
 * SPL related defines
 */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE	0xfc000000

/* Place BSS for SPL near end of SDRAM */
#define CONFIG_SPL_BSS_START_ADDR	((128 - 1) << 20)
#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)

/* Place patched DT blob (fdt) at this address */
#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000

/* Settings for real U-Boot to be loaded from NOR flash */
#ifndef __ASSEMBLY__
extern char __spl_flash_end[];
#endif
#define CONFIG_SYS_UBOOT_BASE		__spl_flash_end
#define CONFIG_SYS_SPL_MAX_LEN		(32 << 10)
#define CONFIG_SYS_UBOOT_START		0x1000100

#endif /* __CONFIG_H */
Commit	Line	Data
13b4f639	1	/*
8aa34499	2	* Copyright 2012-2013 Stefan Roese <sr@denx.de>
13b4f639	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
13b4f639 SR	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
	10	/*
	11	* High Level Configuration Options
	12	* (easy to change)
	13	*/
	14
	15	#define CONFIG_MPC5200
b2a6dfe4	16	#define CONFIG_A3M071 /* A3M071 board */
13b4f639 SR	17
	18	#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
	19
d4451d35 SR	20	#define CONFIG_SPL_TARGET "u-boot-img.bin"
d4451d35 SR	21
13b4f639 SR	22	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
	23
	24	#define CONFIG_MISC_INIT_R
	25	#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
	26
d4451d35 SR	27	#ifdef CONFIG_A4M2K
	28	#define CONFIG_HOSTNAME a4m2k
	29	#else
	30	#define CONFIG_HOSTNAME a3m071
	31	#endif
	32
d62a89bd SR	33	#define CONFIG_BOOTCOUNT_LIMIT
d62a89bd SR	34
13b4f639 SR	35	/*
	36	* Serial console configuration
	37	*/
	38	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
13b4f639 SR	39	#define CONFIG_SYS_BAUDRATE_TABLE \
	40	{ 9600, 19200, 38400, 57600, 115200, 230400 }
	41
	42	/*
	43	* Command line configuration.
	44	*/
13b4f639	45	#define CONFIG_CMD_REGINFO
8aa34499 SR	46	#define CONFIG_BOOTP_SEND_HOSTNAME
	47	#define CONFIG_BOOTP_SERVERIP
	48	#define CONFIG_BOOTP_MAY_FAIL
	49	#define CONFIG_BOOTP_BOOTPATH
	50	#define CONFIG_BOOTP_GATEWAY
	51	#define CONFIG_BOOTP_SERVERIP
	52	#define CONFIG_NET_RETRY_COUNT 3
8aa34499	53	#define CONFIG_NETCONSOLE
8aa34499 SR	54	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	55	#define CONFIG_MTD_PARTITIONS /* needed for UBI */
	56	#define CONFIG_FLASH_CFI_MTD
	57	#define MTDIDS_DEFAULT "nor0=fc000000.flash"
	58	#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
d62a89bd SR	59	"128k(env1)," \
d62a89bd SR	60	"128k(env2)," \
8aa34499 SR	61	"128k(hwinfo)," \
	62	"1M(nvramsim)," \
	63	"128k(dtb)," \
	64	"5M(kernel)," \
	65	"128k(sysinfo)," \
	66	"7552k(root)," \
	67	"4M(app)," \
d62a89bd SR	68	"5376k(data)," \
	69	"8M(install)"
	70
8aa34499 SR	71	#define CONFIG_LZO /* needed for UBI */
	72	#define CONFIG_RBTREE /* needed for UBI */
	73	#define CONFIG_CMD_MTDPARTS
8aa34499	74	#define CONFIG_CMD_UBIFS
13b4f639 SR	75
	76	/*
	77	* IPB Bus clocking configuration.
	78	*/
	79	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	80	/* define for 66MHz speed - undef for 33MHz PCI clock speed */
d4451d35 SR	81	#ifdef CONFIG_A4M2K
	82	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
	83	#else
13b4f639	84	#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
d4451d35	85	#endif
13b4f639	86
13b4f639 SR	87	/* maximum size of the flat tree (8K) */
	88	#define OF_FLAT_TREE_MAX_SIZE 8192
	89
	90	#define OF_CPU "PowerPC,5200@0"
	91	#define OF_SOC "soc5200@f0000000"
	92	#define OF_TBCLK (bd->bi_busfreq / 4)
	93	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	94
13b4f639 SR	95	/*
	96	* NOR flash configuration
	97	*/
	98	#define CONFIG_SYS_FLASH_BASE 0xfc000000
d4451d35	99	#define CONFIG_SYS_FLASH_SIZE 0x02000000
8aa34499	100	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
13b4f639 SR	101
	102	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	103	#define CONFIG_SYS_MAX_FLASH_SECT 256
	104	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	105	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	106	#define CONFIG_SYS_FLASH_LOCK_TOUT 5
	107	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
	108	#define CONFIG_SYS_FLASH_PROTECTION
	109	#define CONFIG_FLASH_CFI_DRIVER
	110	#define CONFIG_SYS_FLASH_CFI
	111	#define CONFIG_SYS_FLASH_EMPTY_INFO
	112	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
f8945518	113	#define CONFIG_FLASH_VERIFY
13b4f639 SR	114
	115	/*
	116	* Environment settings
	117	*/
	118	#define CONFIG_ENV_IS_IN_FLASH
	119	#define CONFIG_ENV_SIZE 0x10000
	120	#define CONFIG_ENV_SECT_SIZE 0x20000
	121	#define CONFIG_ENV_OVERWRITE
8aa34499 SR	122	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
8aa34499 SR	123	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
13b4f639 SR	124
	125	/*
	126	* Memory map
	127	*/
	128	#define CONFIG_SYS_MBAR 0xf0000000
	129	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	130	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	131
	132	/* Use SRAM until RAM will be available */
	133	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
b39d1213	134	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
13b4f639	135
b39d1213	136	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
704afcc4	137	GENERATED_GBL_DATA_SIZE)
13b4f639 SR	138	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	139
	140	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	141
8aa34499 SR	142	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
8aa34499 SR	143	#define CONFIG_SYS_MALLOC_LEN (4 << 20)
13b4f639 SR	144	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	145
	146	/*
	147	* Ethernet configuration
	148	*/
	149	#define CONFIG_MPC5xxx_FEC
	150	#define CONFIG_MPC5xxx_FEC_MII100
d4451d35 SR	151	#ifdef CONFIG_A4M2K
	152	#define CONFIG_PHY_ADDR 0x01
	153	#else
13b4f639	154	#define CONFIG_PHY_ADDR 0x00
d4451d35	155	#endif
13b4f639 SR	156
	157	/*
	158	* GPIO configuration
	159	*/
	160
	161	/*
	162	* GPIO-config depends on failsave-level
	163	* failsave 0 means just MPX-config, no digiboard, no fpga
	164	* 1 means digiboard ok
	165	* 2 means fpga ok
	166	*/
	167
d4451d35	168	#ifdef CONFIG_A4M2K
8aa34499	169	#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
d4451d35	170	#else
13b4f639 SR	171	/* for failsave-level 0 - full failsave */
	172	#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
	173	/* for failsave-level 1 - only digiboard ok */
8aa34499	174	#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
13b4f639	175	/* for failsave-level 2 - all ok */
8aa34499	176	#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
d4451d35	177	#endif
13b4f639	178
aed75484 SR	179	#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
	180	#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
	181	#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
	182	#endif
	183
13b4f639 SR	184	/*
13b4f639 SR	185	* Configuration matrix
8aa34499	186	* MSB LSB
d4451d35	187	* failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
8aa34499 SR	188	* failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
8aa34499 SR	189	* failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
13b4f639 SR	190	* \|\| \|\|\| \|\| \| \|\|\| \| \| \| \|
	191	* \|\| \|\|\| \|\| \| \|\|\| \| \| \| \| bit rev name
	192	* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
	193	* +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
	194	* \|\|\| \|\| \| \|\|\| \| \| \| \| 2 29 ALTs
	195	* +++-++--+---+++-+---+---+---+- 3 28 ALTs
	196	* ++-++--+---+++-+---+---+---+- 4 27 CS7
	197	* +-++--+---+++-+---+---+---+- 5 26 CS6
	198	* \|\| \| \|\|\| \| \| \| \| 6 25 ATA
	199	* ++--+---+++-+---+---+---+- 7 24 ATA
	200	* +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
	201	* \| \|\|\| \| \| \| \| 9 22 IRDA
	202	* \| \|\|\| \| \| \| \| 10 21 IRDA
	203	* +---+++-+---+---+---+- 11 20 IRDA
	204	* \|\|\| \| \| \| \| 12 19 Ether
	205	* \|\|\| \| \| \| \| 13 18 Ether
	206	* \|\|\| \| \| \| \| 14 17 Ether
	207	* +++-+---+---+---+- 15 16 Ether
	208	* ++-+---+---+---+- 16 15 PCI_DIS
	209	* +-+---+---+---+- 17 14 USB_SE
	210	* \| \| \| \| 18 13 USB
	211	* +---+---+---+- 19 12 USB
	212	* \| \| \| 20 11 PSC3
	213	* \| \| \| 21 10 PSC3
	214	* \| \| \| 22 9 PSC3
	215	* +---+---+- 23 8 PSC3
	216	* \| \| 24 7 -
	217	* \| \| 25 6 PSC2
	218	* \| \| 26 5 PSC2
	219	* +---+- 27 4 PSC2
	220	* \| 28 3 -
	221	* \| 29 2 PSC1
	222	* \| 30 1 PSC1
	223	* +- 31 0 PSC1
	224	*/
	225
13b4f639 SR	226	/*
	227	* Miscellaneous configurable options
	228	*/
	229	#define CONFIG_SYS_LONGHELP
13b4f639 SR	230
13b4f639 SR	231	#define CONFIG_CMDLINE_EDITING
13b4f639 SR	232
	233	#if defined(CONFIG_CMD_KGDB)
	234	#define CONFIG_SYS_CBSIZE 1024
	235	#else
	236	#define CONFIG_SYS_CBSIZE 256
	237	#endif
	238	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	239	#define CONFIG_SYS_MAXARGS 16
	240	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	241
	242	#define CONFIG_SYS_MEMTEST_START 0x00100000
	243	#define CONFIG_SYS_MEMTEST_END 0x00f00000
	244
	245	#define CONFIG_SYS_LOAD_ADDR 0x00100000
	246
13b4f639 SR	247	/*
	248	* Various low-level settings
	249	*/
	250	#define CONFIG_SYS_HID0_INIT (HID0_ICE \| HID0_ICFI)
	251	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	252
	253	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	254	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	255	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	256	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
d4451d35 SR	257
	258	#ifdef CONFIG_A4M2K
	259	/* external MRAM */
	260	#define CONFIG_SYS_CS1_START 0xf1000000
	261	#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
	262	#endif
	263
13b4f639 SR	264	#define CONFIG_SYS_CS2_START 0xe0000000
	265	#define CONFIG_SYS_CS2_SIZE 0x00100000
	266
d4451d35	267	/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
13b4f639	268	#define CONFIG_SYS_CS3_START 0xE9000000
d4451d35 SR	269	#ifdef CONFIG_A4M2K
	270	#define CONFIG_SYS_CS3_SIZE 0x00100000
	271	#else
13b4f639	272	#define CONFIG_SYS_CS3_SIZE 0x00080000
d4451d35	273	#endif
13b4f639 SR	274	/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
	275	#define CONFIG_SYS_CS3_CFG 0x0032B900
	276
d4451d35	277	#ifndef CONFIG_A4M2K
13b4f639 SR	278	/* Diagnosis Interface - see ticket #63 */
	279	#define CONFIG_SYS_CS4_START 0xEA000000
	280	#define CONFIG_SYS_CS4_SIZE 0x00000001
	281	/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
	282	#define CONFIG_SYS_CS4_CFG 0x0002B900
d4451d35	283	#endif
13b4f639	284
d4451d35	285	/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
13b4f639	286	#define CONFIG_SYS_CS5_START 0xE8000000
d4451d35 SR	287	#ifdef CONFIG_A4M2K
	288	#define CONFIG_SYS_CS5_SIZE 0x00100000
	289	#else
13b4f639	290	#define CONFIG_SYS_CS5_SIZE 0x00010000
d4451d35	291	#endif
13b4f639 SR	292	/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
	293	#define CONFIG_SYS_CS5_CFG 0x0032B900
	294
	295	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
	296	#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
d4451d35	297	#define CONFIG_SYS_CS1_CFG 0x0008FD00
13b4f639 SR	298	#define CONFIG_SYS_CS2_CFG 0x0006F90C
	299	#else /* for pci_clk = 33 MHz */
	300	#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
	301	#define CONFIG_SYS_CS1_CFG 0x0001FB00
	302	#define CONFIG_SYS_CS2_CFG 0x0002F90C
	303	#endif
	304
	305	#define CONFIG_SYS_CS_BURST 0x00000000
	306	/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
	307	/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
	308	/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
	309	#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
	310
	311	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
	312
	313	/*
	314	* Environment Configuration
	315	*/
	316
13b4f639	317	#undef CONFIG_BOOTARGS
13b4f639	318
8aa34499 SR	319	#define CONFIG_SYS_AUTOLOAD "n"
8aa34499 SR	320
13b4f639 SR	321	#define CONFIG_PREBOOT "echo;" \
	322	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
	323	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
	324	"echo"
	325
	326	#undef CONFIG_BOOTARGS
	327
8aa34499	328	#define CONFIG_SYS_FDT_BASE 0xfc1e0000
5aa79f26	329	#define CONFIG_SYS_FDT_SIZE (16<<10)
13b4f639	330
13b4f639 SR	331	#define CONFIG_EXTRA_ENV_SETTINGS \
	332	"netdev=eth0\0" \
	333	"verify=no\0" \
d4451d35 SR	334	"loadaddr=200000\0" \
	335	"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
	336	"kernel_addr_r=1000000\0" \
	337	"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
	338	"fdt_addr_r=1800000\0" \
	339	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
	340	"fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
	341	__stringify(CONFIG_HOSTNAME) ".dtb\0" \
	342	"rootpath=/opt/eldk-5.2.1/powerpc/" \
	343	"core-image-minimal-mtdutils-dropbear-generic\0" \
13b4f639 SR	344	"consoledev=ttyPSC0\0" \
	345	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	346	"nfsroot=${serverip}:${rootpath}\0" \
	347	"ramargs=setenv bootargs root=/dev/ram rw\0" \
d62a89bd	348	"mtdargs=setenv bootargs root=/dev/mtdblock8 " \
8aa34499 SR	349	"rootfstype=squashfs,jffs2\0" \
	350	"addhost=setenv bootargs ${bootargs} " \
	351	"hostname=${hostname}\0" \
13b4f639 SR	352	"addip=setenv bootargs ${bootargs} " \
	353	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	354	":${hostname}:${netdev}:off panic=1\0" \
	355	"addtty=setenv bootargs ${bootargs} " \
	356	"console=${consoledev},${baudrate}\0" \
d62a89bd	357	"flash_nfs=run nfsargs addip addtty addmtd addhost;" \
8aa34499	358	"bootm ${kernel_addr} - ${fdt_addr}\0" \
d62a89bd	359	"flash_mtd=run mtdargs addip addtty addmtd addhost;" \
8aa34499	360	"bootm ${kernel_addr} - ${fdt_addr}\0" \
d62a89bd	361	"flash_self=run ramargs addip addtty addmtd addhost;" \
d4451d35 SR	362	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	363	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	364	"tftp ${fdt_addr_r} ${fdtfile};" \
d62a89bd	365	"run nfsargs addip addtty addmtd addhost;" \
d4451d35 SR	366	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	367	"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
	368	"/u-boot-img.bin\0" \
d62a89bd	369	"update=protect off fc000000 fc07ffff;" \
8aa34499 SR	370	"era fc000000 fc07ffff;" \
8aa34499 SR	371	"cp.b ${loadaddr} fc000000 ${filesize}\0" \
13b4f639	372	"upd=run load;run update\0" \
d62a89bd SR	373	"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
	374	"run mtdargs addip addtty addmtd addhost;" \
	375	"fdt addr 1800000;fdt boardsetup;fdt chosen;" \
	376	"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
	377	"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
	378	"erase fc200000 fc6fffff;" \
	379	"cp.b 1000000 fc200000 ${filesize}" \
	380	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	381	"mtdids=" MTDIDS_DEFAULT "\0" \
	382	"mtdparts=" MTDPARTS_DEFAULT "\0" \
13b4f639 SR	383	""
	384
	385	#define CONFIG_BOOTCOMMAND "run flash_mtd"
	386
	387	/*
	388	* SPL related defines
	389	*/
13b4f639	390	#define CONFIG_SPL_FRAMEWORK
d4451d35	391	#define CONFIG_SPL_BOARD_INIT
13b4f639	392	#define CONFIG_SPL_TEXT_BASE 0xfc000000
13b4f639 SR	393
	394	/* Place BSS for SPL near end of SDRAM */
	395	#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
	396	#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
	397
13b4f639 SR	398	/* Place patched DT blob (fdt) at this address */
	399	#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
	400
	401	/* Settings for real U-Boot to be loaded from NOR flash */
	402	#ifndef __ASSEMBLY__
	403	extern char __spl_flash_end[];
	404	#endif
	405	#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
	406	#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
	407	#define CONFIG_SYS_UBOOT_START 0x1000100
	408
	409	#endif /* __CONFIG_H */