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13b4f639 | 1 | /* |
8aa34499 | 2 | * Copyright 2012-2013 Stefan Roese <sr@denx.de> |
13b4f639 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
13b4f639 SR |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | /* | |
11 | * High Level Configuration Options | |
12 | * (easy to change) | |
13 | */ | |
14 | ||
15 | #define CONFIG_MPC5200 | |
b2a6dfe4 | 16 | #define CONFIG_A3M071 /* A3M071 board */ |
c07e8da1 | 17 | #define CONFIG_DISPLAY_BOARDINFO |
13b4f639 SR |
18 | |
19 | #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ | |
20 | ||
d4451d35 SR |
21 | #define CONFIG_SPL_TARGET "u-boot-img.bin" |
22 | ||
13b4f639 SR |
23 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
24 | ||
25 | #define CONFIG_MISC_INIT_R | |
26 | #define CONFIG_SYS_LOWBOOT /* Enable lowboot */ | |
27 | ||
d4451d35 SR |
28 | #ifdef CONFIG_A4M2K |
29 | #define CONFIG_HOSTNAME a4m2k | |
30 | #else | |
31 | #define CONFIG_HOSTNAME a3m071 | |
32 | #endif | |
33 | ||
d62a89bd SR |
34 | #define CONFIG_BOOTCOUNT_LIMIT |
35 | ||
13b4f639 SR |
36 | /* |
37 | * Serial console configuration | |
38 | */ | |
39 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
40 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
41 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
42 | { 9600, 19200, 38400, 57600, 115200, 230400 } | |
43 | ||
44 | /* | |
45 | * Command line configuration. | |
46 | */ | |
13b4f639 SR |
47 | #define CONFIG_CMD_BSP |
48 | #define CONFIG_CMD_CACHE | |
13b4f639 SR |
49 | #define CONFIG_CMD_MII |
50 | #define CONFIG_CMD_REGINFO | |
8aa34499 SR |
51 | #define CONFIG_CMD_DHCP |
52 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
53 | #define CONFIG_BOOTP_SERVERIP | |
54 | #define CONFIG_BOOTP_MAY_FAIL | |
55 | #define CONFIG_BOOTP_BOOTPATH | |
56 | #define CONFIG_BOOTP_GATEWAY | |
57 | #define CONFIG_BOOTP_SERVERIP | |
58 | #define CONFIG_NET_RETRY_COUNT 3 | |
59 | #define CONFIG_CMD_LINK_LOCAL | |
60 | #define CONFIG_NETCONSOLE | |
61 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
62 | #define CONFIG_CMD_PING | |
63 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
64 | #define CONFIG_MTD_PARTITIONS /* needed for UBI */ | |
65 | #define CONFIG_FLASH_CFI_MTD | |
66 | #define MTDIDS_DEFAULT "nor0=fc000000.flash" | |
67 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ | |
d62a89bd SR |
68 | "128k(env1)," \ |
69 | "128k(env2)," \ | |
8aa34499 SR |
70 | "128k(hwinfo)," \ |
71 | "1M(nvramsim)," \ | |
72 | "128k(dtb)," \ | |
73 | "5M(kernel)," \ | |
74 | "128k(sysinfo)," \ | |
75 | "7552k(root)," \ | |
76 | "4M(app)," \ | |
d62a89bd SR |
77 | "5376k(data)," \ |
78 | "8M(install)" | |
79 | ||
8aa34499 SR |
80 | #define CONFIG_LZO /* needed for UBI */ |
81 | #define CONFIG_RBTREE /* needed for UBI */ | |
82 | #define CONFIG_CMD_MTDPARTS | |
83 | #define CONFIG_CMD_UBI | |
84 | #define CONFIG_CMD_UBIFS | |
13b4f639 SR |
85 | |
86 | /* | |
87 | * IPB Bus clocking configuration. | |
88 | */ | |
89 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ | |
90 | /* define for 66MHz speed - undef for 33MHz PCI clock speed */ | |
d4451d35 SR |
91 | #ifdef CONFIG_A4M2K |
92 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
93 | #else | |
13b4f639 | 94 | #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 |
d4451d35 | 95 | #endif |
13b4f639 | 96 | |
13b4f639 SR |
97 | /* maximum size of the flat tree (8K) */ |
98 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
99 | ||
100 | #define OF_CPU "PowerPC,5200@0" | |
101 | #define OF_SOC "soc5200@f0000000" | |
102 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
103 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
104 | ||
13b4f639 SR |
105 | /* |
106 | * NOR flash configuration | |
107 | */ | |
108 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 | |
d4451d35 | 109 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 |
8aa34499 | 110 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) |
13b4f639 SR |
111 | |
112 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
113 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
114 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 | |
115 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
116 | #define CONFIG_SYS_FLASH_LOCK_TOUT 5 | |
117 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 | |
118 | #define CONFIG_SYS_FLASH_PROTECTION | |
119 | #define CONFIG_FLASH_CFI_DRIVER | |
120 | #define CONFIG_SYS_FLASH_CFI | |
121 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
122 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
f8945518 | 123 | #define CONFIG_FLASH_VERIFY |
13b4f639 SR |
124 | |
125 | /* | |
126 | * Environment settings | |
127 | */ | |
128 | #define CONFIG_ENV_IS_IN_FLASH | |
129 | #define CONFIG_ENV_SIZE 0x10000 | |
130 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
131 | #define CONFIG_ENV_OVERWRITE | |
8aa34499 SR |
132 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
133 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
13b4f639 SR |
134 | |
135 | /* | |
136 | * Memory map | |
137 | */ | |
138 | #define CONFIG_SYS_MBAR 0xf0000000 | |
139 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
140 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
141 | ||
142 | /* Use SRAM until RAM will be available */ | |
143 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
b39d1213 | 144 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
13b4f639 | 145 | |
b39d1213 | 146 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
704afcc4 | 147 | GENERATED_GBL_DATA_SIZE) |
13b4f639 SR |
148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
149 | ||
150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
151 | ||
8aa34499 SR |
152 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
153 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) | |
13b4f639 SR |
154 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
155 | ||
156 | /* | |
157 | * Ethernet configuration | |
158 | */ | |
159 | #define CONFIG_MPC5xxx_FEC | |
160 | #define CONFIG_MPC5xxx_FEC_MII100 | |
d4451d35 SR |
161 | #ifdef CONFIG_A4M2K |
162 | #define CONFIG_PHY_ADDR 0x01 | |
163 | #else | |
13b4f639 | 164 | #define CONFIG_PHY_ADDR 0x00 |
d4451d35 | 165 | #endif |
13b4f639 SR |
166 | |
167 | /* | |
168 | * GPIO configuration | |
169 | */ | |
170 | ||
171 | /* | |
172 | * GPIO-config depends on failsave-level | |
173 | * failsave 0 means just MPX-config, no digiboard, no fpga | |
174 | * 1 means digiboard ok | |
175 | * 2 means fpga ok | |
176 | */ | |
177 | ||
d4451d35 | 178 | #ifdef CONFIG_A4M2K |
8aa34499 | 179 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805 |
d4451d35 | 180 | #else |
13b4f639 SR |
181 | /* for failsave-level 0 - full failsave */ |
182 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 | |
183 | /* for failsave-level 1 - only digiboard ok */ | |
8aa34499 | 184 | #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065 |
13b4f639 | 185 | /* for failsave-level 2 - all ok */ |
8aa34499 | 186 | #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065 |
d4451d35 | 187 | #endif |
13b4f639 | 188 | |
aed75484 SR |
189 | #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 |
190 | #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) | |
191 | #define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ | |
192 | #endif | |
193 | ||
13b4f639 SR |
194 | /* |
195 | * Configuration matrix | |
8aa34499 | 196 | * MSB LSB |
d4451d35 | 197 | * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) |
8aa34499 SR |
198 | * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok ) |
199 | * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok ) | |
13b4f639 SR |
200 | * || ||| || | ||| | | | | |
201 | * || ||| || | ||| | | | | bit rev name | |
202 | * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 | |
203 | * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ | |
204 | * ||| || | ||| | | | | 2 29 ALTs | |
205 | * +++-++--+---+++-+---+---+---+- 3 28 ALTs | |
206 | * ++-++--+---+++-+---+---+---+- 4 27 CS7 | |
207 | * +-++--+---+++-+---+---+---+- 5 26 CS6 | |
208 | * || | ||| | | | | 6 25 ATA | |
209 | * ++--+---+++-+---+---+---+- 7 24 ATA | |
210 | * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK | |
211 | * | ||| | | | | 9 22 IRDA | |
212 | * | ||| | | | | 10 21 IRDA | |
213 | * +---+++-+---+---+---+- 11 20 IRDA | |
214 | * ||| | | | | 12 19 Ether | |
215 | * ||| | | | | 13 18 Ether | |
216 | * ||| | | | | 14 17 Ether | |
217 | * +++-+---+---+---+- 15 16 Ether | |
218 | * ++-+---+---+---+- 16 15 PCI_DIS | |
219 | * +-+---+---+---+- 17 14 USB_SE | |
220 | * | | | | 18 13 USB | |
221 | * +---+---+---+- 19 12 USB | |
222 | * | | | 20 11 PSC3 | |
223 | * | | | 21 10 PSC3 | |
224 | * | | | 22 9 PSC3 | |
225 | * +---+---+- 23 8 PSC3 | |
226 | * | | 24 7 - | |
227 | * | | 25 6 PSC2 | |
228 | * | | 26 5 PSC2 | |
229 | * +---+- 27 4 PSC2 | |
230 | * | 28 3 - | |
231 | * | 29 2 PSC1 | |
232 | * | 30 1 PSC1 | |
233 | * +- 31 0 PSC1 | |
234 | */ | |
235 | ||
236 | ||
237 | /* | |
238 | * Miscellaneous configurable options | |
239 | */ | |
240 | #define CONFIG_SYS_LONGHELP | |
13b4f639 SR |
241 | |
242 | #define CONFIG_CMDLINE_EDITING | |
13b4f639 SR |
243 | |
244 | #if defined(CONFIG_CMD_KGDB) | |
245 | #define CONFIG_SYS_CBSIZE 1024 | |
246 | #else | |
247 | #define CONFIG_SYS_CBSIZE 256 | |
248 | #endif | |
249 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
250 | #define CONFIG_SYS_MAXARGS 16 | |
251 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
252 | ||
253 | #define CONFIG_SYS_MEMTEST_START 0x00100000 | |
254 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 | |
255 | ||
256 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 | |
257 | ||
13b4f639 SR |
258 | #define CONFIG_LOOPW |
259 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ | |
260 | ||
261 | /* | |
262 | * Various low-level settings | |
263 | */ | |
264 | #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) | |
265 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
266 | ||
267 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
268 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
269 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
270 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
d4451d35 SR |
271 | |
272 | #ifdef CONFIG_A4M2K | |
273 | /* external MRAM */ | |
274 | #define CONFIG_SYS_CS1_START 0xf1000000 | |
275 | #define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ | |
276 | #endif | |
277 | ||
13b4f639 SR |
278 | #define CONFIG_SYS_CS2_START 0xe0000000 |
279 | #define CONFIG_SYS_CS2_SIZE 0x00100000 | |
280 | ||
d4451d35 | 281 | /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ |
13b4f639 | 282 | #define CONFIG_SYS_CS3_START 0xE9000000 |
d4451d35 SR |
283 | #ifdef CONFIG_A4M2K |
284 | #define CONFIG_SYS_CS3_SIZE 0x00100000 | |
285 | #else | |
13b4f639 | 286 | #define CONFIG_SYS_CS3_SIZE 0x00080000 |
d4451d35 | 287 | #endif |
13b4f639 SR |
288 | /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ |
289 | #define CONFIG_SYS_CS3_CFG 0x0032B900 | |
290 | ||
d4451d35 | 291 | #ifndef CONFIG_A4M2K |
13b4f639 SR |
292 | /* Diagnosis Interface - see ticket #63 */ |
293 | #define CONFIG_SYS_CS4_START 0xEA000000 | |
294 | #define CONFIG_SYS_CS4_SIZE 0x00000001 | |
295 | /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ | |
296 | #define CONFIG_SYS_CS4_CFG 0x0002B900 | |
d4451d35 | 297 | #endif |
13b4f639 | 298 | |
d4451d35 | 299 | /* FPGA master io (64kiB / 1MiB) - see ticket #66 */ |
13b4f639 | 300 | #define CONFIG_SYS_CS5_START 0xE8000000 |
d4451d35 SR |
301 | #ifdef CONFIG_A4M2K |
302 | #define CONFIG_SYS_CS5_SIZE 0x00100000 | |
303 | #else | |
13b4f639 | 304 | #define CONFIG_SYS_CS5_SIZE 0x00010000 |
d4451d35 | 305 | #endif |
13b4f639 SR |
306 | /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ |
307 | #define CONFIG_SYS_CS5_CFG 0x0032B900 | |
308 | ||
309 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ | |
310 | #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 | |
d4451d35 | 311 | #define CONFIG_SYS_CS1_CFG 0x0008FD00 |
13b4f639 SR |
312 | #define CONFIG_SYS_CS2_CFG 0x0006F90C |
313 | #else /* for pci_clk = 33 MHz */ | |
314 | #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 | |
315 | #define CONFIG_SYS_CS1_CFG 0x0001FB00 | |
316 | #define CONFIG_SYS_CS2_CFG 0x0002F90C | |
317 | #endif | |
318 | ||
319 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
320 | /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */ | |
321 | /* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */ | |
322 | /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */ | |
323 | #define CONFIG_SYS_CS_DEADCYCLE 0x33030000 | |
324 | ||
325 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
326 | ||
327 | /* | |
328 | * Environment Configuration | |
329 | */ | |
330 | ||
8aa34499 | 331 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ |
13b4f639 SR |
332 | #undef CONFIG_BOOTARGS |
333 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
334 | ||
8aa34499 SR |
335 | #define CONFIG_SYS_AUTOLOAD "n" |
336 | ||
13b4f639 SR |
337 | #define CONFIG_PREBOOT "echo;" \ |
338 | "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \ | |
339 | "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \ | |
340 | "echo" | |
341 | ||
342 | #undef CONFIG_BOOTARGS | |
343 | ||
8aa34499 SR |
344 | #define CONFIG_SYS_OS_BASE 0xfc200000 |
345 | #define CONFIG_SYS_FDT_BASE 0xfc1e0000 | |
13b4f639 | 346 | |
13b4f639 SR |
347 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
348 | "netdev=eth0\0" \ | |
349 | "verify=no\0" \ | |
d4451d35 SR |
350 | "loadaddr=200000\0" \ |
351 | "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ | |
352 | "kernel_addr_r=1000000\0" \ | |
353 | "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ | |
354 | "fdt_addr_r=1800000\0" \ | |
355 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ | |
356 | "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ | |
357 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
358 | "rootpath=/opt/eldk-5.2.1/powerpc/" \ | |
359 | "core-image-minimal-mtdutils-dropbear-generic\0" \ | |
13b4f639 SR |
360 | "consoledev=ttyPSC0\0" \ |
361 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
362 | "nfsroot=${serverip}:${rootpath}\0" \ | |
363 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
d62a89bd | 364 | "mtdargs=setenv bootargs root=/dev/mtdblock8 " \ |
8aa34499 SR |
365 | "rootfstype=squashfs,jffs2\0" \ |
366 | "addhost=setenv bootargs ${bootargs} " \ | |
367 | "hostname=${hostname}\0" \ | |
13b4f639 SR |
368 | "addip=setenv bootargs ${bootargs} " \ |
369 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
370 | ":${hostname}:${netdev}:off panic=1\0" \ | |
371 | "addtty=setenv bootargs ${bootargs} " \ | |
372 | "console=${consoledev},${baudrate}\0" \ | |
d62a89bd | 373 | "flash_nfs=run nfsargs addip addtty addmtd addhost;" \ |
8aa34499 | 374 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
d62a89bd | 375 | "flash_mtd=run mtdargs addip addtty addmtd addhost;" \ |
8aa34499 | 376 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
d62a89bd | 377 | "flash_self=run ramargs addip addtty addmtd addhost;" \ |
d4451d35 SR |
378 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
379 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
380 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
d62a89bd | 381 | "run nfsargs addip addtty addmtd addhost;" \ |
d4451d35 SR |
382 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
383 | "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ | |
384 | "/u-boot-img.bin\0" \ | |
d62a89bd | 385 | "update=protect off fc000000 fc07ffff;" \ |
8aa34499 SR |
386 | "era fc000000 fc07ffff;" \ |
387 | "cp.b ${loadaddr} fc000000 ${filesize}\0" \ | |
13b4f639 | 388 | "upd=run load;run update\0" \ |
d62a89bd SR |
389 | "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \ |
390 | "run mtdargs addip addtty addmtd addhost;" \ | |
391 | "fdt addr 1800000;fdt boardsetup;fdt chosen;" \ | |
392 | "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \ | |
393 | "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \ | |
394 | "erase fc200000 fc6fffff;" \ | |
395 | "cp.b 1000000 fc200000 ${filesize}" \ | |
396 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
397 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
398 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
13b4f639 SR |
399 | "" |
400 | ||
401 | #define CONFIG_BOOTCOMMAND "run flash_mtd" | |
402 | ||
403 | /* | |
404 | * SPL related defines | |
405 | */ | |
13b4f639 | 406 | #define CONFIG_SPL_FRAMEWORK |
d4451d35 | 407 | #define CONFIG_SPL_BOARD_INIT |
13b4f639 SR |
408 | #define CONFIG_SPL_NOR_SUPPORT |
409 | #define CONFIG_SPL_TEXT_BASE 0xfc000000 | |
13b4f639 SR |
410 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ |
411 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ | |
412 | #define CONFIG_SPL_SERIAL_SUPPORT | |
413 | ||
414 | /* Place BSS for SPL near end of SDRAM */ | |
415 | #define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20) | |
416 | #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) | |
417 | ||
418 | #define CONFIG_SPL_OS_BOOT | |
ba1bee43 | 419 | #define CONFIG_SPL_ENV_SUPPORT |
13b4f639 SR |
420 | /* Place patched DT blob (fdt) at this address */ |
421 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 | |
422 | ||
423 | /* Settings for real U-Boot to be loaded from NOR flash */ | |
424 | #ifndef __ASSEMBLY__ | |
425 | extern char __spl_flash_end[]; | |
426 | #endif | |
427 | #define CONFIG_SYS_UBOOT_BASE __spl_flash_end | |
428 | #define CONFIG_SYS_SPL_MAX_LEN (32 << 10) | |
429 | #define CONFIG_SYS_UBOOT_START 0x1000100 | |
430 | ||
431 | #endif /* __CONFIG_H */ |