projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9531a238 SP |
1 | /* |
| 2 | * (C) Copyright 2003-2005 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * (C) Copyright 2010 | |
| 6 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 30 | /* | |
| 31 | * High Level Configuration Options | |
| 32 | * (easy to change) | |
| 33 | */ | |
| 34 | ||
| 35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
| 36 | #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ | |
| 37 | #define CONFIG_A4M072 1 /* ... on A4M072 board */ | |
| 38 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
| 39 | ||
| 40 | #define CONFIG_MISC_INIT_R | |
| 41 | ||
| 42 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
| 43 | ||
| 44 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 45 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 46 | ||
| 47 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
| 48 | ||
| 49 | /* | |
| 50 | * Serial console configuration | |
| 51 | */ | |
| 52 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
| 53 | #define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ | |
| 54 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
| 55 | /* define to enable silent console */ | |
| 56 | #define CONFIG_SILENT_CONSOLE | |
| 57 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ | |
| 58 | ||
| 59 | /* | |
| 60 | * PCI Mapping: | |
| 61 | * 0x40000000 - 0x4fffffff - PCI Memory | |
| 62 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
| 63 | */ | |
| 64 | #define CONFIG_PCI | |
| 65 | ||
| 66 | #if defined(CONFIG_PCI) | |
| 67 | #define CONFIG_PCI_PNP 1 | |
| 68 | #define CONFIG_PCI_SCAN_SHOW 1 | |
| 69 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 | |
| 70 | ||
| 71 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
| 72 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
| 73 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
| 74 | ||
| 75 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
| 76 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
| 77 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
| 78 | #endif | |
| 79 | ||
| 80 | #define CONFIG_SYS_XLB_PIPELINING 1 | |
| 81 | ||
| 82 | #undef CONFIG_NET_MULTI | |
| 83 | #undef CONFIG_EEPRO100 | |
| 84 | ||
| 85 | /* Partitions */ | |
| 86 | #define CONFIG_MAC_PARTITION | |
| 87 | #define CONFIG_DOS_PARTITION | |
| 88 | ||
| 89 | /* USB */ | |
| 90 | #define CONFIG_USB_OHCI_NEW | |
| 91 | #define CONFIG_USB_STORAGE | |
| 92 | #define CONFIG_SYS_OHCI_BE_CONTROLLER | |
| 93 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT | |
| 94 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
| 95 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
| 96 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
| 97 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 98 | ||
| 99 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
| 100 | ||
| 101 | /* | |
| 102 | * BOOTP options | |
| 103 | */ | |
| 104 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 105 | #define CONFIG_BOOTP_BOOTPATH | |
| 106 | #define CONFIG_BOOTP_GATEWAY | |
| 107 | #define CONFIG_BOOTP_HOSTNAME | |
| 108 | ||
| 109 | ||
| 110 | /* | |
| 111 | * Command line configuration. | |
| 112 | */ | |
| 113 | #include <config_cmd_default.h> | |
| 114 | ||
| 115 | #define CONFIG_CMD_EEPROM | |
| 116 | #define CONFIG_CMD_FAT | |
| 117 | #define CONFIG_CMD_I2C | |
| 118 | #define CONFIG_CMD_IDE | |
| 119 | #define CONFIG_CMD_NFS | |
| 120 | #define CONFIG_CMD_SNTP | |
| 121 | #define CONFIG_CMD_USB | |
| 122 | #define CONFIG_CMD_MII | |
| 123 | #define CONFIG_CMD_DHCP | |
| 124 | #define CONFIG_CMD_PING | |
| 125 | ||
| 126 | #if defined(CONFIG_PCI) | |
| 127 | #define CONFIG_CMD_PCI | |
| 128 | #endif | |
| 129 | ||
| 130 | #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ | |
| 131 | #define CONFIG_SYS_LOWBOOT 1 | |
| 132 | #define CONFIG_SYS_LOWBOOT32 1 | |
| 133 | #endif | |
| 134 | ||
| 135 | /* | |
| 136 | * Autobooting | |
| 137 | */ | |
| 138 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ | |
| 139 | ||
| 140 | #define CONFIG_SYS_AUTOLOAD "n" | |
| 141 | ||
| 142 | #define CONFIG_AUTOBOOT_KEYED | |
| 143 | #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay | |
| 144 | #define CONFIG_AUTOBOOT_DELAY_STR "asdfg" | |
| 145 | ||
| 146 | #undef CONFIG_BOOTARGS | |
| 147 | #define CONFIG_PREBOOT "run try_update" | |
| 148 | ||
| 149 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 150 | "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \ | |
| 151 | "cf1=diskboot 200000 0:1\0" \ | |
| 152 | "bootcmd_cf1=run bcf1\0" \ | |
| 153 | "bcf=setenv bootargs root=/dev/hda3\0" \ | |
| 154 | "bootcmd_nfs=run bnfs\0" \ | |
| 155 | "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \ | |
| 156 | "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \ | |
| 157 | "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \ | |
| 158 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ | |
| 159 | "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \ | |
| 160 | "env_addr=FE060000\0" \ | |
| 161 | "kernel_addr=FE100000\0" \ | |
| 162 | "rootfs_addr=FE200000\0" \ | |
| 163 | "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \ | |
| 164 | "bcf1=run cf1; run bcf; run addip; run bk\0" \ | |
| 165 | "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \ | |
| 166 | "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \ | |
| 167 | "hostname=CPUP0\0" \ | |
| 168 | "ethaddr=00:00:00:00:00:00\0" \ | |
| 169 | "netdev=eth0\0" \ | |
| 170 | "bootcmd=run bootcmd_nor\0" \ | |
| 171 | "" | |
| 172 | /* | |
| 173 | * IPB Bus clocking configuration. | |
| 174 | */ | |
| 175 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ | |
| 176 | ||
| 177 | /* | |
| 178 | * I2C configuration | |
| 179 | */ | |
| 180 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
| 181 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ | |
| 182 | ||
| 183 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
| 184 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 185 | ||
| 186 | /* | |
| 187 | * EEPROM configuration | |
| 188 | */ | |
| 189 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */ | |
| 190 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 191 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
| 192 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 193 | #define CONFIG_SYS_EEPROM_WREN 1 | |
| 194 | #define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4 | |
| 195 | ||
| 196 | /* | |
| 197 | * Flash configuration | |
| 198 | */ | |
| 199 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
| 200 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
| 201 | #if !defined(CONFIG_SYS_LOWBOOT) | |
| 202 | #error "CONFIG_SYS_LOWBOOT not defined?" | |
| 203 | #else /* CONFIG_SYS_LOWBOOT */ | |
| 204 | #if defined(CONFIG_SYS_LOWBOOT32) | |
| 205 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) | |
| 206 | #endif | |
| 207 | #endif /* CONFIG_SYS_LOWBOOT */ | |
| 208 | ||
| 209 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
| 210 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
| 211 | #define CONFIG_FLASH_CFI_DRIVER | |
| 212 | #define CONFIG_SYS_FLASH_CFI | |
| 213 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 214 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} | |
| 215 | ||
| 216 | /* | |
| 217 | * Environment settings | |
| 218 | */ | |
| 219 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 220 | #define CONFIG_ENV_SIZE 0x10000 | |
| 221 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 222 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
| 223 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 224 | ||
| 225 | #define CONFIG_ENV_OVERWRITE 1 | |
| 226 | ||
| 227 | /* | |
| 228 | * Memory map | |
| 229 | */ | |
| 230 | #define CONFIG_SYS_MBAR 0xF0000000 | |
| 231 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
| 232 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
| 233 | ||
| 234 | /* Use SRAM until RAM will be available */ | |
| 235 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
| 236 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
| 237 | ||
| 238 | ||
| 239 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
| 240 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 241 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 242 | ||
| 243 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
| 244 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
| 245 | # define CONFIG_SYS_RAMBOOT 1 | |
| 246 | #endif | |
| 247 | ||
| 248 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ | |
| 249 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 250 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 251 | ||
| 252 | /* | |
| 253 | * Ethernet configuration | |
| 254 | */ | |
| 255 | #define CONFIG_MPC5xxx_FEC 1 | |
| 256 | #define CONFIG_MPC5xxx_FEC_MII100 | |
| 257 | /* | |
| 258 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb | |
| 259 | */ | |
| 260 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ | |
| 261 | #define CONFIG_PHY_ADDR 0x1f | |
| 262 | #define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ | |
| 263 | ||
| 264 | /* | |
| 265 | * GPIO configuration | |
| 266 | */ | |
| 267 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 | |
| 268 | ||
| 269 | /* | |
| 270 | * Miscellaneous configurable options | |
| 271 | */ | |
| 272 | #define CONFIG_SYS_HUSH_PARSER | |
| 273 | #define CONFIG_CMDLINE_EDITING 1 | |
| 274 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 275 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 276 | #endif | |
| 277 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 278 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 279 | #if defined(CONFIG_CMD_KGDB) | |
| 280 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 281 | #else | |
| 282 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 283 | #endif | |
| 284 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 285 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 286 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 287 | ||
| 288 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
| 289 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
| 290 | ||
| 291 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
| 292 | ||
| 293 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 294 | ||
| 295 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ | |
| 296 | #if defined(CONFIG_CMD_KGDB) | |
| 297 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 298 | #endif | |
| 299 | ||
| 300 | ||
| 301 | /* | |
| 302 | * Various low-level settings | |
| 303 | */ | |
| 304 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI | |
| 305 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
| 306 | /* Flash at CSBoot, CS0 */ | |
| 307 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
| 308 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
| 309 | #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 | |
| 310 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
| 311 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
| 312 | /* External SRAM at CS1 */ | |
| 313 | #define CONFIG_SYS_CS1_START 0x62000000 | |
| 314 | #define CONFIG_SYS_CS1_SIZE 0x00400000 | |
| 315 | #define CONFIG_SYS_CS1_CFG 0x00009930 | |
| 316 | #define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START | |
| 317 | #define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE | |
| 318 | ||
| 319 | ||
| 320 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
| 321 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333003 | |
| 322 | ||
| 323 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
| 324 | ||
| 325 | /*----------------------------------------------------------------------- | |
| 326 | * USB stuff | |
| 327 | *----------------------------------------------------------------------- | |
| 328 | */ | |
| 329 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
| 330 | #define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ | |
| 331 | ||
| 332 | /*----------------------------------------------------------------------- | |
| 333 | * IDE/ATA stuff Supports IDE harddisk | |
| 334 | *----------------------------------------------------------------------- | |
| 335 | */ | |
| 336 | ||
| 337 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
| 338 | ||
| 339 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 340 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 341 | ||
| 342 | #define CONFIG_IDE_PREINIT | |
| 343 | ||
| 344 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
| 345 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ | |
| 346 | ||
| 347 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| 348 | ||
| 349 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
| 350 | ||
| 351 | /* Offset for data I/O */ | |
| 352 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
| 353 | ||
| 354 | /* Offset for normal register accesses */ | |
| 355 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
| 356 | ||
| 357 | /* Offset for alternate registers */ | |
| 358 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
| 359 | ||
| 360 | /* Interval between registers */ | |
| 361 | #define CONFIG_SYS_ATA_STRIDE 4 | |
| 362 | ||
| 363 | #define CONFIG_ATAPI 1 | |
| 364 | ||
| 365 | /*----------------------------------------------------------------------- | |
| 366 | * Open firmware flat tree support | |
| 367 | *----------------------------------------------------------------------- | |
| 368 | */ | |
| 369 | #define CONFIG_OF_LIBFDT 1 | |
| 370 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 371 | ||
| 372 | #define OF_CPU "PowerPC,5200@0" | |
| 373 | #define OF_SOC "soc5200@f0000000" | |
| 374 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 375 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
| 376 | ||
| 377 | #endif /* __CONFIG_H */ |