[people/ms/u-boot.git] / include / configs / ac14xx.h

/*
 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
 * (C) Copyright 2010 DAVE Srl <www.dave.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * ifm AC14xx (MPC5121e based) board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_AC14XX 1

/*
 * Memory map for the ifm AC14xx board:
 *
 * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
 * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
 * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
 * 0xE000_0000-0xEFFF_FFFF	several LPB attached hardware (CSx)
 * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
 */

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */

#define CONFIG_SYS_TEXT_BASE	0xFFF00000

#if defined(CONFIG_VIDEO)
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif

#define CONFIG_SYS_MPC512X_CLKIN	25000000	/* in Hz */
#define SCFR1_IPS_DIV			2
#define SCFR1_LPC_DIV			2
#define SCFR1_NFC_DIV			2
#define SCFR1_DIU_DIV			240

#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_IMMR			0x80000000
#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR + 0x2100)

/* more aggressive 'mtest' over a wider address range */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x0FE00000

/*
 * DDR Setup - manually set all parameters as there's no SPD etc.
 */
#define CONFIG_SYS_DDR_SIZE		256		/* MB */
#define CONFIG_SYS_DDR_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000

/*
 * DDR Controller Configuration
 *
 * SYS_CFG:
 *	[31:31]	MDDRC Soft Reset:	Diabled
 *	[30:30]	DRAM CKE pin:		Enabled
 *	[29:29]	DRAM CLK:		Enabled
 *	[28:28]	Command Mode:		Enabled (For initialization only)
 *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
 *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
 *	[20:19]	Read Test:		DON'T USE
 *	[18:18]	Self Refresh:		Enabled
 *	[17:17]	16bit Mode:		Disabled
 *	[16:13] Ready Delay:		2
 *	[12:12]	Half DQS Delay:		Disabled
 *	[11:11]	Quarter DQS Delay:	Disabled
 *	[10:08]	Write Delay:		2
 *	[07:07]	Early ODT:		Disabled
 *	[06:06]	On DIE Termination:	Disabled
 *	[05:05]	FIFO Overflow Clear:	DON'T USE here
 *	[04:04]	FIFO Underflow Clear:	DON'T USE here
 *	[03:03]	FIFO Overflow Pending:	DON'T USE here
 *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
 *	[01:01]	FIFO Overlfow Enabled:	Enabled
 *	[00:00]	FIFO Underflow Enabled:	Enabled
 * TIME_CFG0
 *	[31:16]	DRAM Refresh Time:	0 CSB clocks
 *	[15:8]	DRAM Command Time:	0 CSB clocks
 *	[07:00]	DRAM Precharge Time:	0 CSB clocks
 * TIME_CFG1
 *	[31:26]	DRAM tRFC:
 *	[25:21]	DRAM tWR1:
 *	[20:17]	DRAM tWRT1:
 *	[16:11]	DRAM tDRR:
 *	[10:05]	DRAM tRC:
 *	[04:00]	DRAM tRAS:
 * TIME_CFG2
 *	[31:28]	DRAM tRCD:
 *	[27:23]	DRAM tFAW:
 *	[22:19]	DRAM tRTW1:
 *	[18:15]	DRAM tCCD:
 *	[14:10] DRAM tRTP:
 *	[09:05]	DRAM tRP:
 *	[04:00] DRAM tRPA
 */

/*
 * NOTE: although this board uses DDR1 only, the common source brings defaults
 * for DDR2 init sequences, that's why we have to keep those here as well
 */

/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
#define CONFIG_SYS_IOCTRL_MUX_DDR	((0 << 6) | (3 << 3) | (3 << 0))

#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
			| (1 << 31)	/* RST_B */ \
			| (1 << 30)	/* CKE */ \
			| (1 << 29)	/* CLK_ON */ \
			| (0 << 28)	/* CMD_MODE */ \
			| (5 << 25)	/* DRAM_ROW_SELECT */ \
			| (5 << 21)	/* DRAM_BANK_SELECT */ \
			| (0 << 18)	/* SELF_REF_EN */ \
			| (0 << 17)	/* 16BIT_MODE */ \
			| (4 << 13)	/* RDLY */ \
			| (1 << 12)	/* HALF_DQS_DLY */ \
			| (0 << 11)	/* QUART_DQS_DLY */ \
			| (1 <<  8)	/* WDLY */ \
			| (0 <<  7)	/* EARLY_ODT */ \
			| (0 <<  6)	/* ON_DIE_TERMINATE */ \
			| (0 <<  5)	/* FIFO_OV_CLEAR */ \
			| (0 <<  4)	/* FIFO_UV_CLEAR */ \
			| (0 <<  1)	/* FIFO_OV_EN */ \
			| (0 <<  0)	/* FIFO_UV_EN */ \
			)

#define CONFIG_SYS_MDDRC_TIME_CFG0	0x04E03124
#define CONFIG_SYS_MDDRC_TIME_CFG1	0x30CA1147
#define CONFIG_SYS_MDDRC_TIME_CFG2	0x32B10864

/* register address only, i.e. template without values */
#define CONFIG_SYS_MICRON_BMODE		0x01000000
#define CONFIG_SYS_MICRON_EMODE		0x01010000
#define CONFIG_SYS_MICRON_EMODE2	0x01020000
#define CONFIG_SYS_MICRON_EMODE3	0x01030000
/*
 * values for mode registers (without mode register address)
 */
/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
#define CONFIG_SYS_MICRON_BMODE_PARAM	0x00000062
#define CONFIG_SYS_MICRON_BMODE_RSTDLL	0x00000100
/* DLL enable, reduced drive strength */
#define CONFIG_SYS_MICRON_EMODE_PARAM	0x00000002

#define CONFIG_SYS_DDRCMD_NOP		0x01380000
#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
#define CONFIG_SYS_MICRON_EMR	       ((1 << 24) |	/* CMD_REQ */ \
					(0 << 22) |	/* DRAM_CS */ \
					(0 << 21) |	/* DRAM_RAS */ \
					(0 << 20) |	/* DRAM_CAS */ \
					(0 << 19) |	/* DRAM_WEB */ \
					(1 << 16) |	/* DRAM_BS[2:0] */ \
					(0 << 15) |	/* */ \
					(0 << 12) |	/* A12->out */ \
					(0 << 11) |	/* A11->RDQS */ \
					(0 << 10) |	/* A10->DQS# */ \
					(0 <<  7) |	/* OCD program */ \
					(0 <<  6) |	/* Rtt1 */ \
					(0 <<  3) |	/* posted CAS# */ \
					(0 <<  2) |	/* Rtt0 */ \
					(1 <<  1) |	/* ODS */ \
					(0 <<  0)	/* DLL */ \
				     )
#define CONFIG_SYS_MICRON_EMR2		0x01020000
#define CONFIG_SYS_MICRON_EMR3		0x01030000
#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
#define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |	/* CMD_REQ */ \
					(0 << 22) |	/* DRAM_CS */ \
					(0 << 21) |	/* DRAM_RAS */ \
					(0 << 20) |	/* DRAM_CAS */ \
					(0 << 19) |	/* DRAM_WEB */ \
					(1 << 16) |	/* DRAM_BS[2:0] */ \
					(0 << 15) |	/* */ \
					(0 << 12) |	/* A12->out */ \
					(0 << 11) |	/* A11->RDQS */ \
					(1 << 10) |	/* A10->DQS# */ \
					(7 <<  7) |	/* OCD program */ \
					(0 <<  6) |	/* Rtt1 */ \
					(0 <<  3) |	/* posted CAS# */ \
					(1 <<  2) |	/* Rtt0 */ \
					(0 <<  1) |	/* ODS */ \
					(0 <<  0)	/* DLL */ \
				     )

/*
 * Backward compatible definitions,
 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
 */
#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)

/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111

/*
 * NOR FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
	CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
	}
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * SRAM support
 */
#define CONFIG_SYS_SRAM_BASE		0x30000000
#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */

/*
 * CS related parameters
 */
/* CS0 Flash */
#define CONFIG_SYS_CS0_CFG		0x00031110
#define CONFIG_SYS_CS0_START		0xFC000000
#define CONFIG_SYS_CS0_SIZE		0x04000000
/* CS1 FRAM */
#define CONFIG_SYS_CS1_CFG		0x00011000
#define CONFIG_SYS_CS1_START		0xE0000000
#define CONFIG_SYS_CS1_SIZE		0x00010000
/* CS2 AS-i 1 */
#define CONFIG_SYS_CS2_CFG		0x00009100
#define CONFIG_SYS_CS2_START		0xE0100000
#define CONFIG_SYS_CS2_SIZE		0x00080000
/* CS3 netX */
#define CONFIG_SYS_CS3_CFG		0x000A1140
#define CONFIG_SYS_CS3_START		0xE0300000
#define CONFIG_SYS_CS3_SIZE		0x00020000
/* CS5 safety */
#define CONFIG_SYS_CS5_CFG		0x0011F000
#define CONFIG_SYS_CS5_START		0xE0400000
#define CONFIG_SYS_CS5_SIZE		0x00010000
/* CS6 AS-i 2 */
#define CONFIG_SYS_CS6_CFG		0x00009100
#define CONFIG_SYS_CS6_START		0xE0200000
#define CONFIG_SYS_CS6_SIZE		0x00080000

/* Don't use alternative CS timing for any CS */
#define CONFIG_SYS_CS_ALETIMING		0x00000000
#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE		0x00000020
#define CONFIG_SYS_CS_HOLDCYCLE		0x00000020

/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

#ifdef	CONFIG_FSL_DIU_FB
#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
#else
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
#endif

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif

#define CONFIG_BAUDRATE			115200	/* ... at 115200 bps */

#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR

/*
 * Clocks in use
 */
#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |		\
			 CLOCK_SCCR1_LPC_EN |		\
			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
			 CLOCK_SCCR1_PSC_EN(7) |	\
			 CLOCK_SCCR1_PSCFIFO_EN |	\
			 CLOCK_SCCR1_DDR_EN |		\
			 CLOCK_SCCR1_FEC_EN |		\
			 CLOCK_SCCR1_TPR_EN)

#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
			 CLOCK_SCCR2_SPDIF_EN |		\
			 CLOCK_SCCR2_DIU_EN |		\
			 CLOCK_SCCR2_I2C_EN)

#define CONFIG_CMDLINE_EDITING		1	/* command line history */

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#define CONFIG_I2C_MULTI_BUS

/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * IIM - IC Identification Module
 */
#undef CONFIG_FSL_IIM

/*
 * EEPROM configuration for Atmel AT24C01:
 * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	30
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5

/*
 * Ethernet configuration
 */
#define CONFIG_MPC512x_FEC		1
#define CONFIG_PHY_ADDR			0x1F
#define CONFIG_MII			1	/* MII PHY management */
#define CONFIG_FEC_AN_TIMEOUT		1
#define CONFIG_HAS_ETH0

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH		1
/* This has to be a multiple of the flash sector size */
#define CONFIG_ENV_ADDR			0xFFF40000
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_SECT_SIZE		0x20000

/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
					 CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO		1
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1

#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_FUSE
#undef CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#endif /* defined(CONFIG_CMD_IDE) */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
				 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS	32
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/* Cache Configuration */
#define CONFIG_SYS_DCACHE_SIZE		32768
#define CONFIG_SYS_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
#endif

#define CONFIG_SYS_HID0_INIT		0x000000000
#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
					 HID0_ICE)
#define CONFIG_SYS_HID2	HID2_HBE

#define CONFIG_HIGH_BATS		1	/* High BATs supported */

#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TIMESTAMP

/* default load addr for tftp and bootm */
#define CONFIG_LOADADDR		400000


/* the builtin environment and standard greeting */
#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
	"muster_nr=-00\0"						\
	"fromram=run ramargs addip addtty; "				\
		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
		"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "	\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
	"fromnfs=run nfsargs addip addtty; "				\
		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"fromflash=run nfsargs addip addtty; "				\
		"bootm fc020000 - fc000000\0"				\
	"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"		\
	"recovery=run mtdargsrec addip addtty; "			\
		"bootm ffd20000 - ffee0000\0"				\
	"production=run ramargs addip addtty; "				\
		"bootm fc020000 fc400000 fc000000\0"			\
	"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"		\
	"prodmtd=run mtdargs addip addtty; "				\
		"bootm fc020000 - fc000000\0"				\
	""

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u-boot_addr_r=200000\0"					\
	"kernel_addr_r=600000\0"					\
	"fdt_addr_r=a00000\0"						\
	"ramdisk_addr_r=b00000\0"					\
	"u-boot_addr=FFF00000\0"					\
	"kernel_addr=FC020000\0"					\
	"fdt_addr=FC000000\0"						\
	"ramdisk_addr=FC400000\0"					\
	"verify=n\0"							\
	"ramdiskfile=ac14xx/uRamdisk\0"					\
	"u-boot=ac14xx/u-boot.bin\0"					\
	"bootfile=ac14xx/uImage\0"					\
	"fdtfile=ac14xx/ac14xx.dtb\0"					\
	"netdev=eth0\0"							\
	"consdev=ttyPSC0\0"						\
	"hostname=ac14xx\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}${muster_nr}\0"	\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consdev},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run ramargs addip addtty;"				\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
	"update=protect off ${u-boot_addr} +${filesize};"		\
		"era ${u-boot_addr} +${filesize};"			\
		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
	CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
	"upd=run load update\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run production"

#define CONFIG_ARP_TIMEOUT	200UL

#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1

#define OF_CPU			"PowerPC,5121@0"
#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"

#endif	/* __CONFIG_H */
Commit	Line	Data
fcc7fe42 AG	1	/*
	2	* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
	3	* (C) Copyright 2010 DAVE Srl <www.dave.eu>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
fcc7fe42 AG	6	*/
	7
	8	/*
	9	* ifm AC14xx (MPC5121e based) board configuration file
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#define CONFIG_AC14XX 1
37cf49c5	16
fcc7fe42 AG	17	/*
	18	* Memory map for the ifm AC14xx board:
	19	*
	20	* 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
	21	* 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
	22	* 0x8000_0000-0x803F_FFFF IMMR (4 MB)
	23	* 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
	24	* 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
	25	*/
	26
	27	/*
	28	* High Level Configuration Options
	29	*/
	30	#define CONFIG_E300 1 /* E300 Family */
fcc7fe42 AG	31
	32	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	33
	34	#if defined(CONFIG_VIDEO)
	35	#define CONFIG_CFB_CONSOLE
	36	#define CONFIG_VGA_AS_SINGLE_DEVICE
	37	#endif
	38
	39	#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
	40	#define SCFR1_IPS_DIV 2
	41	#define SCFR1_LPC_DIV 2
	42	#define SCFR1_NFC_DIV 2
	43	#define SCFR1_DIU_DIV 240
	44
	45	#define CONFIG_MISC_INIT_R
	46
	47	#define CONFIG_SYS_IMMR 0x80000000
	48	#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
	49
	50	/* more aggressive 'mtest' over a wider address range */
	51	#define CONFIG_SYS_ALT_MEMTEST
	52	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
	53	#define CONFIG_SYS_MEMTEST_END 0x0FE00000
	54
	55	/*
	56	* DDR Setup - manually set all parameters as there's no SPD etc.
	57	*/
	58	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
	59	#define CONFIG_SYS_DDR_BASE 0x00000000
	60	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	61	#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
	62
	63	/*
b5992e77	64	* DDR Controller Configuration
fcc7fe42 AG	65	*
	66	* SYS_CFG:
	67	* [31:31] MDDRC Soft Reset: Diabled
	68	* [30:30] DRAM CKE pin: Enabled
	69	* [29:29] DRAM CLK: Enabled
	70	* [28:28] Command Mode: Enabled (For initialization only)
	71	* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
	72	* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
	73	* [20:19] Read Test: DON'T USE
	74	* [18:18] Self Refresh: Enabled
	75	* [17:17] 16bit Mode: Disabled
	76	* [16:13] Ready Delay: 2
	77	* [12:12] Half DQS Delay: Disabled
	78	* [11:11] Quarter DQS Delay: Disabled
	79	* [10:08] Write Delay: 2
	80	* [07:07] Early ODT: Disabled
	81	* [06:06] On DIE Termination: Disabled
	82	* [05:05] FIFO Overflow Clear: DON'T USE here
	83	* [04:04] FIFO Underflow Clear: DON'T USE here
	84	* [03:03] FIFO Overflow Pending: DON'T USE here
	85	* [02:02] FIFO Underlfow Pending: DON'T USE here
	86	* [01:01] FIFO Overlfow Enabled: Enabled
	87	* [00:00] FIFO Underflow Enabled: Enabled
	88	* TIME_CFG0
	89	* [31:16] DRAM Refresh Time: 0 CSB clocks
	90	* [15:8] DRAM Command Time: 0 CSB clocks
	91	* [07:00] DRAM Precharge Time: 0 CSB clocks
	92	* TIME_CFG1
	93	* [31:26] DRAM tRFC:
	94	* [25:21] DRAM tWR1:
	95	* [20:17] DRAM tWRT1:
	96	* [16:11] DRAM tDRR:
	97	* [10:05] DRAM tRC:
	98	* [04:00] DRAM tRAS:
	99	* TIME_CFG2
	100	* [31:28] DRAM tRCD:
	101	* [27:23] DRAM tFAW:
	102	* [22:19] DRAM tRTW1:
	103	* [18:15] DRAM tCCD:
	104	* [14:10] DRAM tRTP:
	105	* [09:05] DRAM tRP:
	106	* [04:00] DRAM tRPA
	107	*/
	108
	109	/*
	110	* NOTE: although this board uses DDR1 only, the common source brings defaults
	111	* for DDR2 init sequences, that's why we have to keep those here as well
	112	*/
	113
	114	/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
	115	#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) \| (3 << 3) \| (3 << 0))
	116
	117	#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
	118	\| (1 << 31) /* RST_B */ \
	119	\| (1 << 30) /* CKE */ \
	120	\| (1 << 29) /* CLK_ON */ \
	121	\| (0 << 28) /* CMD_MODE */ \
	122	\| (5 << 25) /* DRAM_ROW_SELECT */ \
	123	\| (5 << 21) /* DRAM_BANK_SELECT */ \
	124	\| (0 << 18) /* SELF_REF_EN */ \
	125	\| (0 << 17) /* 16BIT_MODE */ \
	126	\| (4 << 13) /* RDLY */ \
	127	\| (1 << 12) /* HALF_DQS_DLY */ \
	128	\| (0 << 11) /* QUART_DQS_DLY */ \
129	\| (1 << 8) /* WDLY */ \
130	\| (0 << 7) /* EARLY_ODT */ \
131	\| (0 << 6) /* ON_DIE_TERMINATE */ \
132	\| (0 << 5) /* FIFO_OV_CLEAR */ \
133	\| (0 << 4) /* FIFO_UV_CLEAR */ \
134	\| (0 << 1) /* FIFO_OV_EN */ \
135	\| (0 << 0) /* FIFO_UV_EN */ \
136	)
137
138	#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
139	#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
140	#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
141
142	/* register address only, i.e. template without values */
143	#define CONFIG_SYS_MICRON_BMODE 0x01000000
144	#define CONFIG_SYS_MICRON_EMODE 0x01010000
145	#define CONFIG_SYS_MICRON_EMODE2 0x01020000
146	#define CONFIG_SYS_MICRON_EMODE3 0x01030000
147	/*
148	* values for mode registers (without mode register address)
149	*/
150	/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
151	#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
152	#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
153	/* DLL enable, reduced drive strength */
154	#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
155
156	#define CONFIG_SYS_DDRCMD_NOP 0x01380000
157	#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
158	#define CONFIG_SYS_MICRON_EMR ((1 << 24) \| /* CMD_REQ */ \
159	(0 << 22) \| /* DRAM_CS */ \
160	(0 << 21) \| /* DRAM_RAS */ \
161	(0 << 20) \| /* DRAM_CAS */ \
162	(0 << 19) \| /* DRAM_WEB */ \
163	(1 << 16) \| /* DRAM_BS[2:0] */ \
164	(0 << 15) \| /* */ \
165	(0 << 12) \| /* A12->out */ \
166	(0 << 11) \| /* A11->RDQS */ \
167	(0 << 10) \| /* A10->DQS# */ \
168	(0 << 7) \| /* OCD program */ \
169	(0 << 6) \| /* Rtt1 */ \
170	(0 << 3) \| /* posted CAS# */ \
171	(0 << 2) \| /* Rtt0 */ \
172	(1 << 1) \| /* ODS */ \
173	(0 << 0) /* DLL */ \
174	)
175	#define CONFIG_SYS_MICRON_EMR2 0x01020000
176	#define CONFIG_SYS_MICRON_EMR3 0x01030000
177	#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
178	#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
179	#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) \| /* CMD_REQ */ \
180	(0 << 22) \| /* DRAM_CS */ \
181	(0 << 21) \| /* DRAM_RAS */ \
182	(0 << 20) \| /* DRAM_CAS */ \
183	(0 << 19) \| /* DRAM_WEB */ \
184	(1 << 16) \| /* DRAM_BS[2:0] */ \
185	(0 << 15) \| /* */ \
186	(0 << 12) \| /* A12->out */ \
187	(0 << 11) \| /* A11->RDQS */ \
188	(1 << 10) \| /* A10->DQS# */ \
189	(7 << 7) \| /* OCD program */ \
190	(0 << 6) \| /* Rtt1 */ \
191	(0 << 3) \| /* posted CAS# */ \
192	(1 << 2) \| /* Rtt0 */ \
193	(0 << 1) \| /* ODS */ \
194	(0 << 0) /* DLL */ \
195	)
196
197	/*
198	* Backward compatible definitions,
199	* so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
200	*/
201	#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
202	#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
203	#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
204	#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
205
206	/* DDR Priority Manager Configuration */
207	#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
208	#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
209	#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
210	#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
211	#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
212	#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
213	#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
214	#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
215	#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
216	#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
217	#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
218	#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
219	#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
220	#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
221	#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
222	#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
223	#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
224	#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
225	#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
226	#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
227	#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
228	#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
229	#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
230
231	/*
232	* NOR FLASH on the Local Bus
233	*/
234	#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
235	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
236	#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
237	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
238
239	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
240	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
241	#define CONFIG_SYS_FLASH_BANKS_LIST { \
242	CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
243	}
244	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
245
246	#undef CONFIG_SYS_FLASH_CHECKSUM
247	#define CONFIG_SYS_FLASH_PROTECTION
248
249	/*
250	* SRAM support
251	*/
252	#define CONFIG_SYS_SRAM_BASE 0x30000000
253	#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
254
255	/*
256	* CS related parameters
fcc7fe42 AG	257	*/
	258	/* CS0 Flash */
	259	#define CONFIG_SYS_CS0_CFG 0x00031110
	260	#define CONFIG_SYS_CS0_START 0xFC000000
	261	#define CONFIG_SYS_CS0_SIZE 0x04000000
	262	/* CS1 FRAM */
	263	#define CONFIG_SYS_CS1_CFG 0x00011000
	264	#define CONFIG_SYS_CS1_START 0xE0000000
	265	#define CONFIG_SYS_CS1_SIZE 0x00010000
	266	/* CS2 AS-i 1 */
	267	#define CONFIG_SYS_CS2_CFG 0x00009100
	268	#define CONFIG_SYS_CS2_START 0xE0100000
	269	#define CONFIG_SYS_CS2_SIZE 0x00080000
	270	/* CS3 netX */
	271	#define CONFIG_SYS_CS3_CFG 0x000A1140
	272	#define CONFIG_SYS_CS3_START 0xE0300000
	273	#define CONFIG_SYS_CS3_SIZE 0x00020000
	274	/* CS5 safety */
	275	#define CONFIG_SYS_CS5_CFG 0x0011F000
	276	#define CONFIG_SYS_CS5_START 0xE0400000
	277	#define CONFIG_SYS_CS5_SIZE 0x00010000
	278	/* CS6 AS-i 2 */
	279	#define CONFIG_SYS_CS6_CFG 0x00009100
	280	#define CONFIG_SYS_CS6_START 0xE0200000
	281	#define CONFIG_SYS_CS6_SIZE 0x00080000
	282
	283	/* Don't use alternative CS timing for any CS */
	284	#define CONFIG_SYS_CS_ALETIMING 0x00000000
	285	#define CONFIG_SYS_CS_BURST 0x00000000
	286	#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
	287	#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
	288
	289	/* Use SRAM for initial stack */
	290	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
b39d1213	291	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
fcc7fe42	292
b39d1213	293	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
627b73e2	294	GENERATED_GBL_DATA_SIZE)
fcc7fe42 AG	295	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	296
	297	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	298	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	299
	300	#ifdef CONFIG_FSL_DIU_FB
	301	#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
	302	#else
	303	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
	304	#endif
	305
	306	/*
	307	* Serial Port
	308	*/
	309	#define CONFIG_CONS_INDEX 1
	310
	311	/*
	312	* Serial console configuration
	313	*/
	314	#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
	315	#define CONFIG_SYS_PSC3
	316	#if CONFIG_PSC_CONSOLE != 3
	317	#error CONFIG_PSC_CONSOLE must be 3
	318	#endif
	319
	320	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
fcc7fe42 AG	321
	322	#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
	323	#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
	324	#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
	325	#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
	326
	327	/*
	328	* Clocks in use
	329	*/
	330	#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN \| \
	331	CLOCK_SCCR1_LPC_EN \| \
	332	CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) \| \
	333	CLOCK_SCCR1_PSC_EN(7) \| \
	334	CLOCK_SCCR1_PSCFIFO_EN \| \
	335	CLOCK_SCCR1_DDR_EN \| \
	336	CLOCK_SCCR1_FEC_EN \| \
	337	CLOCK_SCCR1_TPR_EN)
	338
	339	#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN \| \
	340	CLOCK_SCCR2_SPDIF_EN \| \
	341	CLOCK_SCCR2_DIU_EN \| \
	342	CLOCK_SCCR2_I2C_EN)
	343
fcc7fe42 AG	344	#define CONFIG_CMDLINE_EDITING 1 /* command line history */
	345
	346	/* I2C */
	347	#define CONFIG_HARD_I2C /* I2C with hardware support */
	348	#define CONFIG_I2C_MULTI_BUS
	349
	350	/* I2C speed and slave address */
	351	#define CONFIG_SYS_I2C_SPEED 100000
	352	#define CONFIG_SYS_I2C_SLAVE 0x7F
	353
83306927 BT	354	/*
	355	* IIM - IC Identification Module
	356	*/
	357	#undef CONFIG_FSL_IIM
	358
fcc7fe42 AG	359	/*
	360	* EEPROM configuration for Atmel AT24C01:
	361	* 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
	362	*/
	363	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	364	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	365	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
	366	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	367
	368	/*
	369	* Ethernet configuration
	370	*/
	371	#define CONFIG_MPC512x_FEC 1
fcc7fe42 AG	372	#define CONFIG_PHY_ADDR 0x1F
	373	#define CONFIG_MII 1 /* MII PHY management */
	374	#define CONFIG_FEC_AN_TIMEOUT 1
	375	#define CONFIG_HAS_ETH0
	376
	377	/*
	378	* Environment
	379	*/
	380	#define CONFIG_ENV_IS_IN_FLASH 1
	381	/* This has to be a multiple of the flash sector size */
	382	#define CONFIG_ENV_ADDR 0xFFF40000
	383	#define CONFIG_ENV_SIZE 0x2000
	384	#define CONFIG_ENV_SECT_SIZE 0x20000
	385
	386	/* Address and size of Redundant Environment Sector */
	387	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
	388	CONFIG_ENV_SECT_SIZE)
	389	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	390
	391	#define CONFIG_LOADS_ECHO 1
	392	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
	393
fcc7fe42 AG	394	#define CONFIG_CMD_EEPROM
fcc7fe42 AG	395	#undef CONFIG_CMD_FUSE
fcc7fe42	396	#undef CONFIG_CMD_IDE
fcc7fe42	397	#define CONFIG_CMD_JFFS2
fcc7fe42 AG	398	#define CONFIG_CMD_REGINFO
	399
	400	#if defined(CONFIG_PCI)
	401	#define CONFIG_CMD_PCI
	402	#endif
	403
	404	#if defined(CONFIG_CMD_IDE) \|\| defined(CONFIG_CMD_EXT2)
	405	#define CONFIG_DOS_PARTITION
	406	#define CONFIG_MAC_PARTITION
	407	#define CONFIG_ISO_PARTITION
	408	#endif /* defined(CONFIG_CMD_IDE) */
	409
	410	/*
	411	* Miscellaneous configurable options
	412	*/
	413	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	414	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
fcc7fe42 AG	415
	416	#ifdef CONFIG_CMD_KGDB
	417	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	418	#else
	419	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	420	#endif
	421
	422	/* Print Buffer Size */
	423	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	424	sizeof(CONFIG_SYS_PROMPT) + 16)
	425	/* max number of command args */
	426	#define CONFIG_SYS_MAXARGS 32
	427	/* Boot Argument Buffer Size */
	428	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	429
fcc7fe42 AG	430	/*
	431	* For booting Linux, the board info and command line data
	432	* have to be in the first 8 MB of memory, since this is
	433	* the maximum mapped by the Linux kernel during initialization.
	434	*/
	435	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	436
	437	/* Cache Configuration */
	438	#define CONFIG_SYS_DCACHE_SIZE 32768
	439	#define CONFIG_SYS_CACHELINE_SIZE 32
	440	#ifdef CONFIG_CMD_KGDB
	441	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
	442	#endif
	443
	444	#define CONFIG_SYS_HID0_INIT 0x000000000
	445	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	446	HID0_ICE)
	447	#define CONFIG_SYS_HID2 HID2_HBE
	448
	449	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	450
fcc7fe42 AG	451	#ifdef CONFIG_CMD_KGDB
fcc7fe42 AG	452	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
fcc7fe42 AG	453	#endif
	454
	455	/*
	456	* Environment Configuration
	457	*/
	458	#define CONFIG_ENV_OVERWRITE
	459	#define CONFIG_TIMESTAMP
	460
fcc7fe42 AG	461	/* default load addr for tftp and bootm */
	462	#define CONFIG_LOADADDR 400000
	463
fcc7fe42	464
b5992e77	465	/* the builtin environment and standard greeting */
fcc7fe42 AG	466	#define CONFIG_PREBOOT "echo;" \
	467	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	468	"echo"
	469
	470	#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
6c5001d5	471	"muster_nr=-00\0" \
fcc7fe42	472	"fromram=run ramargs addip addtty; " \
6c5001d5 GS	473	"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
	474	"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
	475	"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \
fcc7fe42 AG	476	"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
fcc7fe42 AG	477	"fromnfs=run nfsargs addip addtty; " \
6c5001d5 GS	478	"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
6c5001d5 GS	479	"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
fcc7fe42 AG	480	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	481	"fromflash=run nfsargs addip addtty; " \
	482	"bootm fc020000 - fc000000\0" \
	483	"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
	484	"recovery=run mtdargsrec addip addtty; " \
	485	"bootm ffd20000 - ffee0000\0" \
	486	"production=run ramargs addip addtty; " \
	487	"bootm fc020000 fc400000 fc000000\0" \
	488	"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
	489	"prodmtd=run mtdargs addip addtty; " \
	490	"bootm fc020000 - fc000000\0" \
	491	""
	492
	493	#define CONFIG_EXTRA_ENV_SETTINGS \
	494	"u-boot_addr_r=200000\0" \
	495	"kernel_addr_r=600000\0" \
	496	"fdt_addr_r=a00000\0" \
	497	"ramdisk_addr_r=b00000\0" \
	498	"u-boot_addr=FFF00000\0" \
	499	"kernel_addr=FC020000\0" \
	500	"fdt_addr=FC000000\0" \
	501	"ramdisk_addr=FC400000\0" \
	502	"verify=n\0" \
	503	"ramdiskfile=ac14xx/uRamdisk\0" \
	504	"u-boot=ac14xx/u-boot.bin\0" \
	505	"bootfile=ac14xx/uImage\0" \
	506	"fdtfile=ac14xx/ac14xx.dtb\0" \
fcc7fe42 AG	507	"netdev=eth0\0" \
	508	"consdev=ttyPSC0\0" \
	509	"hostname=ac14xx\0" \
	510	"nfsargs=setenv bootargs root=/dev/nfs rw " \
6c5001d5	511	"nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
fcc7fe42 AG	512	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	513	"addip=setenv bootargs ${bootargs} " \
	514	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	515	":${hostname}:${netdev}:off panic=1\0" \
	516	"addtty=setenv bootargs ${bootargs} " \
	517	"console=${consdev},${baudrate}\0" \
	518	"flash_nfs=run nfsargs addip addtty;" \
	519	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	520	"flash_self=run ramargs addip addtty;" \
	521	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	522	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	523	"tftp ${fdt_addr_r} ${fdtfile};" \
	524	"run nfsargs addip addtty;" \
	525	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	526	"net_self=tftp ${kernel_addr_r} ${bootfile};" \
	527	"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
	528	"tftp ${fdt_addr_r} ${fdtfile};" \
	529	"run ramargs addip addtty;" \
	530	"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
	531	"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
	532	"update=protect off ${u-boot_addr} +${filesize};" \
	533	"era ${u-boot_addr} +${filesize};" \
	534	"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
	535	CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
	536	"upd=run load update\0" \
	537	""
	538
	539	#define CONFIG_BOOTCOMMAND "run production"
	540
6c5001d5 GS	541	#define CONFIG_ARP_TIMEOUT 200UL
6c5001d5 GS	542
fcc7fe42 AG	543	#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
	544
	545	#define OF_CPU "PowerPC,5121@0"
	546	#define OF_SOC_COMPAT "fsl,mpc5121-immr"
	547	#define OF_TBCLK (bd->bi_busfreq / 4)
	548	#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
	549
	550	#endif /* __CONFIG_H */