[people/ms/u-boot.git] / include / configs / adp-ae3xx.h

/*
 * Copyright (C) 2011 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch-ae3xx/ae3xx.h>

/*
 * CPU and Board Configuration Options
 */
#define CONFIG_USE_INTERRUPT

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_SKIP_TRUNOFF_WATCHDOG

#define CONFIG_CMDLINE_EDITING
#define CONFIG_PANIC_HANG

#define CONFIG_ARCH_MAP_SYSMEM

#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE	0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else

#define CONFIG_SYS_TEXT_BASE	0x80000000
#endif

/*
 * Timer
 */
#define CONFIG_SYS_CLK_FREQ	39062500
#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ

/*
 * Use Externel CLOCK or PCLK
 */
#undef CONFIG_FTRTC010_EXTCLK

#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif

#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
#endif

#define TIMER_LOAD_VAL	0xffffffff

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Real Time Clock Divider
 * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
 */
#define OSC_5MHZ			(5*1000000)
#define OSC_CLK				(4*OSC_5MHZ)
#define RTC_DIV_COUNT			(0.5)	/* Why?? */

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */

/*
 * SD (MMC) controller
 */
#define CONFIG_FTSDC010_NUMBER		1
#define CONFIG_FTSDC010_SDIO

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */

/*
 * Size of malloc() pool
 */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)

/*
 * Physical Memory Map
 */
#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */

#define PHYS_SDRAM_1 \
	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */

#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		0x300000

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)

/*
 * Static memory controller configuration
 */
#define CONFIG_FTSMC020

#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
					 FTSMC020_BANK_SIZE_32M	|	\
					 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
					 FTSMC020_TPR_AST(1)	|	\
					 FTSMC020_TPR_CTW(1)	|	\
					 FTSMC020_TPR_ATI(1)	|	\
					 FTSMC020_TPR_AT2(1)	|	\
					 FTSMC020_TPR_WTC(1)	|	\
					 FTSMC020_TPR_AHT(1)	|	\
					 FTSMC020_TPR_TRNA(1))
#endif

/*
 * FLASH on ADP_AG101P is connected to BANK0
 * Just disalbe the other BANK to avoid detection error.
 */
#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(0x00)
#define FTSMC020_BANK1_TIMING	(0x00)
#endif /* CONFIG_FTSMC020 */

/*
 * FLASH and environment organization
 */
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
#endif

/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */

/* max number of memory banks */
/*
 * There are 4 banks supported for this Controller,
 * but we have only 1 bank connected to flash on board
 */
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}

/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* environments */
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		50000000
#define CONFIG_ENV_SPI_MODE		0
#define CONFIG_ENV_SECT_SIZE		0x1000
#define CONFIG_ENV_OFFSET		0x140000
#define CONFIG_ENV_SIZE			8192
#define CONFIG_ENV_OVERWRITE


/* SPI FLASH */
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		0

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)

#endif	/* __CONFIG_H */
Commit	Line	Data
b841b6e9	1	/*
	2	* Copyright (C) 2011 Andes Technology Corporation
	3	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	4	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch-ae3xx/ae3xx.h>
	13
	14	/*
	15	* CPU and Board Configuration Options
	16	*/
	17	#define CONFIG_USE_INTERRUPT
	18
	19	#define CONFIG_SKIP_LOWLEVEL_INIT
	20
	21	#define CONFIG_SKIP_TRUNOFF_WATCHDOG
	22
	23	#define CONFIG_CMDLINE_EDITING
	24	#define CONFIG_PANIC_HANG
	25
e336b73d	26	#define CONFIG_ARCH_MAP_SYSMEM
b841b6e9	27
	28	#define CONFIG_BOOTP_SEND_HOSTNAME
	29	#define CONFIG_BOOTP_SERVERIP
	30
	31	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	32	#define CONFIG_SYS_TEXT_BASE 0x00500000
	33	#ifdef CONFIG_OF_CONTROL
	34	#undef CONFIG_OF_SEPARATE
	35	#define CONFIG_OF_EMBED
	36	#endif
	37	#else
	38
	39	#define CONFIG_SYS_TEXT_BASE 0x80000000
	40	#endif
	41
	42	/*
	43	* Timer
	44	*/
	45	#define CONFIG_SYS_CLK_FREQ 39062500
	46	#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	47
	48	/*
	49	* Use Externel CLOCK or PCLK
	50	*/
	51	#undef CONFIG_FTRTC010_EXTCLK
	52
	53	#ifndef CONFIG_FTRTC010_EXTCLK
	54	#define CONFIG_FTRTC010_PCLK
	55	#endif
	56
	57	#ifdef CONFIG_FTRTC010_EXTCLK
	58	#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	59	#else
	60	#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	61	#endif
	62
	63	#define TIMER_LOAD_VAL 0xffffffff
	64
	65	/*
	66	* Real Time Clock
	67	*/
	68	#define CONFIG_RTC_FTRTC010
	69
	70	/*
	71	* Real Time Clock Divider
	72	* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	73	*/
	74	#define OSC_5MHZ (5*1000000)
	75	#define OSC_CLK (4*OSC_5MHZ)
	76	#define RTC_DIV_COUNT (0.5) /* Why?? */
	77
	78	/*
	79	* Serial console configuration
	80	*/
	81
	82	/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
	83	#define CONFIG_CONS_INDEX 1
	84	#define CONFIG_SYS_NS16550_SERIAL
	85	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
	86	#ifndef CONFIG_DM_SERIAL
	87	#define CONFIG_SYS_NS16550_REG_SIZE -4
	88	#endif
	89	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
	90
b841b6e9	91	/*
	92	* SD (MMC) controller
	93	*/
b841b6e9	94	#define CONFIG_FTSDC010_NUMBER 1
	95	#define CONFIG_FTSDC010_SDIO
	96
	97	/*
	98	* Miscellaneous configurable options
	99	*/
	100	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b841b6e9	101
b841b6e9	102	/*
	103	* Size of malloc() pool
	104	*/
	105	/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
	106	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	107
	108	/*
	109	* Physical Memory Map
	110	*/
	111	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	112
	113	#define PHYS_SDRAM_1 \
	114	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
	115
	116	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
	117
	118	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	119	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	120
	121	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	122
	123	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	124	GENERATED_GBL_DATA_SIZE)
	125
	126	/*
	127	* Load address and memory test area should agree with
	128	* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
	129	*/
	130	#define CONFIG_SYS_LOAD_ADDR 0x300000
	131
	132	/* memtest works on 63 MB in DRAM */
	133	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
	134	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
	135
	136	/*
	137	* Static memory controller configuration
	138	*/
	139	#define CONFIG_FTSMC020
	140
	141	#ifdef CONFIG_FTSMC020
	142	#include <faraday/ftsmc020.h>
	143
	144	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	145	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	146	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	147	}
	148
	149	#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
	150	#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE \| \
	151	FTSMC020_BANK_SIZE_32M \| \
	152	FTSMC020_BANK_MBW_32)
	153
	154	#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE \| \
	155	FTSMC020_TPR_AST(1) \| \
	156	FTSMC020_TPR_CTW(1) \| \
	157	FTSMC020_TPR_ATI(1) \| \
	158	FTSMC020_TPR_AT2(1) \| \
	159	FTSMC020_TPR_WTC(1) \| \
	160	FTSMC020_TPR_AHT(1) \| \
	161	FTSMC020_TPR_TRNA(1))
	162	#endif
	163
	164	/*
	165	* FLASH on ADP_AG101P is connected to BANK0
166	* Just disalbe the other BANK to avoid detection error.
167	*/
168	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
169	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
170	FTSMC020_BANK_SIZE_32M \| \
171	FTSMC020_BANK_MBW_32)
172
173	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) \| \
174	FTSMC020_TPR_CTW(3) \| \
175	FTSMC020_TPR_ATI(0xf) \| \
176	FTSMC020_TPR_AT2(3) \| \
177	FTSMC020_TPR_WTC(3) \| \
178	FTSMC020_TPR_AHT(3) \| \
179	FTSMC020_TPR_TRNA(0xf))
180
181	#define FTSMC020_BANK1_CONFIG (0x00)
182	#define FTSMC020_BANK1_TIMING (0x00)
183	#endif /* CONFIG_FTSMC020 */
184
185	/*
186	* FLASH and environment organization
187	*/
188	/* use CFI framework */
189	#define CONFIG_SYS_FLASH_CFI
190	#define CONFIG_FLASH_CFI_DRIVER
191
192	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
193	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
194	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
195
196	/* support JEDEC */
197	#ifdef CONFIG_CFI_FLASH
198	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
199	#endif
200
201	/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
202	#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
203	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
204	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
205	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
206
207	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
208	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
209
210	/* max number of memory banks */
211	/*
212	* There are 4 banks supported for this Controller,
213	* but we have only 1 bank connected to flash on board
214	*/
215	#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
216	#define CONFIG_SYS_MAX_FLASH_BANKS 1
217	#endif
218	#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
219
220	/* max number of sectors on one chip */
221	#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
b841b6e9	222	#define CONFIG_SYS_MAX_FLASH_SECT 512
	223
	224	/* environments */
7b1a50b7	225	#define CONFIG_ENV_SPI_BUS 0
	226	#define CONFIG_ENV_SPI_CS 0
	227	#define CONFIG_ENV_SPI_MAX_HZ 50000000
	228	#define CONFIG_ENV_SPI_MODE 0
	229	#define CONFIG_ENV_SECT_SIZE 0x1000
	230	#define CONFIG_ENV_OFFSET 0x140000
b841b6e9	231	#define CONFIG_ENV_SIZE 8192
	232	#define CONFIG_ENV_OVERWRITE
	233
7b1a50b7	234
	235	/* SPI FLASH */
	236	#define CONFIG_SF_DEFAULT_BUS 0
	237	#define CONFIG_SF_DEFAULT_CS 0
	238	#define CONFIG_SF_DEFAULT_SPEED 1000000
	239	#define CONFIG_SF_DEFAULT_MODE 0
	240
b841b6e9	241	/*
	242	* For booting Linux, the board info and command line data
	243	* have to be in the first 16 MB of memory, since this is
	244	* the maximum mapped by the Linux kernel during initialization.
	245	*/
	246
	247	/* Initial Memory map for Linux*/
	248	#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
	249	/* Increase max gunzip size */
	250	#define CONFIG_SYS_BOOTM_LEN (64 << 20)
	251
	252	#endif /* __CONFIG_H */