[people/ms/u-boot.git] / include / configs / adp-ae3xx.h

/*
 * Copyright (C) 2011 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch-ae3xx/ae3xx.h>

/*
 * CPU and Board Configuration Options
 */
#define CONFIG_USE_INTERRUPT

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_SKIP_TRUNOFF_WATCHDOG

#define CONFIG_ARCH_MAP_SYSMEM

#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#endif

/*
 * Timer
 */
#define CONFIG_SYS_CLK_FREQ	39062500
#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ

/*
 * Use Externel CLOCK or PCLK
 */
#undef CONFIG_FTRTC010_EXTCLK

#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif

#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
#endif

#define TIMER_LOAD_VAL	0xffffffff

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Real Time Clock Divider
 * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
 */
#define OSC_5MHZ			(5*1000000)
#define OSC_CLK				(4*OSC_5MHZ)
#define RTC_DIV_COUNT			(0.5)	/* Why?? */

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */

/*
 * SD (MMC) controller
 */
#define CONFIG_FTSDC010_NUMBER		1
#define CONFIG_FTSDC010_SDIO

/*
 * Miscellaneous configurable options
 */

/*
 * Size of malloc() pool
 */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)

/*
 * Physical Memory Map
 */
#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */

#define PHYS_SDRAM_1 \
	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */

#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		0x300000

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)

/*
 * Static memory controller configuration
 */
#define CONFIG_FTSMC020

#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
					 FTSMC020_BANK_SIZE_32M	|	\
					 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
					 FTSMC020_TPR_AST(1)	|	\
					 FTSMC020_TPR_CTW(1)	|	\
					 FTSMC020_TPR_ATI(1)	|	\
					 FTSMC020_TPR_AT2(1)	|	\
					 FTSMC020_TPR_WTC(1)	|	\
					 FTSMC020_TPR_AHT(1)	|	\
					 FTSMC020_TPR_TRNA(1))
#endif

/*
 * FLASH on ADP_AG101P is connected to BANK0
 * Just disalbe the other BANK to avoid detection error.
 */
#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(0x00)
#define FTSMC020_BANK1_TIMING	(0x00)
#endif /* CONFIG_FTSMC020 */

/*
 * FLASH and environment organization
 */
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
#endif

/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */

/* max number of memory banks */
/*
 * There are 4 banks supported for this Controller,
 * but we have only 1 bank connected to flash on board
 */
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}

/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* environments */
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		50000000
#define CONFIG_ENV_SPI_MODE		0
#define CONFIG_ENV_SECT_SIZE		0x1000
#define CONFIG_ENV_OFFSET		0x140000
#define CONFIG_ENV_SIZE			8192
#define CONFIG_ENV_OVERWRITE


/* SPI FLASH */
#define CONFIG_SF_DEFAULT_BUS		0
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		0

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)

#endif	/* __CONFIG_H */
Commit	Line	Data
b841b6e9	1	/*
	2	* Copyright (C) 2011 Andes Technology Corporation
	3	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	4	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch-ae3xx/ae3xx.h>
	13
	14	/*
	15	* CPU and Board Configuration Options
	16	*/
	17	#define CONFIG_USE_INTERRUPT
	18
	19	#define CONFIG_SKIP_LOWLEVEL_INIT
	20
	21	#define CONFIG_SKIP_TRUNOFF_WATCHDOG
	22
e336b73d	23	#define CONFIG_ARCH_MAP_SYSMEM
b841b6e9	24
	25	#define CONFIG_BOOTP_SEND_HOSTNAME
	26	#define CONFIG_BOOTP_SERVERIP
	27
	28	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
b841b6e9	29	#ifdef CONFIG_OF_CONTROL
	30	#undef CONFIG_OF_SEPARATE
	31	#define CONFIG_OF_EMBED
	32	#endif
b841b6e9	33	#endif
	34
	35	/*
	36	* Timer
	37	*/
	38	#define CONFIG_SYS_CLK_FREQ 39062500
	39	#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	40
	41	/*
	42	* Use Externel CLOCK or PCLK
	43	*/
	44	#undef CONFIG_FTRTC010_EXTCLK
	45
	46	#ifndef CONFIG_FTRTC010_EXTCLK
	47	#define CONFIG_FTRTC010_PCLK
	48	#endif
	49
	50	#ifdef CONFIG_FTRTC010_EXTCLK
	51	#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	52	#else
	53	#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	54	#endif
	55
	56	#define TIMER_LOAD_VAL 0xffffffff
	57
	58	/*
	59	* Real Time Clock
	60	*/
	61	#define CONFIG_RTC_FTRTC010
	62
	63	/*
	64	* Real Time Clock Divider
	65	* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	66	*/
	67	#define OSC_5MHZ (5*1000000)
	68	#define OSC_CLK (4*OSC_5MHZ)
	69	#define RTC_DIV_COUNT (0.5) /* Why?? */
	70
	71	/*
	72	* Serial console configuration
	73	*/
	74
	75	/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
	76	#define CONFIG_CONS_INDEX 1
	77	#define CONFIG_SYS_NS16550_SERIAL
	78	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
	79	#ifndef CONFIG_DM_SERIAL
	80	#define CONFIG_SYS_NS16550_REG_SIZE -4
	81	#endif
	82	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
	83
b841b6e9	84	/*
	85	* SD (MMC) controller
	86	*/
b841b6e9	87	#define CONFIG_FTSDC010_NUMBER 1
	88	#define CONFIG_FTSDC010_SDIO
	89
	90	/*
	91	* Miscellaneous configurable options
	92	*/
b841b6e9	93
b841b6e9	94	/*
	95	* Size of malloc() pool
	96	*/
	97	/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
	98	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	99
	100	/*
	101	* Physical Memory Map
	102	*/
	103	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	104
	105	#define PHYS_SDRAM_1 \
	106	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
	107
	108	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
	109
	110	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	111	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	112
	113	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	114
	115	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	116	GENERATED_GBL_DATA_SIZE)
	117
	118	/*
	119	* Load address and memory test area should agree with
	120	* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
	121	*/
	122	#define CONFIG_SYS_LOAD_ADDR 0x300000
	123
	124	/* memtest works on 63 MB in DRAM */
	125	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
	126	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
	127
	128	/*
	129	* Static memory controller configuration
	130	*/
	131	#define CONFIG_FTSMC020
	132
	133	#ifdef CONFIG_FTSMC020
	134	#include <faraday/ftsmc020.h>
	135
	136	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	137	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	138	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	139	}
	140
	141	#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
	142	#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE \| \
	143	FTSMC020_BANK_SIZE_32M \| \
	144	FTSMC020_BANK_MBW_32)
	145
	146	#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE \| \
	147	FTSMC020_TPR_AST(1) \| \
	148	FTSMC020_TPR_CTW(1) \| \
	149	FTSMC020_TPR_ATI(1) \| \
	150	FTSMC020_TPR_AT2(1) \| \
	151	FTSMC020_TPR_WTC(1) \| \
	152	FTSMC020_TPR_AHT(1) \| \
	153	FTSMC020_TPR_TRNA(1))
	154	#endif
	155
	156	/*
	157	* FLASH on ADP_AG101P is connected to BANK0
158	* Just disalbe the other BANK to avoid detection error.
159	*/
160	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
161	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
162	FTSMC020_BANK_SIZE_32M \| \
163	FTSMC020_BANK_MBW_32)
164
165	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) \| \
166	FTSMC020_TPR_CTW(3) \| \
167	FTSMC020_TPR_ATI(0xf) \| \
168	FTSMC020_TPR_AT2(3) \| \
169	FTSMC020_TPR_WTC(3) \| \
170	FTSMC020_TPR_AHT(3) \| \
171	FTSMC020_TPR_TRNA(0xf))
172
173	#define FTSMC020_BANK1_CONFIG (0x00)
174	#define FTSMC020_BANK1_TIMING (0x00)
175	#endif /* CONFIG_FTSMC020 */
176
177	/*
178	* FLASH and environment organization
179	*/
180	/* use CFI framework */
181	#define CONFIG_SYS_FLASH_CFI
182	#define CONFIG_FLASH_CFI_DRIVER
183
184	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
185	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
186	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
187
188	/* support JEDEC */
189	#ifdef CONFIG_CFI_FLASH
190	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
191	#endif
192
193	/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
194	#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
195	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
196	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
197	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
198
199	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
200	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
201
202	/* max number of memory banks */
203	/*
204	* There are 4 banks supported for this Controller,
205	* but we have only 1 bank connected to flash on board
206	*/
207	#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
208	#define CONFIG_SYS_MAX_FLASH_BANKS 1
209	#endif
210	#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
211
212	/* max number of sectors on one chip */
213	#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
b841b6e9	214	#define CONFIG_SYS_MAX_FLASH_SECT 512
	215
	216	/* environments */
7b1a50b7	217	#define CONFIG_ENV_SPI_BUS 0
	218	#define CONFIG_ENV_SPI_CS 0
	219	#define CONFIG_ENV_SPI_MAX_HZ 50000000
	220	#define CONFIG_ENV_SPI_MODE 0
	221	#define CONFIG_ENV_SECT_SIZE 0x1000
	222	#define CONFIG_ENV_OFFSET 0x140000
b841b6e9	223	#define CONFIG_ENV_SIZE 8192
	224	#define CONFIG_ENV_OVERWRITE
	225
7b1a50b7	226
	227	/* SPI FLASH */
	228	#define CONFIG_SF_DEFAULT_BUS 0
	229	#define CONFIG_SF_DEFAULT_CS 0
	230	#define CONFIG_SF_DEFAULT_SPEED 1000000
	231	#define CONFIG_SF_DEFAULT_MODE 0
	232
b841b6e9	233	/*
	234	* For booting Linux, the board info and command line data
	235	* have to be in the first 16 MB of memory, since this is
	236	* the maximum mapped by the Linux kernel during initialization.
	237	*/
	238
	239	/* Initial Memory map for Linux*/
	240	#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
	241	/* Increase max gunzip size */
	242	#define CONFIG_SYS_BOOTM_LEN (64 << 20)
	243
	244	#endif /* __CONFIG_H */