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5f1719c1 ML |
1 | /* |
2 | * Copyright (C) 2011 Andes Technology Corporation | |
3 | * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> | |
4 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5f1719c1 ML |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include <asm/arch/ag101.h> | |
13 | ||
14 | /* | |
15 | * CPU and Board Configuration Options | |
16 | */ | |
17 | #define CONFIG_ADP_AG101 | |
18 | ||
19 | #define CONFIG_USE_INTERRUPT | |
20 | ||
21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
22 | ||
e3c58b02 | 23 | /* |
24 | * Definitions related to passing arguments to kernel. | |
25 | */ | |
26 | #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ | |
27 | #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ | |
28 | #define CONFIG_INITRD_TAG /* send initrd params */ | |
29 | ||
5f1719c1 ML |
30 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
31 | #define CONFIG_MEM_REMAP | |
32 | #endif | |
33 | ||
34 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
35 | #define CONFIG_SYS_TEXT_BASE 0x03200000 | |
36 | #else | |
37 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
38 | #endif | |
39 | ||
40 | /* | |
41 | * Timer | |
42 | */ | |
5f1719c1 ML |
43 | #define CONFIG_SYS_CLK_FREQ 48000000 |
44 | #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ | |
45 | ||
46 | /* | |
47 | * Use Externel CLOCK or PCLK | |
48 | */ | |
49 | #undef CONFIG_FTRTC010_EXTCLK | |
50 | ||
51 | #ifndef CONFIG_FTRTC010_EXTCLK | |
52 | #define CONFIG_FTRTC010_PCLK | |
53 | #endif | |
54 | ||
55 | #ifdef CONFIG_FTRTC010_EXTCLK | |
56 | #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ | |
57 | #else | |
58 | #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ | |
59 | #endif | |
60 | ||
61 | #define TIMER_LOAD_VAL 0xffffffff | |
62 | ||
63 | /* | |
64 | * Real Time Clock | |
65 | */ | |
66 | #define CONFIG_RTC_FTRTC010 | |
67 | ||
68 | /* | |
69 | * Real Time Clock Divider | |
70 | * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) | |
71 | */ | |
72 | #define OSC_5MHZ (5*1000000) | |
73 | #define OSC_CLK (2*OSC_5MHZ) | |
74 | #define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) | |
75 | ||
76 | /* | |
77 | * Serial console configuration | |
78 | */ | |
79 | ||
80 | /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ | |
81 | #define CONFIG_BAUDRATE 38400 | |
82 | #define CONFIG_CONS_INDEX 1 | |
83 | #define CONFIG_SYS_NS16550 | |
84 | #define CONFIG_SYS_NS16550_SERIAL | |
85 | #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE | |
86 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
87 | #define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */ | |
88 | ||
5f1719c1 ML |
89 | /* |
90 | * Ethernet | |
91 | */ | |
92 | #define CONFIG_FTMAC100 | |
93 | ||
94 | #define CONFIG_BOOTDELAY 3 | |
95 | ||
96 | /* | |
97 | * SD (MMC) controller | |
98 | */ | |
99 | #define CONFIG_MMC | |
100 | #define CONFIG_CMD_MMC | |
101 | #define CONFIG_GENERIC_MMC | |
102 | #define CONFIG_DOS_PARTITION | |
103 | #define CONFIG_FTSDC010 | |
104 | #define CONFIG_FTSDC010_NUMBER 1 | |
61ccf082 | 105 | #define CONFIG_FTSDC010_SDIO |
5f1719c1 | 106 | #define CONFIG_CMD_FAT |
61ccf082 | 107 | #define CONFIG_CMD_EXT2 |
5f1719c1 ML |
108 | |
109 | /* | |
110 | * Command line configuration. | |
111 | */ | |
5f1719c1 ML |
112 | #define CONFIG_CMD_CACHE |
113 | #define CONFIG_CMD_DATE | |
114 | #define CONFIG_CMD_PING | |
115 | ||
116 | /* | |
117 | * Miscellaneous configurable options | |
118 | */ | |
119 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
120 | #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ | |
121 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
122 | ||
123 | /* Print Buffer Size */ | |
124 | #define CONFIG_SYS_PBSIZE \ | |
125 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
126 | ||
127 | /* max number of command args */ | |
128 | #define CONFIG_SYS_MAXARGS 16 | |
129 | ||
130 | /* Boot Argument Buffer Size */ | |
131 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
132 | ||
5f1719c1 ML |
133 | /* |
134 | * Size of malloc() pool | |
135 | */ | |
136 | /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ | |
137 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) | |
138 | ||
5f1719c1 ML |
139 | /* |
140 | * AHB Controller configuration | |
141 | */ | |
142 | #define CONFIG_FTAHBC020S | |
143 | ||
144 | #ifdef CONFIG_FTAHBC020S | |
145 | #include <faraday/ftahbc020s.h> | |
146 | ||
147 | /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ | |
148 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 | |
149 | ||
150 | /* | |
151 | * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, | |
152 | * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote | |
153 | * in C language. | |
154 | */ | |
155 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ | |
156 | (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ | |
157 | FTAHBC020S_SLAVE_BSR_SIZE(0xb)) | |
158 | #endif | |
159 | ||
160 | /* | |
161 | * Watchdog | |
162 | */ | |
163 | #define CONFIG_FTWDT010_WATCHDOG | |
164 | ||
165 | /* | |
166 | * PMU Power controller configuration | |
167 | */ | |
168 | #define CONFIG_PMU | |
169 | #define CONFIG_FTPMU010_POWER | |
170 | ||
171 | #ifdef CONFIG_FTPMU010_POWER | |
172 | #include <faraday/ftpmu010.h> | |
173 | #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E | |
174 | #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ | |
175 | FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ | |
176 | FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ | |
177 | FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ | |
178 | FTPMU010_SDRAMHTC_CKE_DCSR | \ | |
179 | FTPMU010_SDRAMHTC_DQM_DCSR | \ | |
180 | FTPMU010_SDRAMHTC_SDCLK_DCSR) | |
181 | #endif | |
182 | ||
183 | /* | |
184 | * SDRAM controller configuration | |
185 | */ | |
186 | #define CONFIG_FTSDMC021 | |
187 | ||
188 | #ifdef CONFIG_FTSDMC021 | |
189 | #include <faraday/ftsdmc021.h> | |
190 | ||
191 | #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \ | |
192 | FTSDMC021_TP1_TRCD(1) | \ | |
193 | FTSDMC021_TP1_TRF(3) | \ | |
194 | FTSDMC021_TP1_TWR(1) | \ | |
195 | FTSDMC021_TP1_TCL(2)) | |
196 | ||
197 | #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ | |
198 | FTSDMC021_TP2_INI_REFT(8) | \ | |
199 | FTSDMC021_TP2_REF_INTV(0x180)) | |
200 | ||
201 | /* | |
202 | * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, | |
203 | * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in | |
204 | * C language. | |
205 | */ | |
206 | #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ | |
207 | FTSDMC021_CR1_DSZ(3) | \ | |
208 | FTSDMC021_CR1_MBW(2) | \ | |
209 | FTSDMC021_CR1_BNKSIZE(6)) | |
210 | ||
211 | #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ | |
212 | FTSDMC021_CR2_IREF | \ | |
213 | FTSDMC021_CR2_ISMR) | |
214 | ||
215 | #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE | |
216 | #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ | |
217 | CONFIG_SYS_FTSDMC021_BANK0_BASE) | |
218 | ||
3c016704 | 219 | #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ |
220 | (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) | |
221 | #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ | |
222 | CONFIG_SYS_FTSDMC021_BANK1_BASE) | |
223 | ||
5f1719c1 ML |
224 | #endif |
225 | ||
226 | /* | |
227 | * Physical Memory Map | |
228 | */ | |
229 | #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) | |
230 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ | |
231 | #if defined(CONFIG_MEM_REMAP) | |
232 | #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ | |
233 | #endif | |
234 | #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ | |
235 | #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ | |
236 | #endif | |
3c016704 | 237 | #define PHYS_SDRAM_1 \ |
238 | (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ | |
5f1719c1 | 239 | |
3c016704 | 240 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ |
5f1719c1 | 241 | #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ |
3c016704 | 242 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
5f1719c1 ML |
243 | |
244 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 | |
245 | ||
246 | #ifdef CONFIG_MEM_REMAP | |
247 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ | |
248 | GENERATED_GBL_DATA_SIZE) | |
249 | #else | |
250 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
251 | GENERATED_GBL_DATA_SIZE) | |
252 | #endif /* CONFIG_MEM_REMAP */ | |
253 | ||
254 | /* | |
255 | * Load address and memory test area should agree with | |
256 | * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. | |
257 | */ | |
258 | #define CONFIG_SYS_LOAD_ADDR 0x300000 | |
259 | ||
260 | /* memtest works on 63 MB in DRAM */ | |
261 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 | |
262 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) | |
263 | ||
264 | /* | |
265 | * Static memory controller configuration | |
266 | */ | |
267 | #define CONFIG_FTSMC020 | |
268 | ||
269 | #ifdef CONFIG_FTSMC020 | |
270 | #include <faraday/ftsmc020.h> | |
271 | ||
272 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
273 | #define CONFIG_SYS_FTSMC020_CONFIGS { \ | |
274 | { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ | |
275 | { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ | |
276 | } | |
277 | #else | |
278 | #define CONFIG_SYS_FTSMC020_CONFIGS { \ | |
279 | { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ | |
280 | } | |
281 | #endif | |
282 | ||
283 | /* | |
284 | * There are 2 bank connected to FTSMC020 on ADP-AG101. | |
285 | * You can use jumper and switch to force it booted from ROM or FLASH. | |
286 | * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH. | |
287 | * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled. | |
288 | */ | |
289 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ | |
290 | #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ | |
291 | FTSMC020_BANK_SIZE_32M | \ | |
292 | FTSMC020_BANK_MBW_32) | |
293 | ||
294 | #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ | |
295 | FTSMC020_TPR_AST(1) | \ | |
296 | FTSMC020_TPR_CTW(1) | \ | |
297 | FTSMC020_TPR_ATI(1) | \ | |
298 | FTSMC020_TPR_AT2(1) | \ | |
299 | FTSMC020_TPR_WTC(1) | \ | |
300 | FTSMC020_TPR_AHT(1) | \ | |
301 | FTSMC020_TPR_TRNA(1)) | |
302 | #endif | |
303 | ||
304 | /* | |
305 | * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0. | |
306 | * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM, | |
307 | * Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition. | |
308 | * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH. | |
309 | */ | |
310 | #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \ | |
311 | FTSMC020_BANK_MBW_32) | |
312 | ||
313 | #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ | |
314 | FTSMC020_TPR_AST(3) | \ | |
315 | FTSMC020_TPR_CTW(3) | \ | |
316 | FTSMC020_TPR_ATI(0xf) | \ | |
317 | FTSMC020_TPR_AT2(3) | \ | |
318 | FTSMC020_TPR_WTC(3) | \ | |
319 | FTSMC020_TPR_AHT(3) | \ | |
320 | FTSMC020_TPR_TRNA(0xf)) | |
321 | ||
322 | #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ | |
323 | FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ | |
324 | FTSMC020_BANK_SIZE_32M | \ | |
325 | FTSMC020_BANK_MBW_32) | |
326 | ||
327 | #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \ | |
328 | FTSMC020_TPR_AST(1) | \ | |
329 | FTSMC020_TPR_CTW(1) | \ | |
330 | FTSMC020_TPR_ATI(1) | \ | |
331 | FTSMC020_TPR_AT2(1) | \ | |
332 | FTSMC020_TPR_WTC(1) | \ | |
333 | FTSMC020_TPR_AHT(1) | \ | |
334 | FTSMC020_TPR_TRNA(1)) | |
335 | #endif /* CONFIG_FTSMC020 */ | |
336 | ||
337 | /* | |
338 | * FLASH and environment organization | |
339 | */ | |
340 | /* use CFI framework */ | |
341 | #define CONFIG_SYS_FLASH_CFI | |
342 | #define CONFIG_FLASH_CFI_DRIVER | |
343 | ||
344 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
345 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
346 | ||
347 | /* support JEDEC */ | |
348 | ||
349 | /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ | |
350 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
351 | #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ | |
352 | #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ | |
353 | #ifdef CONFIG_MEM_REMAP | |
354 | #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ | |
355 | #else | |
356 | #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ | |
357 | #endif /* CONFIG_MEM_REMAP */ | |
358 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ | |
359 | ||
360 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
361 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } | |
362 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
363 | ||
364 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ | |
365 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ | |
366 | ||
367 | /* max number of memory banks */ | |
368 | /* | |
369 | * There are 4 banks supported for this Controller, | |
370 | * but we have only 1 bank connected to flash on board | |
371 | */ | |
372 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
373 | ||
374 | /* max number of sectors on one chip */ | |
375 | #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) | |
376 | #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE | |
377 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
378 | ||
379 | /* environments */ | |
380 | #define CONFIG_ENV_IS_IN_FLASH | |
381 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) | |
382 | #define CONFIG_ENV_SIZE 8192 | |
383 | #define CONFIG_ENV_OVERWRITE | |
384 | ||
385 | #endif /* __CONFIG_H */ |