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6cb144bc ML |
1 | /* |
2 | * Copyright (C) 2011 Andes Technology Corporation | |
3 | * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> | |
4 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6cb144bc ML |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
7e3f94e1 | 12 | #include <asm/arch-ag101/ag101.h> |
6cb144bc ML |
13 | |
14 | /* | |
15 | * CPU and Board Configuration Options | |
16 | */ | |
17 | #define CONFIG_ADP_AG101P | |
18 | ||
19 | #define CONFIG_USE_INTERRUPT | |
20 | ||
21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
22 | ||
2e88bb28 KHH |
23 | #define CONFIG_SYS_GENERIC_GLOBAL_DATA |
24 | ||
e3c58b02 | 25 | /* |
26 | * Definitions related to passing arguments to kernel. | |
27 | */ | |
28 | #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ | |
29 | #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ | |
30 | #define CONFIG_INITRD_TAG /* send initrd params */ | |
31 | ||
6cb144bc ML |
32 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
33 | #define CONFIG_MEM_REMAP | |
34 | #endif | |
35 | ||
36 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
2e88bb28 KHH |
37 | #define CONFIG_SYS_TEXT_BASE 0x00500000 |
38 | #else | |
39 | #ifdef CONFIG_MEM_REMAP | |
40 | #define CONFIG_SYS_TEXT_BASE 0x80000000 | |
6cb144bc ML |
41 | #else |
42 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
43 | #endif | |
2e88bb28 | 44 | #endif |
6cb144bc ML |
45 | |
46 | /* | |
47 | * Timer | |
48 | */ | |
6cb144bc ML |
49 | #define CONFIG_SYS_CLK_FREQ 39062500 |
50 | #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ | |
51 | ||
52 | /* | |
53 | * Use Externel CLOCK or PCLK | |
54 | */ | |
55 | #undef CONFIG_FTRTC010_EXTCLK | |
56 | ||
57 | #ifndef CONFIG_FTRTC010_EXTCLK | |
58 | #define CONFIG_FTRTC010_PCLK | |
59 | #endif | |
60 | ||
61 | #ifdef CONFIG_FTRTC010_EXTCLK | |
62 | #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ | |
63 | #else | |
64 | #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ | |
65 | #endif | |
66 | ||
67 | #define TIMER_LOAD_VAL 0xffffffff | |
68 | ||
69 | /* | |
70 | * Real Time Clock | |
71 | */ | |
72 | #define CONFIG_RTC_FTRTC010 | |
73 | ||
74 | /* | |
75 | * Real Time Clock Divider | |
76 | * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) | |
77 | */ | |
78 | #define OSC_5MHZ (5*1000000) | |
79 | #define OSC_CLK (4*OSC_5MHZ) | |
80 | #define RTC_DIV_COUNT (0.5) /* Why?? */ | |
81 | ||
82 | /* | |
83 | * Serial console configuration | |
84 | */ | |
85 | ||
86 | /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ | |
87 | #define CONFIG_BAUDRATE 38400 | |
88 | #define CONFIG_CONS_INDEX 1 | |
6cb144bc ML |
89 | #define CONFIG_SYS_NS16550_SERIAL |
90 | #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE | |
91 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
92 | #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ | |
93 | ||
6cb144bc ML |
94 | /* |
95 | * Ethernet | |
96 | */ | |
97 | #define CONFIG_FTMAC100 | |
98 | ||
6cb144bc ML |
99 | |
100 | /* | |
101 | * SD (MMC) controller | |
102 | */ | |
6cb144bc ML |
103 | #define CONFIG_GENERIC_MMC |
104 | #define CONFIG_DOS_PARTITION | |
105 | #define CONFIG_FTSDC010 | |
106 | #define CONFIG_FTSDC010_NUMBER 1 | |
61ccf082 | 107 | #define CONFIG_FTSDC010_SDIO |
6cb144bc ML |
108 | |
109 | /* | |
110 | * Command line configuration. | |
111 | */ | |
6cb144bc | 112 | #define CONFIG_CMD_DATE |
6cb144bc ML |
113 | |
114 | /* | |
115 | * Miscellaneous configurable options | |
116 | */ | |
117 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
6cb144bc ML |
118 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
119 | ||
120 | /* Print Buffer Size */ | |
121 | #define CONFIG_SYS_PBSIZE \ | |
122 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
123 | ||
124 | /* max number of command args */ | |
125 | #define CONFIG_SYS_MAXARGS 16 | |
126 | ||
127 | /* Boot Argument Buffer Size */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
129 | ||
6cb144bc ML |
130 | /* |
131 | * Size of malloc() pool | |
132 | */ | |
133 | /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ | |
134 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) | |
135 | ||
6cb144bc ML |
136 | /* |
137 | * AHB Controller configuration | |
138 | */ | |
139 | #define CONFIG_FTAHBC020S | |
140 | ||
141 | #ifdef CONFIG_FTAHBC020S | |
142 | #include <faraday/ftahbc020s.h> | |
143 | ||
144 | /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ | |
145 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 | |
146 | ||
147 | /* | |
148 | * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, | |
149 | * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote | |
150 | * in C language. | |
151 | */ | |
152 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ | |
153 | (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ | |
154 | FTAHBC020S_SLAVE_BSR_SIZE(0xb)) | |
155 | #endif | |
156 | ||
157 | /* | |
158 | * Watchdog | |
159 | */ | |
160 | #define CONFIG_FTWDT010_WATCHDOG | |
161 | ||
162 | /* | |
163 | * PMU Power controller configuration | |
164 | */ | |
165 | #define CONFIG_PMU | |
166 | #define CONFIG_FTPMU010_POWER | |
167 | ||
168 | #ifdef CONFIG_FTPMU010_POWER | |
169 | #include <faraday/ftpmu010.h> | |
170 | #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E | |
171 | #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ | |
172 | FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ | |
173 | FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ | |
174 | FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ | |
175 | FTPMU010_SDRAMHTC_CKE_DCSR | \ | |
176 | FTPMU010_SDRAMHTC_DQM_DCSR | \ | |
177 | FTPMU010_SDRAMHTC_SDCLK_DCSR) | |
178 | #endif | |
179 | ||
180 | /* | |
181 | * SDRAM controller configuration | |
182 | */ | |
183 | #define CONFIG_FTSDMC021 | |
184 | ||
185 | #ifdef CONFIG_FTSDMC021 | |
186 | #include <faraday/ftsdmc021.h> | |
187 | ||
188 | #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ | |
189 | FTSDMC021_TP1_TRP(1) | \ | |
190 | FTSDMC021_TP1_TRCD(1) | \ | |
191 | FTSDMC021_TP1_TRF(3) | \ | |
192 | FTSDMC021_TP1_TWR(1) | \ | |
193 | FTSDMC021_TP1_TCL(2)) | |
194 | ||
195 | #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ | |
196 | FTSDMC021_TP2_INI_REFT(8) | \ | |
197 | FTSDMC021_TP2_REF_INTV(0x180)) | |
198 | ||
199 | /* | |
200 | * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, | |
201 | * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in | |
202 | * C language. | |
203 | */ | |
204 | #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ | |
205 | FTSDMC021_CR1_DSZ(3) | \ | |
206 | FTSDMC021_CR1_MBW(2) | \ | |
207 | FTSDMC021_CR1_BNKSIZE(6)) | |
208 | ||
209 | #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ | |
210 | FTSDMC021_CR2_IREF | \ | |
211 | FTSDMC021_CR2_ISMR) | |
212 | ||
213 | #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE | |
214 | #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ | |
215 | CONFIG_SYS_FTSDMC021_BANK0_BASE) | |
216 | ||
3c016704 | 217 | #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ |
218 | (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) | |
219 | #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ | |
220 | CONFIG_SYS_FTSDMC021_BANK1_BASE) | |
6cb144bc ML |
221 | #endif |
222 | ||
223 | /* | |
224 | * Physical Memory Map | |
225 | */ | |
2e88bb28 KHH |
226 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT |
227 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ | |
228 | #else | |
229 | #ifdef CONFIG_MEM_REMAP | |
230 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ | |
231 | #else | |
232 | #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ | |
6cb144bc | 233 | #endif |
6cb144bc | 234 | #endif |
2e88bb28 | 235 | |
3c016704 | 236 | #define PHYS_SDRAM_1 \ |
237 | (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ | |
6cb144bc | 238 | |
3c016704 | 239 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ |
2e88bb28 KHH |
240 | |
241 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
242 | #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ | |
243 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ | |
244 | #else | |
245 | #ifdef CONFIG_MEM_REMAP | |
246 | #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ | |
247 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ | |
248 | #else | |
249 | #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ | |
250 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ | |
251 | #endif | |
252 | #endif | |
6cb144bc ML |
253 | |
254 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 | |
255 | ||
256 | #ifdef CONFIG_MEM_REMAP | |
257 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ | |
258 | GENERATED_GBL_DATA_SIZE) | |
259 | #else | |
260 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
261 | GENERATED_GBL_DATA_SIZE) | |
262 | #endif /* CONFIG_MEM_REMAP */ | |
263 | ||
264 | /* | |
265 | * Load address and memory test area should agree with | |
a187559e | 266 | * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. |
6cb144bc ML |
267 | */ |
268 | #define CONFIG_SYS_LOAD_ADDR 0x300000 | |
269 | ||
270 | /* memtest works on 63 MB in DRAM */ | |
271 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 | |
272 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) | |
273 | ||
274 | /* | |
275 | * Static memory controller configuration | |
276 | */ | |
277 | #define CONFIG_FTSMC020 | |
278 | ||
279 | #ifdef CONFIG_FTSMC020 | |
280 | #include <faraday/ftsmc020.h> | |
281 | ||
282 | #define CONFIG_SYS_FTSMC020_CONFIGS { \ | |
283 | { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ | |
284 | { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ | |
285 | } | |
286 | ||
287 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ | |
288 | #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ | |
289 | FTSMC020_BANK_SIZE_32M | \ | |
290 | FTSMC020_BANK_MBW_32) | |
291 | ||
292 | #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ | |
293 | FTSMC020_TPR_AST(1) | \ | |
294 | FTSMC020_TPR_CTW(1) | \ | |
295 | FTSMC020_TPR_ATI(1) | \ | |
296 | FTSMC020_TPR_AT2(1) | \ | |
297 | FTSMC020_TPR_WTC(1) | \ | |
298 | FTSMC020_TPR_AHT(1) | \ | |
299 | FTSMC020_TPR_TRNA(1)) | |
300 | #endif | |
301 | ||
302 | /* | |
303 | * FLASH on ADP_AG101P is connected to BANK0 | |
304 | * Just disalbe the other BANK to avoid detection error. | |
305 | */ | |
306 | #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ | |
307 | FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ | |
308 | FTSMC020_BANK_SIZE_32M | \ | |
309 | FTSMC020_BANK_MBW_32) | |
310 | ||
311 | #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ | |
312 | FTSMC020_TPR_CTW(3) | \ | |
313 | FTSMC020_TPR_ATI(0xf) | \ | |
314 | FTSMC020_TPR_AT2(3) | \ | |
315 | FTSMC020_TPR_WTC(3) | \ | |
316 | FTSMC020_TPR_AHT(3) | \ | |
317 | FTSMC020_TPR_TRNA(0xf)) | |
318 | ||
319 | #define FTSMC020_BANK1_CONFIG (0x00) | |
320 | #define FTSMC020_BANK1_TIMING (0x00) | |
321 | #endif /* CONFIG_FTSMC020 */ | |
322 | ||
323 | /* | |
324 | * FLASH and environment organization | |
325 | */ | |
326 | /* use CFI framework */ | |
327 | #define CONFIG_SYS_FLASH_CFI | |
328 | #define CONFIG_FLASH_CFI_DRIVER | |
329 | ||
330 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
331 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
2e88bb28 | 332 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL |
6cb144bc ML |
333 | |
334 | /* support JEDEC */ | |
335 | ||
336 | /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ | |
337 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
2e88bb28 KHH |
338 | #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ |
339 | #else | |
6cb144bc ML |
340 | #ifdef CONFIG_MEM_REMAP |
341 | #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ | |
342 | #else | |
343 | #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ | |
2e88bb28 | 344 | #endif |
6cb144bc | 345 | #endif /* CONFIG_MEM_REMAP */ |
6cb144bc ML |
346 | |
347 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
348 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } | |
349 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
350 | ||
351 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ | |
352 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ | |
353 | ||
354 | /* max number of memory banks */ | |
355 | /* | |
356 | * There are 4 banks supported for this Controller, | |
357 | * but we have only 1 bank connected to flash on board | |
358 | */ | |
359 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
2e88bb28 | 360 | #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} |
6cb144bc ML |
361 | |
362 | /* max number of sectors on one chip */ | |
2e88bb28 | 363 | #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) |
6cb144bc | 364 | #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE |
2e88bb28 | 365 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
6cb144bc ML |
366 | |
367 | /* environments */ | |
368 | #define CONFIG_ENV_IS_IN_FLASH | |
369 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) | |
370 | #define CONFIG_ENV_SIZE 8192 | |
371 | #define CONFIG_ENV_OVERWRITE | |
372 | ||
373 | #endif /* __CONFIG_H */ |