[people/ms/u-boot.git] / include / configs / adp-ag101p.h

/*
 * Copyright (C) 2011 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch-ag101/ag101.h>

/*
 * CPU and Board Configuration Options
 */
#define CONFIG_ADP_AG101P

#define CONFIG_USE_INTERRUPT

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_CMDLINE_EDITING

#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_MEM_REMAP
#endif

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE	0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else
#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_TEXT_BASE	0x80000000
#else
#define CONFIG_SYS_TEXT_BASE	0x00000000
#endif
#endif

/*
 * Timer
 */
#define CONFIG_SYS_CLK_FREQ	39062500
#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ

/*
 * Use Externel CLOCK or PCLK
 */
#undef CONFIG_FTRTC010_EXTCLK

#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif

#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
#endif

#define TIMER_LOAD_VAL	0xffffffff

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Real Time Clock Divider
 * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
 */
#define OSC_5MHZ			(5*1000000)
#define OSC_CLK				(4*OSC_5MHZ)
#define RTC_DIV_COUNT			(0.5)	/* Why?? */

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */

/*
 * SD (MMC) controller
 */
#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER		1
#define CONFIG_FTSDC010_SDIO

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* max number of command args */
#define CONFIG_SYS_MAXARGS	16

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * Size of malloc() pool
 */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)

/*
 * AHB Controller configuration
 */
#define CONFIG_FTAHBC020S

#ifdef CONFIG_FTAHBC020S
#include <faraday/ftahbc020s.h>

/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100

/*
 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 * in C language.
 */
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
#endif

/*
 * Watchdog
 */
#define CONFIG_FTWDT010_WATCHDOG

/*
 * PMU Power controller configuration
 */
#define CONFIG_PMU
#define CONFIG_FTPMU010_POWER

#ifdef CONFIG_FTPMU010_POWER
#include <faraday/ftpmu010.h>
#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
#endif

/*
 * SDRAM controller configuration
 */
#define CONFIG_FTSDMC021

#ifdef CONFIG_FTSDMC021
#include <faraday/ftsdmc021.h>

#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRAS(2)	|	\
					 FTSDMC021_TP1_TRP(1)	|	\
					 FTSDMC021_TP1_TRCD(1)	|	\
					 FTSDMC021_TP1_TRF(3)	|	\
					 FTSDMC021_TP1_TWR(1)	|	\
					 FTSDMC021_TP1_TCL(2))

#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
					 FTSDMC021_TP2_INI_REFT(8) |	\
					 FTSDMC021_TP2_REF_INTV(0x180))

/*
 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 * C language.
 */
#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
					 FTSDMC021_CR1_DSZ(3)	 |	\
					 FTSDMC021_CR1_MBW(2)	 |	\
					 FTSDMC021_CR1_BNKSIZE(6))

#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
					 FTSDMC021_CR2_IREF	 |	\
					 FTSDMC021_CR2_ISMR)

#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
					 CONFIG_SYS_FTSDMC021_BANK0_BASE)

#define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
#define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
#endif

/*
 * Physical Memory Map
 */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_SDRAM_0	0x00000000	/* SDRAM Bank #1 */
#else
#define PHYS_SDRAM_0	0x80000000	/* SDRAM Bank #1 */
#endif
#endif

#define PHYS_SDRAM_1 \
	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
#else
#define PHYS_SDRAM_0_SIZE	0x08000000	/* 128 MB */
#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
#endif
#endif

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0

#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
					GENERATED_GBL_DATA_SIZE)
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
					GENERATED_GBL_DATA_SIZE)
#endif /* CONFIG_MEM_REMAP */

/*
 * Load address and memory test area should agree with
 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		0x300000

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)

/*
 * Static memory controller configuration
 */
#define CONFIG_FTSMC020

#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
					 FTSMC020_BANK_SIZE_32M	|	\
					 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
					 FTSMC020_TPR_AST(1)	|	\
					 FTSMC020_TPR_CTW(1)	|	\
					 FTSMC020_TPR_ATI(1)	|	\
					 FTSMC020_TPR_AT2(1)	|	\
					 FTSMC020_TPR_WTC(1)	|	\
					 FTSMC020_TPR_AHT(1)	|	\
					 FTSMC020_TPR_TRNA(1))
#endif

/*
 * FLASH on ADP_AG101P is connected to BANK0
 * Just disalbe the other BANK to avoid detection error.
 */
#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(0x00)
#define FTSMC020_BANK1_TIMING	(0x00)
#endif /* CONFIG_FTSMC020 */

/*
 * FLASH and environment organization
 */
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

/* support JEDEC */

/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
#else
#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
#endif
#endif	/* CONFIG_MEM_REMAP */

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */

/* max number of memory banks */
/*
 * There are 4 banks supported for this Controller,
 * but we have only 1 bank connected to flash on board
 */
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}

/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* environments */
#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
#define CONFIG_ENV_SIZE			8192
#define CONFIG_ENV_OVERWRITE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)

#endif	/* __CONFIG_H */
Commit	Line	Data
6cb144bc ML	1	/*
	2	* Copyright (C) 2011 Andes Technology Corporation
	3	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	4	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
6cb144bc ML	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
7e3f94e1	12	#include <asm/arch-ag101/ag101.h>
6cb144bc ML	13
	14	/*
	15	* CPU and Board Configuration Options
	16	*/
	17	#define CONFIG_ADP_AG101P
	18
	19	#define CONFIG_USE_INTERRUPT
	20
	21	#define CONFIG_SKIP_LOWLEVEL_INIT
	22
b841b6e9	23	#define CONFIG_CMDLINE_EDITING
	24
	25	#define CONFIG_SYS_ICACHE_OFF
	26	#define CONFIG_SYS_DCACHE_OFF
	27
	28	#define CONFIG_BOOTP_SEND_HOSTNAME
	29	#define CONFIG_BOOTP_SERVERIP
e3c58b02	30
6cb144bc ML	31	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	32	#define CONFIG_MEM_REMAP
	33	#endif
	34
	35	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
2e88bb28	36	#define CONFIG_SYS_TEXT_BASE 0x00500000
86132af7	37	#ifdef CONFIG_OF_CONTROL
	38	#undef CONFIG_OF_SEPARATE
	39	#define CONFIG_OF_EMBED
	40	#endif
2e88bb28 KHH	41	#else
	42	#ifdef CONFIG_MEM_REMAP
	43	#define CONFIG_SYS_TEXT_BASE 0x80000000
6cb144bc ML	44	#else
	45	#define CONFIG_SYS_TEXT_BASE 0x00000000
	46	#endif
2e88bb28	47	#endif
6cb144bc ML	48
	49	/*
	50	* Timer
	51	*/
6cb144bc ML	52	#define CONFIG_SYS_CLK_FREQ 39062500
	53	#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	54
	55	/*
	56	* Use Externel CLOCK or PCLK
	57	*/
	58	#undef CONFIG_FTRTC010_EXTCLK
	59
	60	#ifndef CONFIG_FTRTC010_EXTCLK
	61	#define CONFIG_FTRTC010_PCLK
	62	#endif
	63
	64	#ifdef CONFIG_FTRTC010_EXTCLK
	65	#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	66	#else
	67	#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	68	#endif
	69
	70	#define TIMER_LOAD_VAL 0xffffffff
	71
	72	/*
	73	* Real Time Clock
	74	*/
	75	#define CONFIG_RTC_FTRTC010
	76
	77	/*
	78	* Real Time Clock Divider
	79	* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	80	*/
	81	#define OSC_5MHZ (5*1000000)
	82	#define OSC_CLK (4*OSC_5MHZ)
	83	#define RTC_DIV_COUNT (0.5) /* Why?? */
	84
	85	/*
	86	* Serial console configuration
	87	*/
	88
	89	/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
6cb144bc	90	#define CONFIG_CONS_INDEX 1
6cb144bc ML	91	#define CONFIG_SYS_NS16550_SERIAL
6cb144bc ML	92	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
86132af7	93	#ifndef CONFIG_DM_SERIAL
6cb144bc	94	#define CONFIG_SYS_NS16550_REG_SIZE -4
86132af7	95	#endif
6cb144bc ML	96	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
6cb144bc ML	97
6cb144bc ML	98	/*
	99	* SD (MMC) controller
	100	*/
6cb144bc ML	101	#define CONFIG_FTSDC010
6cb144bc ML	102	#define CONFIG_FTSDC010_NUMBER 1
61ccf082	103	#define CONFIG_FTSDC010_SDIO
6cb144bc	104
6cb144bc ML	105	/*
	106	* Miscellaneous configurable options
	107	*/
	108	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6cb144bc ML	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	110
	111	/* Print Buffer Size */
	112	#define CONFIG_SYS_PBSIZE \
	113	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	114
	115	/* max number of command args */
	116	#define CONFIG_SYS_MAXARGS 16
	117
	118	/* Boot Argument Buffer Size */
	119	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	120
6cb144bc ML	121	/*
	122	* Size of malloc() pool
	123	*/
	124	/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
	125	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	126
6cb144bc ML	127	/*
	128	* AHB Controller configuration
	129	*/
	130	#define CONFIG_FTAHBC020S
	131
	132	#ifdef CONFIG_FTAHBC020S
	133	#include <faraday/ftahbc020s.h>
	134
	135	/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
	136	#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
	137
	138	/*
	139	* CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
	140	* hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
	141	* in C language.
	142	*/
	143	#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
	144	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) \| \
	145	FTAHBC020S_SLAVE_BSR_SIZE(0xb))
	146	#endif
	147
	148	/*
	149	* Watchdog
	150	*/
	151	#define CONFIG_FTWDT010_WATCHDOG
	152
	153	/*
	154	* PMU Power controller configuration
	155	*/
	156	#define CONFIG_PMU
	157	#define CONFIG_FTPMU010_POWER
	158
	159	#ifdef CONFIG_FTPMU010_POWER
	160	#include <faraday/ftpmu010.h>
	161	#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
	162	#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR \| \
	163	FTPMU010_SDRAMHTC_EBIDATA_DCSR \| \
	164	FTPMU010_SDRAMHTC_SDRAMCS_DCSR \| \
	165	FTPMU010_SDRAMHTC_SDRAMCTL_DCSR \| \
	166	FTPMU010_SDRAMHTC_CKE_DCSR \| \
	167	FTPMU010_SDRAMHTC_DQM_DCSR \| \
	168	FTPMU010_SDRAMHTC_SDCLK_DCSR)
	169	#endif
	170
	171	/*
	172	* SDRAM controller configuration
	173	*/
	174	#define CONFIG_FTSDMC021
	175
	176	#ifdef CONFIG_FTSDMC021
	177	#include <faraday/ftsdmc021.h>
	178
	179	#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) \| \
	180	FTSDMC021_TP1_TRP(1) \| \
	181	FTSDMC021_TP1_TRCD(1) \| \
	182	FTSDMC021_TP1_TRF(3) \| \
	183	FTSDMC021_TP1_TWR(1) \| \
	184	FTSDMC021_TP1_TCL(2))
	185
	186	#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) \| \
	187	FTSDMC021_TP2_INI_REFT(8) \| \
	188	FTSDMC021_TP2_REF_INTV(0x180))
	189
	190	/*
191	* CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
192	* hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
193	* C language.
194	*/
195	#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) \| \
196	FTSDMC021_CR1_DSZ(3) \| \
197	FTSDMC021_CR1_MBW(2) \| \
198	FTSDMC021_CR1_BNKSIZE(6))
199
200	#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC \| \
201	FTSDMC021_CR2_IREF \| \
202	FTSDMC021_CR2_ISMR)
203
204	#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
205	#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE \| \
206	CONFIG_SYS_FTSDMC021_BANK0_BASE)
207
3c016704	208	#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
	209	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
	210	#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE \| \
	211	CONFIG_SYS_FTSDMC021_BANK1_BASE)
6cb144bc ML	212	#endif
	213
	214	/*
	215	* Physical Memory Map
	216	*/
2e88bb28 KHH	217	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	218	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	219	#else
	220	#ifdef CONFIG_MEM_REMAP
	221	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	222	#else
	223	#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
6cb144bc	224	#endif
6cb144bc	225	#endif
2e88bb28	226
3c016704	227	#define PHYS_SDRAM_1 \
3c016704	228	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
6cb144bc	229
3c016704	230	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
2e88bb28 KHH	231
	232	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	233	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	234	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	235	#else
	236	#ifdef CONFIG_MEM_REMAP
	237	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	238	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	239	#else
	240	#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
	241	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	242	#endif
	243	#endif
6cb144bc ML	244
	245	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	246
	247	#ifdef CONFIG_MEM_REMAP
	248	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	249	GENERATED_GBL_DATA_SIZE)
	250	#else
	251	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	252	GENERATED_GBL_DATA_SIZE)
	253	#endif /* CONFIG_MEM_REMAP */
	254
	255	/*
	256	* Load address and memory test area should agree with
a187559e	257	* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
6cb144bc ML	258	*/
	259	#define CONFIG_SYS_LOAD_ADDR 0x300000
	260
	261	/* memtest works on 63 MB in DRAM */
	262	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
	263	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
	264
	265	/*
	266	* Static memory controller configuration
	267	*/
	268	#define CONFIG_FTSMC020
	269
	270	#ifdef CONFIG_FTSMC020
	271	#include <faraday/ftsmc020.h>
	272
	273	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	274	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	275	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	276	}
	277
	278	#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
	279	#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE \| \
	280	FTSMC020_BANK_SIZE_32M \| \
	281	FTSMC020_BANK_MBW_32)
	282
	283	#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE \| \
	284	FTSMC020_TPR_AST(1) \| \
	285	FTSMC020_TPR_CTW(1) \| \
	286	FTSMC020_TPR_ATI(1) \| \
	287	FTSMC020_TPR_AT2(1) \| \
	288	FTSMC020_TPR_WTC(1) \| \
	289	FTSMC020_TPR_AHT(1) \| \
	290	FTSMC020_TPR_TRNA(1))
	291	#endif
	292
	293	/*
	294	* FLASH on ADP_AG101P is connected to BANK0
	295	* Just disalbe the other BANK to avoid detection error.
	296	*/
	297	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
	298	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
	299	FTSMC020_BANK_SIZE_32M \| \
	300	FTSMC020_BANK_MBW_32)
	301
	302	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) \| \
	303	FTSMC020_TPR_CTW(3) \| \
	304	FTSMC020_TPR_ATI(0xf) \| \
	305	FTSMC020_TPR_AT2(3) \| \
	306	FTSMC020_TPR_WTC(3) \| \
	307	FTSMC020_TPR_AHT(3) \| \
	308	FTSMC020_TPR_TRNA(0xf))
	309
	310	#define FTSMC020_BANK1_CONFIG (0x00)
	311	#define FTSMC020_BANK1_TIMING (0x00)
	312	#endif /* CONFIG_FTSMC020 */
	313
	314	/*
	315	* FLASH and environment organization
	316	*/
	317	/* use CFI framework */
	318	#define CONFIG_SYS_FLASH_CFI
	319	#define CONFIG_FLASH_CFI_DRIVER
	320
	321	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
322	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
2e88bb28	323	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
6cb144bc ML	324
	325	/* support JEDEC */
	326
	327	/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
	328	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
2e88bb28 KHH	329	#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
2e88bb28 KHH	330	#else
6cb144bc ML	331	#ifdef CONFIG_MEM_REMAP
	332	#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
	333	#else
	334	#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
2e88bb28	335	#endif
6cb144bc	336	#endif /* CONFIG_MEM_REMAP */
6cb144bc ML	337
	338	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	339	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
	340	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	341
	342	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
	343	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
	344
	345	/* max number of memory banks */
	346	/*
	347	* There are 4 banks supported for this Controller,
	348	* but we have only 1 bank connected to flash on board
	349	*/
b841b6e9	350	#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
6cb144bc	351	#define CONFIG_SYS_MAX_FLASH_BANKS 1
b841b6e9	352	#endif
2e88bb28	353	#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
6cb144bc ML	354
6cb144bc ML	355	/* max number of sectors on one chip */
2e88bb28	356	#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
6cb144bc	357	#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
2e88bb28	358	#define CONFIG_SYS_MAX_FLASH_SECT 512
6cb144bc ML	359
6cb144bc ML	360	/* environments */
6cb144bc ML	361	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
	362	#define CONFIG_ENV_SIZE 8192
	363	#define CONFIG_ENV_OVERWRITE
	364
b841b6e9	365	/*
	366	* For booting Linux, the board info and command line data
	367	* have to be in the first 16 MB of memory, since this is
	368	* the maximum mapped by the Linux kernel during initialization.
	369	*/
	370
	371	/* Initial Memory map for Linux*/
	372	#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
	373	/* Increase max gunzip size */
	374	#define CONFIG_SYS_BOOTM_LEN (64 << 20)
	375
6cb144bc	376	#endif /* __CONFIG_H */