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8993e54b RJ |
1 | /* |
2 | * (C) Copyright 2007 DENX Software Engineering | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * ADS5121 board configuration file | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | #define DEBUG | |
31 | #undef DEBUG | |
32 | ||
33 | /* | |
34 | * Memory map for the ADS5121 board: | |
35 | * | |
36 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
37 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
38 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
39 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
40 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) | |
41 | */ | |
42 | ||
43 | /* | |
44 | * High Level Configuration Options | |
45 | */ | |
46 | #define CONFIG_E300 1 /* E300 Family */ | |
47 | #define CONFIG_MPC512X 1 /* MPC512X family */ | |
48 | ||
49 | #undef CONFIG_PCI | |
50 | ||
51 | #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ | |
52 | ||
53 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
54 | ||
55 | #define CFG_IMMR 0x80000000 | |
56 | ||
57 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
58 | #define CFG_MEMTEST_END 0x00400000 | |
59 | ||
60 | /* | |
61 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
62 | */ | |
63 | #define CFG_DDR_SIZE 256 /* MB */ | |
64 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
65 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
66 | ||
67 | /* DDR Controller Configuration | |
b1b54e35 WD |
68 | * |
69 | * SYS_CFG: | |
70 | * [31:31] MDDRC Soft Reset: Diabled | |
71 | * [30:30] DRAM CKE pin: Enabled | |
72 | * [29:29] DRAM CLK: Enabled | |
73 | * [28:28] Command Mode: Enabled (For initialization only) | |
74 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
75 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
76 | * [20:19] Read Test: DON'T USE | |
77 | * [18:18] Self Refresh: Enabled | |
78 | * [17:17] 16bit Mode: Disabled | |
79 | * [16:13] Ready Delay: 2 | |
80 | * [12:12] Half DQS Delay: Disabled | |
81 | * [11:11] Quarter DQS Delay: Disabled | |
82 | * [10:08] Write Delay: 2 | |
83 | * [07:07] Early ODT: Disabled | |
84 | * [06:06] On DIE Termination: Disabled | |
85 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
86 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
87 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
88 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
89 | * [01:01] FIFO Overlfow Enabled: Enabled | |
90 | * [00:00] FIFO Underflow Enabled: Enabled | |
91 | * TIME_CFG0 | |
92 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
93 | * [15:8] DRAM Command Time: 0 CSB clocks | |
94 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
95 | * TIME_CFG1 | |
96 | * [31:26] DRAM tRFC: | |
97 | * [25:21] DRAM tWR1: | |
98 | * [20:17] DRAM tWRT1: | |
99 | * [16:11] DRAM tDRR: | |
100 | * [10:05] DRAM tRC: | |
101 | * [04:00] DRAM tRAS: | |
102 | * TIME_CFG2 | |
103 | * [31:28] DRAM tRCD: | |
104 | * [27:23] DRAM tFAW: | |
105 | * [22:19] DRAM tRTW1: | |
106 | * [18:15] DRAM tCCD: | |
107 | * [14:10] DRAM tRTP: | |
108 | * [09:05] DRAM tRP: | |
109 | * [04:00] DRAM tRPA | |
110 | */ | |
8993e54b RJ |
111 | |
112 | #define CFG_MDDRC_SYS_CFG 0xF8604200 | |
113 | #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 | |
114 | #define CFG_MDDRC_SYS_CFG_EN 0x30000000 | |
115 | #define CFG_MDDRC_TIME_CFG0 0x0000281E | |
116 | #define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E | |
117 | #define CFG_MDDRC_TIME_CFG1 0x54EC1168 | |
118 | #define CFG_MDDRC_TIME_CFG2 0x35210864 | |
119 | ||
120 | #define CFG_MICRON_NOP 0x01380000 | |
121 | #define CFG_MICRON_PCHG_ALL 0x01100400 | |
122 | #define CFG_MICRON_MR 0x01000022 | |
123 | #define CFG_MICRON_EM2 0x01020000 | |
124 | #define CFG_MICRON_EM3 0x01030000 | |
125 | #define CFG_MICRON_EN_DLL 0x01010000 | |
126 | #define CFG_MICRON_RST_DLL 0x01000932 | |
127 | #define CFG_MICRON_RFSH 0x01080000 | |
128 | #define CFG_MICRON_INIT_DEV_OP 0x01000832 | |
129 | #define CFG_MICRON_OCD_DEFAULT 0x01010780 | |
130 | #define CFG_MICRON_OCD_EXIT 0x01010400 | |
131 | ||
132 | /* DDR Priority Manager Configuration */ | |
133 | #define CFG_MDDRCGRP_PM_CFG1 0x000777AA | |
134 | #define CFG_MDDRCGRP_PM_CFG2 0x00000055 | |
135 | #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 | |
136 | #define CFG_MDDRCGRP_LUT0_MU 0x11111117 | |
137 | #define CFG_MDDRCGRP_LUT0_ML 0x7777777A | |
138 | #define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE | |
139 | #define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE | |
140 | #define CFG_MDDRCGRP_LUT2_MU 0x44444444 | |
141 | #define CFG_MDDRCGRP_LUT2_ML 0x44444444 | |
142 | #define CFG_MDDRCGRP_LUT3_MU 0x55555555 | |
143 | #define CFG_MDDRCGRP_LUT3_ML 0x55555558 | |
144 | #define CFG_MDDRCGRP_LUT4_MU 0x11111111 | |
145 | #define CFG_MDDRCGRP_LUT4_ML 0x1111117C | |
146 | #define CFG_MDDRCGRP_LUT0_AU 0x33333377 | |
147 | #define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE | |
148 | #define CFG_MDDRCGRP_LUT1_AU 0x11111111 | |
149 | #define CFG_MDDRCGRP_LUT1_AL 0x11111111 | |
150 | #define CFG_MDDRCGRP_LUT2_AU 0x11111111 | |
151 | #define CFG_MDDRCGRP_LUT2_AL 0x11111111 | |
152 | #define CFG_MDDRCGRP_LUT3_AU 0x11111111 | |
153 | #define CFG_MDDRCGRP_LUT3_AL 0x11111111 | |
154 | #define CFG_MDDRCGRP_LUT4_AU 0x11111111 | |
155 | #define CFG_MDDRCGRP_LUT4_AL 0x11111111 | |
156 | ||
157 | /* | |
158 | * NOR FLASH on the Local Bus | |
159 | */ | |
160 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
161 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
162 | #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */ | |
163 | #define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
164 | #define CFG_FLASH_USE_BUFFER_WRITE | |
165 | ||
166 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
167 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} | |
168 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ | |
169 | ||
170 | #undef CFG_FLASH_CHECKSUM | |
171 | ||
172 | /* | |
173 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
174 | * window is 64KB | |
175 | */ | |
176 | #define CFG_CPLD_BASE 0x82000000 | |
177 | #define CFG_CPLD_SIZE 0x00010000 /* 64 KB */ | |
178 | ||
179 | #define CFG_SRAM_BASE 0x30000000 | |
180 | #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ | |
181 | ||
182 | #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ | |
183 | #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
184 | ||
185 | /* Use SRAM for initial stack */ | |
186 | #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ | |
187 | #define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ | |
188 | ||
189 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
190 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
191 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
192 | ||
193 | #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ | |
194 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
195 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
196 | ||
197 | /* | |
198 | * Serial Port | |
199 | */ | |
200 | #define CONFIG_CONS_INDEX 1 | |
201 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
202 | ||
203 | /* | |
204 | * Serial console configuration | |
205 | */ | |
206 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
207 | #if CONFIG_PSC_CONSOLE != 3 | |
208 | #error CONFIG_PSC_CONSOLE must be 3 | |
209 | #endif | |
210 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
211 | #define CFG_BAUDRATE_TABLE \ | |
212 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
213 | ||
214 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
215 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
216 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
217 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
218 | ||
219 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
220 | /* Use the HUSH parser */ | |
221 | #define CFG_HUSH_PARSER | |
222 | #ifdef CFG_HUSH_PARSER | |
223 | #define CFG_PROMPT_HUSH_PS2 "> " | |
224 | #endif | |
225 | ||
226 | /* I2C */ | |
227 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
228 | #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ | |
229 | #define CONFIG_I2C_MULTI_BUS | |
230 | #define CONFIG_I2C_CMD_TREE | |
231 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ | |
232 | #define CFG_I2C_SLAVE 0x7F | |
233 | #if 0 | |
cf5933ba | 234 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
8993e54b RJ |
235 | #endif |
236 | ||
80020120 GB |
237 | /* |
238 | * EEPROM configuration | |
239 | */ | |
240 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ | |
241 | #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
de74b9ee | 242 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ |
80020120 GB |
243 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ |
244 | ||
8993e54b RJ |
245 | /* |
246 | * Ethernet configuration | |
247 | */ | |
248 | #define CONFIG_MPC512x_FEC 1 | |
249 | #define CONFIG_NET_MULTI | |
250 | #define CONFIG_PHY_ADDR 0x1 | |
251 | #define CONFIG_MII 1 /* MII PHY management */ | |
8993e54b RJ |
252 | |
253 | #if 0 | |
254 | /* | |
255 | * Configure on-board RTC | |
256 | */ | |
257 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
258 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
259 | #endif | |
260 | ||
261 | /* | |
262 | * Environment | |
263 | */ | |
264 | #define CFG_ENV_IS_IN_FLASH 1 | |
265 | /* This has to be a multiple of the Flash sector size */ | |
266 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
267 | #define CFG_ENV_SIZE 0x2000 | |
268 | #define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ | |
269 | ||
270 | /* Address and size of Redundant Environment Sector */ | |
271 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
272 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
273 | ||
274 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
275 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
276 | ||
e27f3a6e WD |
277 | #include <config_cmd_default.h> |
278 | ||
279 | #define CONFIG_CMD_ASKENV | |
280 | #define CONFIG_CMD_DHCP | |
281 | #define CONFIG_CMD_I2C | |
282 | #define CONFIG_CMD_MII | |
283 | #define CONFIG_CMD_NFS | |
284 | #define CONFIG_CMD_PING | |
285 | #define CONFIG_CMD_REGINFO | |
80020120 | 286 | #define CONFIG_CMD_EEPROM |
e27f3a6e | 287 | |
8993e54b | 288 | #if defined(CONFIG_PCI) |
e27f3a6e | 289 | #define CONFIG_CMD_PCI |
8993e54b RJ |
290 | #endif |
291 | ||
8993e54b RJ |
292 | /* |
293 | * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. | |
294 | * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set | |
295 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer | |
296 | * to chapter 36 of the MPC5121e Reference Manual. | |
297 | */ | |
298 | #define CONFIG_WATCHDOG /* enable watchdog */ | |
299 | #define CFG_WATCHDOG_VALUE 0xFFFF | |
300 | ||
301 | /* | |
302 | * Miscellaneous configurable options | |
303 | */ | |
304 | #define CFG_LONGHELP /* undef to save memory */ | |
305 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
306 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
307 | ||
e27f3a6e | 308 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
309 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
310 | #else | |
311 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
312 | #endif | |
313 | ||
314 | ||
315 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ | |
316 | #define CFG_MAXARGS 16 /* max number of command args */ | |
317 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
318 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
319 | ||
320 | /* | |
321 | * For booting Linux, the board info and command line data | |
322 | * have to be in the first 8 MB of memory, since this is | |
323 | * the maximum mapped by the Linux kernel during initialization. | |
324 | */ | |
325 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
326 | ||
327 | /* Cache Configuration */ | |
328 | #define CFG_DCACHE_SIZE 32768 | |
329 | #define CFG_CACHELINE_SIZE 32 | |
e27f3a6e | 330 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
331 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
332 | #endif | |
333 | ||
334 | #define CFG_HID0_INIT 0x000000000 | |
335 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
336 | #define CFG_HID2 HID2_HBE | |
337 | ||
338 | /* | |
339 | * Internal Definitions | |
340 | * | |
341 | * Boot Flags | |
342 | */ | |
343 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
344 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
345 | ||
e27f3a6e | 346 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
347 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
348 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
349 | #endif | |
350 | ||
351 | /* | |
352 | * Environment Configuration | |
353 | */ | |
354 | #define CONFIG_ENV_OVERWRITE | |
355 | ||
356 | #define CONFIG_HOSTNAME ads5121 | |
8d103071 | 357 | #define CONFIG_BOOTFILE ads5121/uImage |
8993e54b | 358 | |
8d103071 | 359 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 360 | |
e27f3a6e | 361 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
8993e54b RJ |
362 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
363 | ||
364 | #define CONFIG_BAUDRATE 115200 | |
365 | ||
366 | #define CONFIG_PREBOOT "echo;" \ | |
367 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
368 | "echo" | |
369 | ||
370 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 WD |
371 | "u-boot_addr_r=200000\0" \ |
372 | "kernel_addr_r=200000\0" \ | |
373 | "fdt_addr_r=400000\0" \ | |
374 | "ramdisk_addr_r=500000\0" \ | |
375 | "u-boot_addr=FFF00000\0" \ | |
376 | "kernel_addr=FC000000\0" \ | |
377 | "fdt_addr=FC2C0000\0" \ | |
378 | "ramdisk_addr=FC300000\0" \ | |
379 | "ramdiskfile=ads5121/uRamdisk\0" \ | |
380 | "fdtfile=ads5121/ads5121.dtb\0" \ | |
381 | "u-boot=ads5121/u-boot.bin\0" \ | |
8993e54b | 382 | "netdev=eth0\0" \ |
8d103071 | 383 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
384 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
385 | "nfsroot=${serverip}:${rootpath}\0" \ | |
386 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
387 | "addip=setenv bootargs ${bootargs} " \ | |
388 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
389 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
390 | "addtty=setenv bootargs ${bootargs} " \ |
391 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 392 | "flash_nfs=run nfsargs addip addtty;" \ |
8d103071 | 393 | "bootm ${kernel_addr_r} - ${fdt_addr}\0" \ |
8993e54b | 394 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
395 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
396 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
397 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
398 | "run nfsargs addip addtty;" \ | |
399 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
400 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
401 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
402 | "tftp ${fdt_addr} ${fdtfile};" \ | |
403 | "run ramargs addip addtty;" \ | |
404 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\ | |
405 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ | |
406 | "update=protect off ${u-boot_addr} +${filesize};" \ | |
407 | "era ${u-boot_addr} +${filesize};" \ | |
408 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
409 | "upd=run load update\0" \ | |
8993e54b RJ |
410 | "" |
411 | ||
8993e54b RJ |
412 | #define CONFIG_BOOTCOMMAND "run flash_self" |
413 | ||
281ff9a4 GB |
414 | #define CONFIG_OF_LIBFDT 1 |
415 | #define CONFIG_OF_BOARD_SETUP 1 | |
416 | ||
417 | #define OF_CPU "PowerPC,5121@0" | |
418 | #define OF_SOC "soc5121@80000000" | |
419 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
420 | #define OF_STDOUT_PATH "/soc5121@80000000/serial@11300" | |
421 | ||
8993e54b | 422 | #endif /* __CONFIG_H */ |