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8f79e4c2 | 1 | /* |
5078cce8 | 2 | * (C) Copyright 2003-2006 |
8f79e4c2 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2004-2005 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
39 | #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ | |
40 | #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ | |
41 | #define CONFIG_AEVFIFO 1 | |
42 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
43 | ||
44 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
45 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
46 | ||
47 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ | |
48 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
49 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * Serial console configuration | |
54 | */ | |
55 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
56 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
57 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
58 | ||
59 | /* | |
60 | * PCI Mapping: | |
61 | * 0x40000000 - 0x4fffffff - PCI Memory | |
62 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
63 | */ | |
64 | #ifdef CONFIG_AEVFIFO | |
65 | #define CONFIG_PCI 1 | |
66 | #define CONFIG_PCI_PNP 1 | |
67 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ | |
68 | ||
69 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
70 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
71 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
72 | ||
73 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
74 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
75 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
76 | ||
77 | #define CONFIG_NET_MULTI 1 | |
78 | #define CONFIG_EEPRO100 1 | |
79 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
80 | #define CONFIG_NS8382X 1 | |
81 | #endif /* CONFIG_AEVFIFO */ | |
82 | ||
83 | /* Partitions */ | |
84 | #define CONFIG_MAC_PARTITION | |
85 | #define CONFIG_DOS_PARTITION | |
86 | #define CONFIG_ISO_PARTITION | |
87 | ||
88 | /* POST support */ | |
89 | #define CONFIG_POST (CFG_POST_MEMORY | \ | |
90 | CFG_POST_CPU | \ | |
91 | CFG_POST_I2C) | |
92 | ||
93 | #ifdef CONFIG_POST | |
94 | #define CFG_CMD_POST_DIAG CFG_CMD_DIAG | |
95 | /* preserve space for the post_word at end of on-chip SRAM */ | |
96 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
97 | #else | |
98 | #define CFG_CMD_POST_DIAG 0 | |
99 | #endif | |
100 | ||
101 | /* | |
102 | * Supported commands | |
103 | */ | |
104 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
105 | ADD_BMP_CMD | \ | |
106 | CFG_CMD_PCI | \ | |
107 | CFG_CMD_ASKENV | \ | |
108 | CFG_CMD_DATE | \ | |
109 | CFG_CMD_DHCP | \ | |
110 | CFG_CMD_ECHO | \ | |
111 | CFG_CMD_EEPROM | \ | |
112 | CFG_CMD_I2C | \ | |
113 | CFG_CMD_MII | \ | |
114 | CFG_CMD_NFS | \ | |
115 | CFG_CMD_PING | \ | |
116 | CFG_CMD_POST_DIAG | \ | |
117 | CFG_CMD_REGINFO | \ | |
118 | CFG_CMD_SNTP ) | |
119 | ||
120 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
121 | #include <cmd_confdefs.h> | |
122 | ||
123 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
124 | ||
125 | #if (TEXT_BASE == 0xFC000000) /* Boot low */ | |
126 | # define CFG_LOWBOOT 1 | |
127 | #endif | |
128 | ||
129 | /* | |
130 | * Autobooting | |
131 | */ | |
132 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
133 | ||
134 | #define CONFIG_PREBOOT "echo;" \ | |
135 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
136 | "echo" | |
137 | ||
138 | #undef CONFIG_BOOTARGS | |
139 | ||
140 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
141 | "netdev=eth0\0" \ | |
142 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
143 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
144 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b WD |
145 | "nfsroot=${serverip}:${rootpath} " \ |
146 | "console=ttyS0,${baudrate}\0" \ | |
147 | "addip=setenv bootargs ${bootargs} " \ | |
148 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
149 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8f79e4c2 | 150 | "flash_self=run ramargs addip;" \ |
fe126d8b | 151 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
8f79e4c2 | 152 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b WD |
153 | "bootm ${kernel_addr}\0" \ |
154 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
8f79e4c2 | 155 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
fe126d8b | 156 | "load=tftp 200000 ${u-boot}\0" \ |
8f79e4c2 WD |
157 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ |
158 | "update=protect off FC000000 FC05FFFF;" \ | |
159 | "erase FC000000 FC05FFFF;" \ | |
fe126d8b | 160 | "cp.b 200000 FC000000 ${filesize};" \ |
8f79e4c2 WD |
161 | "protect on FC000000 FC05FFFF\0" \ |
162 | "" | |
163 | ||
164 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
165 | ||
166 | /* | |
167 | * IPB Bus clocking configuration. | |
168 | */ | |
169 | #define CFG_IPBSPEED_133 /* define for 133MHz speed */ | |
170 | ||
171 | #if defined(CFG_IPBSPEED_133) | |
172 | /* | |
173 | * PCI Bus clocking configuration | |
174 | * | |
175 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
176 | * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't | |
177 | * been tested with a IPB Bus Clock of 66 MHz. | |
178 | */ | |
179 | #define CFG_PCISPEED_66 /* define for 66MHz speed */ | |
180 | #endif | |
181 | ||
182 | /* | |
183 | * I2C configuration | |
184 | */ | |
185 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
186 | #ifdef CONFIG_TQM5200_REV100 | |
187 | #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ | |
188 | #else | |
189 | #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ | |
190 | #endif | |
191 | ||
192 | /* | |
193 | * I2C clock frequency | |
194 | * | |
195 | * Please notice, that the resulting clock frequency could differ from the | |
196 | * configured value. This is because the I2C clock is derived from system | |
197 | * clock over a frequency divider with only a few divider values. U-boot | |
198 | * calculates the best approximation for CFG_I2C_SPEED. However the calculated | |
199 | * approximation allways lies below the configured value, never above. | |
200 | */ | |
201 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
202 | #define CFG_I2C_SLAVE 0x7F | |
203 | ||
204 | /* | |
205 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
206 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
207 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
208 | * same configuration could be used. | |
209 | */ | |
210 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
211 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
212 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
213 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
214 | ||
215 | /* | |
216 | * Flash configuration | |
217 | */ | |
218 | #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ | |
219 | ||
220 | /* use CFI flash driver if no module variant is spezified */ | |
221 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
222 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
223 | #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } | |
224 | #define CFG_FLASH_EMPTY_INFO | |
225 | #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
226 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
227 | #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
228 | ||
229 | #if !defined(CFG_LOWBOOT) | |
230 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) | |
231 | #else /* CFG_LOWBOOT */ | |
232 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) | |
233 | #endif /* CFG_LOWBOOT */ | |
234 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks | |
235 | (= chip selects) */ | |
236 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
237 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
238 | ||
239 | ||
240 | /* | |
241 | * Environment settings | |
242 | */ | |
243 | #define CFG_ENV_IS_IN_FLASH 1 | |
244 | #define CFG_ENV_SIZE 0x10000 | |
245 | #define CFG_ENV_SECT_SIZE 0x20000 | |
246 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
247 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
248 | ||
249 | /* | |
250 | * Memory map | |
251 | */ | |
252 | #define CFG_MBAR 0xF0000000 | |
253 | #define CFG_SDRAM_BASE 0x00000000 | |
254 | #define CFG_DEFAULT_MBAR 0x80000000 | |
255 | ||
256 | /* Use ON-Chip SRAM until RAM will be available */ | |
257 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
258 | #ifdef CONFIG_POST | |
259 | /* preserve space for the post_word at end of on-chip SRAM */ | |
260 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE | |
261 | #else | |
262 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
263 | #endif | |
264 | ||
265 | ||
266 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
267 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
268 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
269 | ||
270 | #define CFG_MONITOR_BASE TEXT_BASE | |
271 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
272 | # define CFG_RAMBOOT 1 | |
273 | #endif | |
274 | ||
275 | #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ | |
276 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
277 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
278 | ||
279 | /* | |
280 | * Ethernet configuration | |
281 | */ | |
282 | #define CONFIG_MPC5xxx_FEC 1 | |
283 | /* | |
284 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
285 | */ | |
286 | /* #define CONFIG_FEC_10MBIT 1 */ | |
287 | #define CONFIG_PHY_ADDR 0x00 | |
288 | ||
289 | /* | |
290 | * GPIO configuration | |
291 | * | |
292 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
293 | * Bit 0 (mask: 0x80000000): 1 | |
294 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
295 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
296 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
297 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
298 | * (because, there I2C1 is used as I2C bus) | |
299 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
300 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
301 | * 000 -> All PSC2 pins are GIOPs | |
302 | * 001 -> CAN1/2 on PSC2 pins | |
303 | * Use for REV100 STK52xx boards | |
304 | * use PSC6: | |
305 | * on STK52xx: | |
306 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
307 | * Bits 9:11 (mask: 0x00700000): | |
308 | * 101 -> PSC6 : Extended POST test is not available | |
309 | * on MINI-FAP and TQM5200_IB: | |
310 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
311 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
312 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
313 | * tests. | |
314 | */ | |
315 | #define CFG_GPS_PORT_CONFIG 0x81500014 | |
316 | ||
317 | /* | |
318 | * RTC configuration | |
319 | */ | |
320 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
321 | ||
322 | /* | |
323 | * Miscellaneous configurable options | |
324 | */ | |
325 | #define CFG_LONGHELP /* undef to save memory */ | |
326 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
327 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
328 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
329 | #else | |
330 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
331 | #endif | |
332 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
333 | #define CFG_MAXARGS 16 /* max number of command args */ | |
334 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
335 | ||
336 | /* Enable an alternate, more extensive memory test */ | |
337 | #define CFG_ALT_MEMTEST | |
338 | ||
339 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
340 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
341 | ||
342 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
343 | ||
344 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
345 | ||
346 | /* | |
347 | * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, | |
348 | * which is normally part of the default commands (CFV_CMD_DFL) | |
349 | */ | |
350 | #define CONFIG_LOOPW | |
351 | ||
352 | /* | |
353 | * Various low-level settings | |
354 | */ | |
355 | #if defined(CONFIG_MPC5200) | |
356 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
357 | #define CFG_HID0_FINAL HID0_ICE | |
358 | #else | |
359 | #define CFG_HID0_INIT 0 | |
360 | #define CFG_HID0_FINAL 0 | |
361 | #endif | |
362 | ||
363 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
364 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
365 | #ifdef CFG_PCISPEED_66 | |
366 | #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
367 | #else | |
368 | #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ | |
369 | #endif | |
370 | #define CFG_CS0_START CFG_FLASH_BASE | |
371 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
372 | ||
8f79e4c2 | 373 | #define CONFIG_LAST_STAGE_INIT |
8f79e4c2 WD |
374 | |
375 | /* | |
376 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
377 | * for SDRAM autosizing. | |
378 | */ | |
379 | #define CFG_CS2_START 0xE5000000 | |
380 | #define CFG_CS2_SIZE 0x80000 /* 512 kByte */ | |
381 | #define CFG_CS2_CFG 0x0004D930 | |
382 | ||
383 | /* | |
384 | * Grafic controller - Do not map below 2 GB in address space, because this | |
385 | * area is used for SDRAM autosizing. | |
386 | */ | |
387 | #define SM501_FB_BASE 0xE0000000 | |
388 | #define CFG_CS1_START (SM501_FB_BASE) | |
389 | #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */ | |
390 | #define CFG_CS1_CFG 0x8F48FF70 | |
391 | #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000 | |
392 | ||
393 | #define CFG_CS_BURST 0x00000000 | |
394 | #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
395 | ||
396 | #define CFG_RESET_ADDRESS 0xff000000 | |
397 | ||
398 | #endif /* __CONFIG_H */ |